FR2846789B1 - Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur

Info

Publication number
FR2846789B1
FR2846789B1 FR0213837A FR0213837A FR2846789B1 FR 2846789 B1 FR2846789 B1 FR 2846789B1 FR 0213837 A FR0213837 A FR 0213837A FR 0213837 A FR0213837 A FR 0213837A FR 2846789 B1 FR2846789 B1 FR 2846789B1
Authority
FR
France
Prior art keywords
semiconductor device
manufacturing
mos transistor
stop layer
residual stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0213837A
Other languages
English (en)
Other versions
FR2846789A1 (fr
Inventor
Pierre Morin
Jorge Regolini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0213837A priority Critical patent/FR2846789B1/fr
Priority to US10/701,165 priority patent/US7187038B2/en
Publication of FR2846789A1 publication Critical patent/FR2846789A1/fr
Application granted granted Critical
Publication of FR2846789B1 publication Critical patent/FR2846789B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
FR0213837A 2002-11-05 2002-11-05 Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur Expired - Fee Related FR2846789B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0213837A FR2846789B1 (fr) 2002-11-05 2002-11-05 Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur
US10/701,165 US7187038B2 (en) 2002-11-05 2003-11-04 Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0213837A FR2846789B1 (fr) 2002-11-05 2002-11-05 Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur

Publications (2)

Publication Number Publication Date
FR2846789A1 FR2846789A1 (fr) 2004-05-07
FR2846789B1 true FR2846789B1 (fr) 2005-06-24

Family

ID=32104469

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0213837A Expired - Fee Related FR2846789B1 (fr) 2002-11-05 2002-11-05 Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur

Country Status (2)

Country Link
US (1) US7187038B2 (fr)
FR (1) FR2846789B1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
US7164163B2 (en) * 2005-02-22 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with hybrid-strain inducing layer
EP1717864A1 (fr) * 2005-04-27 2006-11-02 STMicroelectronics ( Crolles 2) SAS Méthode pour gérer la configuration du stress dans le canal d'un transistor MOS et circuit intégré correspondant
JP2006324278A (ja) * 2005-05-17 2006-11-30 Sony Corp 半導体装置およびその製造方法
US20070013070A1 (en) * 2005-06-23 2007-01-18 Liang Mong S Semiconductor devices and methods of manufacture thereof
US7829978B2 (en) * 2005-06-29 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Closed loop CESL high performance CMOS device
US7485517B2 (en) * 2006-04-07 2009-02-03 United Microelectronics Corp. Fabricating method of semiconductor device
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US7585720B2 (en) * 2006-07-05 2009-09-08 Toshiba America Electronic Components, Inc. Dual stress liner device and method
US7675118B2 (en) * 2006-08-31 2010-03-09 International Business Machines Corporation Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
US20080087965A1 (en) * 2006-10-11 2008-04-17 International Business Machines Corporation Structure and method of forming transistor density based stress layers in cmos devices
JP5132943B2 (ja) * 2007-01-24 2013-01-30 パナソニック株式会社 半導体装置
US20090095991A1 (en) * 2007-10-11 2009-04-16 International Business Machines Corporation Method of forming strained mosfet devices using phase transformable materials
US8776514B2 (en) * 2007-12-14 2014-07-15 Lei Wu Electrothermal microactuator for large vertical displacement without tilt or lateral shift
KR102462134B1 (ko) 2015-05-19 2022-11-02 삼성전자주식회사 배선 구조물, 배선 구조물 형성 방법, 반도체 장치 및 반도체 장치의 제조 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332697A (en) * 1989-05-31 1994-07-26 Smith Rosemary L Formation of silicon nitride by nitridation of porous silicon
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5795833A (en) * 1996-08-01 1998-08-18 Taiwan Semiconductor Manufacturing Company, Ltd Method for fabricating passivation layers over metal lines
JPH113869A (ja) * 1997-06-11 1999-01-06 Nec Corp 半導体装置の製造方法
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6372569B1 (en) * 2000-01-18 2002-04-16 Chartered Semiconductor Manufacturing Ltd. Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance
US6580170B2 (en) * 2000-06-22 2003-06-17 Texas Instruments Incorporated Semiconductor device protective overcoat with enhanced adhesion to polymeric materials
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
US6573172B1 (en) * 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6762085B2 (en) * 2002-10-01 2004-07-13 Chartered Semiconductor Manufacturing Ltd. Method of forming a high performance and low cost CMOS device

Also Published As

Publication number Publication date
US7187038B2 (en) 2007-03-06
US20040135234A1 (en) 2004-07-15
FR2846789A1 (fr) 2004-05-07

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Effective date: 20070731