JP3884439B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP3884439B2 JP3884439B2 JP2004057977A JP2004057977A JP3884439B2 JP 3884439 B2 JP3884439 B2 JP 3884439B2 JP 2004057977 A JP2004057977 A JP 2004057977A JP 2004057977 A JP2004057977 A JP 2004057977A JP 3884439 B2 JP3884439 B2 JP 3884439B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- voltage
- vlow
- level conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
前記第1のデジタル信号が入力され、前記第1のデジタル信号の振幅を第2の電源電圧と同じ振幅に変換し、第2のデジタル信号として出力端子から出力するレベル変換回路と、前記第2の電源電圧で動作し、前記第2のデジタル信号が入力される第2の回路ブロックと、前記第2の電源電圧を抵抗で分圧し、その分圧電圧から上限がダイオードによって規定される基準電位を発生し、前記基準電位と前記第1の電源電圧を比較して、前記第1の電源電圧が所定の電圧レベルより低下した場合に、前記レベル変換回路の前記出力端子を所定の電位とする第1の信号を発生するモニター回路とを具備することを特徴とする。
図1は本発明の第1の実施形態に係るレベル変換回路の回路図、図2は図1中で第1の電源VLOWの出力を監視するモニタ回路MCの回路図、図3は図2のモニタ回路MCの出力値と電源電圧VHIGH,VLOWの関係を示す特性図である。
第2の実施形態は、第1の実施形態に対し、VLOWモニタ回路MCのレファレンス電位発生回路VREFの発生方法が異なっている。第1の実施形態では、単に第2の電源VHIGH−接地電位GND間の電圧を抵抗で分圧したものを使用していた。第2の実施形態では、図4に示すようにVREFノードにダイオードDIを接続している。
図8は第3の実施形態に係るレベル変換回路の回路図であり、図9はその出力値と電源電圧VHIGH,VLOWとの関係を示す特性図である。
MC…モニタ回路
INV1〜10…インバータ回路
MP1〜MP3…PMOSトランジスタ
MN1〜MN5…NMOSトランジスタ
DA…差動増幅器
Q1〜Q3…ダイオード接続のトランジスタ
R1〜R3、Rb,Rc…抵抗
BGR…バンドギャップレファレンス回路
FF1、FF2…フリップフロップ
DI,DQ1,DQN…ダイオード
Claims (5)
- 第1の電源電圧で動作し、前記第1の電源電圧と同じ振幅を有する第1のデジタル信号を出力する第1の回路ブロックと、
前記第1のデジタル信号が入力され、前記第1のデジタル信号の振幅を第2の電源電圧と同じ振幅に変換し、第2のデジタル信号として出力端子から出力するレベル変換回路と、
前記第2の電源電圧で動作し、前記第2のデジタル信号が入力される第2の回路ブロックと、
前記第2の電源電圧を抵抗で分圧し、その分圧電圧から上限がダイオードによって規定される基準電位を発生し、前記基準電位と前記第1の電源電圧を比較して、前記第1の電源電圧が所定の電圧レベルより低下した場合に、前記レベル変換回路の前記出力端子を所定の電位とする第1の信号を発生するモニター回路とを具備することを特徴とする半導体装置。 - 前記レベル変換回路の前記出力端子を前記所定の電位とすることにより、前記第2の回路ブロックが非活性化されることを特徴とする請求項1記載の半導体装置。
- 前記第1の電源電圧は前記第2の電源電圧より低いことを特徴とする請求項1記載の半導体装置。
- 前記第1の回路ブロックは、前記第1のデジタル信号の相補信号を作成するためのインバータを含み、前記レベル変換回路は前記相補信号が入力するフリップフロップとを含むことを特徴とする請求項1記載の半導体装置。
- 前記モニタ回路は、前記第1の電源電圧が前記所定の電圧レベルより低下した場合に、前記レベル変換回路の動作を遮断するとともに、前記レベル変換回路の前記出力端子を前記所定の電位とするための前記第1の信号を発生することを特徴とする請求項1記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004057977A JP3884439B2 (ja) | 2004-03-02 | 2004-03-02 | 半導体装置 |
US10/853,260 US7026855B2 (en) | 2004-03-02 | 2004-05-26 | Semiconductor device to prevent a circuit from being inadvertently active |
CN200510053190.4A CN1665138A (zh) | 2004-03-02 | 2005-03-02 | 半导体器件 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004057977A JP3884439B2 (ja) | 2004-03-02 | 2004-03-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005252481A JP2005252481A (ja) | 2005-09-15 |
JP3884439B2 true JP3884439B2 (ja) | 2007-02-21 |
Family
ID=34909079
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004057977A Expired - Fee Related JP3884439B2 (ja) | 2004-03-02 | 2004-03-02 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7026855B2 (ja) |
JP (1) | JP3884439B2 (ja) |
CN (1) | CN1665138A (ja) |
Cited By (1)
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---|---|---|---|---|
US10560084B2 (en) | 2017-09-08 | 2020-02-11 | Toshiba Memory Corporation | Level shift circuit |
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-
2004
- 2004-03-02 JP JP2004057977A patent/JP3884439B2/ja not_active Expired - Fee Related
- 2004-05-26 US US10/853,260 patent/US7026855B2/en not_active Expired - Fee Related
-
2005
- 2005-03-02 CN CN200510053190.4A patent/CN1665138A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10560084B2 (en) | 2017-09-08 | 2020-02-11 | Toshiba Memory Corporation | Level shift circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2005252481A (ja) | 2005-09-15 |
US20050195012A1 (en) | 2005-09-08 |
CN1665138A (zh) | 2005-09-07 |
US7026855B2 (en) | 2006-04-11 |
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