CN1095196C - 具有超浅端区的晶体管及其制造方法 - Google Patents

具有超浅端区的晶体管及其制造方法 Download PDF

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CN1095196C
CN1095196C CN95197621A CN95197621A CN1095196C CN 1095196 C CN1095196 C CN 1095196C CN 95197621 A CN95197621 A CN 95197621A CN 95197621 A CN95197621 A CN 95197621A CN 1095196 C CN1095196 C CN 1095196C
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semi
side wall
wall
conducting material
transistor
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CN1175321A (zh
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R·S·曹
C·－H·彻恩
C·－H·雅
K·R·维尔顿
P·A·佩卡恩
L·D·尧
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Intel Corp
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Intel Corp
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  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

具有超浅端区(214)的新型晶体管(200)及其制造方法。本发明的新型晶体管有一个源/漏扩展或端区(210)，该源/漏扩展或端区包括延伸到栅电极和突起的区域(216)下的超浅区(214)。

Description

具有超浅端区的晶体管及其制造方法
                      发明背景
                      发明领域
本发明涉及半导体集成电路，特别涉及超大规模亚微米晶体管的制造。
                     相关技术介绍
今天，确确实实有上百万个分立晶体管连在一起形成超大规模集成(VLSI)电路，例如微处理器，存储器，和特殊应用的集成电路(ICs)。目前，最先进的IC由大约三百万晶体管组成，例如栅长度级别为0.5μm的金属氧化物半导体(MOS)场效应晶体管。为了继续增加未来的集成电路的复杂性和计算能力，必须将更多的晶体管封装到单个IC中(即，晶体管的密度必须增加)。这样，未来的超大规模集成(ULSI)电路将需要有效栅长度小于0.1μm的极短沟道晶体管。然而，常规MOS晶体管的制造方法和结构不能简单地“按比例缩小”来生产更小的晶体管以实现高密度集成。
常规MOS晶体管100的结构显示在图1中。晶体管100包括栅电极102，一般为多晶硅，在栅介质层104上形成，而栅介质层104是在硅衬底106上形成。一对源/漏扩展区或端区110在衬底106的上表面上形成，并与栅电极102的外边缘对准。端区110一般采用已知的离子注入技术形成。与栅电极102的相对侧相邻并位于端区110之上处形成的是一对侧壁间隔层108。然后通过离子注入在衬底106内形成一对源/漏区120，并基本上与侧壁间隔层108的外边缘对准。
随着晶体管100的栅长度按比例缩小，为了制造更小的晶体管，端区110扩展进入衬底106的深度也必须按比例缩小(即，降低)，以便改善制造的晶体管的穿通特性。然而，端区110的长度必须大于0.10μm以确保后来的大剂量的深源/漏注入不会淹没和覆盖端区110。因此，如图1所示，使用常规方法制造的小比例晶体管中，端区110又浅又长。由于端区110又浅又长，端区110存在实际寄生电阻。寄生电阻反过来影响(减小)晶体管的驱动电流。
因此，实际需要的是具有低阻超浅端区的新型晶体管，和VLSI的制造方法。
                       发明概述
下面介绍的是带低阻超浅端区的新型晶体管及其制造方法。根据本发明的优选方法，栅介质层在半导体衬底的第一表面上形成。接下来，栅电极在栅介质层上形成。然后第一对侧壁间隔层邻接栅电极的相对侧面形成。之后，在半导体衬底内形成一对凹槽，并与第一对侧壁间隔层的外边缘对准。接下来，将半导体材料选择性地淀积到凹槽中，以便半导体材料在半导体衬底的第一表面之上和之下扩展。然后掺杂剂由半导体材料中扩散进第一对侧壁间隔层下的衬底中，形成超浅端区。之后在邻接第一对侧壁间隔层的外边缘的半导体材料上形成第二对侧壁间隔层。接下来，以与第二对侧壁间隔层的外边缘对准的方式进行深注入，形成深结源/漏接触区。最后，在制备的晶体管的源/漏区和栅电极上形成硅化物。
                       附图简述
图1显示的是常规晶体管的剖面图。
图2显示的是本发明的具有低阻超浅端区的晶体管的剖面图。
图3a显示的是在衬底上形成的栅电极的相对侧上形成第一对侧壁间隔层的剖面图。
图3b显示的是图3a的衬底中形成凹槽区剖面图。
图3c显示的是在图3b的衬底上淀积半导体材料的剖面图。
图3d显示的是掺杂剂固态扩散进图3c的衬底中的剖面图。
图3e显示的是在图3d的衬底上形成第二对侧壁间隔层的剖面图。
图3f显示的是在图3d的衬底中形成深结源/漏接触区的剖面图。
图4显示的是带有浅结淀积源/漏接触区的低阻超浅端区晶体管的本发明另一优选实施例的剖面图。
图5显示的是带有淀积半导体掩埋沟道区的低阻超浅端区晶体管的本发明另一优选实施例的剖面图。
图6显示的是带有垂直和水平地扩散的超浅端区的低阻超浅端区晶体管的本发明另一优选实施例的剖面图。
                    本发明的详细描述
下面介绍的是带低阻超浅端区的新型晶体管及其制造方法。为了彻底地理解本发明，在以下的说明中列举了大量的具体细节，例如具体的材料、范围和工艺等等。然而，对于本领域的普通技术人员来说，很明显不采用这些具体细节也可以实践本发明。另外，没有特别详细地介绍已知的半导体设备和工艺以免给本发明带来不必要的混淆。
具有低阻超浅端区的新型晶体管200的本发明优选实施例显示在图2中。晶体管200在硅衬底或阱201上形成。栅介质层202在衬底201的表面203上形成，而栅电极204在栅介质层202上形成。第一对薄侧壁间隔层206在栅电极204的相对侧上形成(间隔层206沿栅电极204的宽度方向)。晶体管200也包括基本上更大些的第二对侧壁间隔层208，而该第二对侧壁间隔层邻接第一对侧壁间隔层206的外边缘形成。晶体管200包括一对源/漏区211，每个包括一对端区或源/漏扩展区210和源/漏接触区212。
端区或源/漏扩展区210限定为位于第二侧壁间隔层208、第一侧壁间隔层206、和栅电极204外边缘下的源/漏区。端区210包括超浅端区部分214和突起的端区部分216。超浅端区214包括掺杂的半导体衬底215，而该掺杂的半导体衬底是由“向外扩散”的掺杂剂从选择性淀积的半导体材料217进入衬底201中形成。超浅端区214由第一侧壁间隔层206下扩展到栅电极204外边缘。对于有效栅长度大约为0.10微米(或1000)的晶体管，超浅端区214在栅电极204下延伸大约100更适宜。此外，对于0.10μm的有效栅长度，超浅端区214延伸进入衬底表面203下衬底201内的深度最好小于500。应该知道，由于本发明采用了新型的制造方法，超浅端区214的特征为典型的突变结。
晶体管200的端区210也包括突起的端区部分216。突起的端区部分21 6位于第二侧壁间隔层208的下面，并与第一对侧壁间隔层206的外边缘邻接。突起的端区216最好由掺杂的半导体材料217形成，而该掺杂的半导体材料217是在半导体衬底215的表面203之上和之下选择性淀积形成。由于突起的端区216的部分在半导体衬底的表面203之上形成，所以突起的端区216被称为“突起的”。突起的端区可显著地减少晶体管200的寄生电阻，从而改善它的性能。
一对源/漏接触区212邻接第二侧壁间隔层208的外边缘形成。源/漏接触区212为深结源/漏接触。源/漏接触区212由离子注入或将附加的掺杂剂扩散到区域220中形成，源/漏接触区212包括选择性淀积的半导体材料217、“向外扩散的”并与第二侧壁间隔层208的外边缘对准的掺杂的半导体衬底215和衬底201。源/漏接触区212为部分突起的源/漏区。硅化物218最好在源/漏区212上形成，以便减少晶体管200的接触电阻。此外，根据本发明，第一半导体材料217最好淀积在栅电极204的上表面。硅化物218也最好在栅电极204的淀积的半导体材料217上形成，以帮助改善接触电阻。
应该知道，本发明有价值的特征在于晶体管200包括端区或源/漏扩展区210，且为超浅的和突起的。这样，晶体管200就会有很低寄生电阻的浅端区。晶体管200的新型结构允许端区按需要缩小比例，用于制造有效栅长度小于0.15μm的晶体管200。由于本发明的新型端区结构，晶体管200具有良好的穿通特性并且VT滚降减小。此外，由于有端区210，晶体管200具有低的寄生电阻，从而产生良好的驱动电流。
图3a-3f显示的是具有低电阻超浅端区的晶体管当前的优选制造方法。优选的制造方法将针对PMOS晶体管的制造进行介绍。应该知道，优选的方法同样适用于导电类型简单相反的NMOS器件的制造。如图3a所示，本发明的PMOS晶体管最好在掺杂浓度在1×1017/cm3到1×1019/cm3之间的n型衬底或阱300上制造。应该知道，衬底300还可以包括淀积的半导体材料的顶层或多层。根据本发明，衬底限定为晶体管在其上制造的初始材料。
根据本发明，首先，栅介质层302在衬底300的上表面304上形成。栅介质层302最好为厚度在20-50之间的氮化物-氧化物(nitrided)层。应该知道，如有需要，其它已知的栅介质层，例如氧化物、氮化物、及它们的结合，也可以使用。接下来，在栅介质层302上形成栅电极306。栅电极306最好使用已知的光刻技术由厚度为1000-3500覆盖淀积的多晶硅层构图成栅电极306形成。应该知道，其它已知的构图技术也可用于形成栅电极306的图形，包括亚微米光刻技术和亚光刻构图技术，例如在审查中专利申请中所介绍，名称为“反转缓冲层晶体管”(Inverted Spacer Transistor)，申请日为1994年8月10日，序列号为08/288,332，已转让给本受让人。此外，虽然栅电极306最好为多晶硅，但如有必要，栅电极306也可以为金属栅、单晶硅栅、或它们的结合。
下一步，也显示在图3a中，第一侧壁间隔层308覆盖淀积在衬底300和栅电极306的顶面和侧面。间隔层308最好为采用已知的工艺淀积的二氧化硅层，厚度大约在50-500之间，最好为200。应该知道，如有必要，其它绝缘层，例如氮化硅和氮化物-氧化物等等，也可用作间隔层308。应该知道，形成的间隔层308的厚度必须足以电隔离栅电极306与随后淀积的半导体材料。此外，从后面可知道，侧壁间隔层308的厚度限定了制造的晶体管的最终间隔层的厚度和超浅端区部分的最小长度。
接下来，如图3b中所示，使用任何已知的技术对第一侧壁间隔层308进行各向异性干法腐蚀，形成沿栅电极306宽度方向的第一对侧壁间隔层310。
之后，如图3b中所示，使用任何已知的技术对衬底300进行各向异性的腐蚀，例如含有比例为2∶1的C2F6和He的化学物质的反应离子腐蚀(RIE)，分别在硅衬底300中形成一对凹槽312，并与第一对侧壁间隔层310的外边缘对准。应该注意的是，在硅衬底凹槽腐蚀期间，多晶硅栅电极306被部分腐蚀。栅电极306和第一对侧壁间隔层310作为掩模可防止位于其下的硅衬底表面304被腐蚀。这样，本发明的凹槽腐蚀可与第一对侧壁间隔层310的外边缘自对准。根据本发明的优选实施例，腐蚀衬底300形成凹槽区312，其深度大约在20-1000之间，衬底表面304下的深度最好为200。应该知道，凹槽区312的深度限定了制造的晶体管的超浅端区延伸到衬底300内的最小深度。凹槽区越深，晶体管的超浅端区延伸到衬底300中的部分就越深。
接下来，根据本发明的优选实施例，如图3c中所示，半导体材料314选择性地淀积到凹槽312中以及栅电极306的上表面。选择性地淀积半导体材料314是为了仅在露出硅的部位例如衬底300和多晶硅栅电极306上形成半导体材料314。在侧壁间隔层310上没有形成半导体材料314。因此侧壁间隔层310可将凹槽312中形成的半导体材料314与栅电极306电隔离开。半导体材料314形成的厚度在200-2000之间，最好约为600。这样，在半导体衬底300的表面304之上和之下都形成了半导体材料314。此外，半导体材料314适宜就地掺杂p型杂质，例如硼，浓度级别在1×1018/cm3到5×1020/cm3之间，最好浓度约为1×1020/cm3。此外，应该知道，半导体材料不必就地掺杂，通过离子注入或扩散淀积后，掺杂到所需的导电率级别。例如，在制造CMOS或BiMOS部分时，有必要在淀积后掺杂半导体材料314，以便可使用标准的光刻胶掩模蔽技术分别形成CMOS电路中PMOS和NMOS器件的p型导电半导体材料和n型导电半导体材料。
应该注意到半导体材料314的厚度和掺杂浓度级别决定制造的晶体管突起的端区部分的电阻率。半导体材料314越厚并且掺杂浓度越高，生成的晶体管的寄生电阻就越低。然而，当反向电压施加到栅电极306和半导体材料314上时，产生反向电容(即，米勒电容)变大。半导体材料314越厚并且掺杂浓度越高，米勒电容就越大。因此，必须在晶体管的寄生电阻和它的米勒电容之间做一折衷。
根据本发明，半导体材料314最好为硅/锗半导体合金，其中锗占合金的大约10-50％。硅/锗半导体合金可以在H2的气氛中分解SiH2Cl2和GeH4得到，温度在500-800℃之间，最好是600℃。优选这种半导体材料是由于在淀积过程中它显示出对硅良好的选择性，可使本发明更易制造。此外，这种硅/锗半导体合金具有许多“缺陷”或“位错”，有助于掺杂剂在固态扩散中穿过半导体材料。应该知道，任何可以选择性淀积的半导体材料都可用于形成半导体材料314。例如，半导体材料314可以选择性淀积多晶硅，该多晶硅是在H2的气氛中，温度在600-900℃之间，分解SiH2Cl2和HCl得到，或可以选择性淀积任何已知技术得到的单晶硅。
下一步，根据本发明，如图3d中所示，p型杂质或掺杂剂由半导体材料314扩散进入半导体衬底300中形成扩散的半导体区316。杂质向外扩散形成的扩散的半导体区316的浓度级别大致等于淀积的半导体材料314的浓度级别。杂质在第一薄侧壁间隔层310下横向地(水平地)扩散直到杂质至少达到栅电极306的外边缘，最好延伸到栅电极306下大约100处。横向地延伸到第一侧壁间隔层310和栅电极306下面的那部分扩散的半导体区316就是制造的晶体管的超浅端区部分。应该知道，杂质向外扩散也将杂质更深地(垂直地)扩散到衬底300中。每横向扩散200，掺杂剂则垂直地向衬底300内大约扩散200。因此，根据本发明的优选实施例，对于0.10μm的有效栅长度超浅端区317的长度大约为300并且深度大约为500(或0.05μm)。
根据本发明的优选实施例，使用快速加热工艺(RTP)在氮气(N2)气氛中，在温度800℃到1000℃之间加热5到60秒，形成半导体材料314，之后直接进行固态扩散步骤。应该知道，本发明的固态扩散步骤不必在半导体材料314形成后直接进行，可以在以后的工艺步骤中使用的热循环期间进行。
应该知道，本发明的关键特征是半导体材料314在半导体衬底表面304的下面形成。也就是，在本发明中，掺杂剂源315放置在衬底300中直接与要形成的超浅端区317相邻。这样，在固态扩散步骤中，掺杂剂能够很容易地沿一个方向(横向地)扩散到第一侧壁间隔层310下和多晶硅栅电极306外边缘的下面。这就产生了超浅端区317，其特征为衬底300的很明显的突变结。这种突变结改善了制造的晶体管的穿通特性。此外，应该知道，采用固态扩散形成的超浅端区317，比采用现在标准的离子注入技术制造出的端区导电率更高。端区浓度更高可改善器件的性能并降低器件的寄生电阻。
接下来，如图3e中所示，第二对侧壁间隔层318在淀积的半导体材料314上邻近第一侧壁间隔层310的外边缘形成。最好采用各向异性干法腐蚀热壁工艺形成的氮化硅的共形层，从而形成第二侧壁间隔层318。与侧壁间隔层310一样，如有必要，第二侧壁间隔层318可使用任何一种已知的技术形成。第二侧壁间隔层318基本上比第一侧壁间隔层310厚，形成的厚度在500-2500之间，最好是1800。
下一步，如图3f中所示，形成源/漏接触区319完成晶体管340的制造。形成第二侧壁间隔层318后，如图3e中所示，对衬底进行标准和已知的离子注入并退火，其中将例如硼等p型导电杂质，注入到淀积的半导体材料314、扩散的硅区316、和半导体衬底300中。离子注入步骤形成的源/漏接触区322的p型导电率级别最好在1×1019/cm3到5×1020/cm3之间，并且源/漏接触区319的总厚度在0.15-0.25μm之间。此外，如果在形成多晶硅栅电极306期间未预先掺杂，那么离子注入步骤也可用于掺杂多晶硅栅电极306。应该知道，形成的第二侧壁间隔层318必须足够的厚和宽以提供足够的掩模，防止源/漏接触区319很深、高剂量的离子注入覆盖制造的端区321。
之后，根据本发明的优选实施例，使用自对准硅化物工艺(Salicide)将硅化物320形成到源/漏接触区319上淀积的半导体材料314上和栅电极306上淀积的半导体材料314上，从而显著地减少器件的接触电阻。在优选的自对准硅化物(Salicide)工艺中，先将钛层覆盖淀积在整个器件上。然后对器件进行温度循环使淀积的钛层和任何暴露的硅表面(即，栅电极306上的半导体材料314和源/漏接触区319上的半导体材料314)发生反应，形成硅化钛320(即，TiSix)。应该知道，钛并不与第二侧壁间隔层318发生反应。接下来，采用选择性腐蚀将未反应的钛从第二侧壁间隔层318上除去，留下硅化钛320。应当知道，其它耐高温金属，例如，钨，可用于形成硅化物320。此外，应该注意的是第二侧壁间隔层318必须足够厚以防止硅化物侵蚀造成栅电极与源/漏接触区电短路。完成硅化物工艺后，采用优选方法制造的具有低阻超浅端区的新型晶体管340也就完成了。
图4为本发明的另一优选实施例的剖面图。图4为带有低阻超浅端区410和一对部分突起的浅结源/漏接触区412的MOS晶体管400。以分别在图3a-3e中图示并介绍及附带说明的晶体管340的相同方式制造晶体管400。形成第二侧壁间隔层318之后，进行第二次选择淀积半导体材料形成第二层半导体材料420，该第二层半导体材料420位于与第二侧壁间隔层318相邻接的第一淀积的半导体材料314的上表面和栅电极306上形成的半导体材料314上。形成的第二层半导体材料420要足够厚，厚度要在100到1500之间，浓度级别要足够高，浓度要在1×1019/cm3到5×1020/cm3之间，从而为制造的器件提供足够的源/漏接触区412。应该知道，形成的源/漏接触区412必须足够厚以确保不产生金属接触尖刺。第二层半导体材料420最好由硅/锗合金形成，该硅/锗合金掺杂p型杂质，例如硼，并达到所需的导电率级别。应该知道，第二侧壁间隔层318需要足够厚，以防止第二层半导体材料420和栅电极306之间的过大的米勒电容增长，对器件特性造成不利影响。
此时最好使用化学-机械抛光工艺从栅电极306的上表面除去第二层半导体材料420，以改善制造的晶体管的形貌。最后，使用自对准硅化物(Salicide)工艺将硅化物320形成到第二次淀积的半导体材料420上和栅电极306上的半导体材料314上。
图5为本发明的另一优选实施例的剖面图。图5图示了带有低阻超浅端区510的埋沟道MOS晶体管500。晶体管500可以用与晶体管340相同的方式制造，不同的是半导体衬底300也包括上部淀积的半导体材料524，其厚度在200-1000之间，掺杂成p型导电，其浓度在1×1017/cm3到1×1019cm3之间。应该知道，本发明优选的范围与淀积的半导体材料524的上表面526相关，在这个实施例中上表面526被认为是半导体衬底300的上表面。应该知道，淀积的半导体材料524不必是单一半导体材料，可以包括多种不同掺杂和不同类型的半导体材料。埋沟道晶体管500显示出沟道载流子的迁移率增加，从而改善了器件的驱动电流和开关速度。
图6为本发明的另一优选实施例的剖面图。图6显示带有低阻超浅端区610的埋沟道MOS晶体管600。晶体管600与本发明公开的其它实施例不同，不同之处在于选择淀积半导体材料319之前没在半导体衬底300中形成凹槽312。取而代之的是，半导体材料314直接淀积在半导体衬底300的上表面304上。其它的制造步骤，如在图3b-3f中和附带的说明中所公开的，用于完成晶体管600的制备。应该知道，对于晶体管600，没有半导体材料凹进衬底300中，因此固态扩散步骤必须先驱使p型掺杂剂向下(垂直地)扩散到衬底300中，然后驱使它们在第一侧壁间隔层310下面横向地(水平地)扩散到栅电极306的外边缘，形成晶体管600的超浅低阻端区610。虽然已显示出这种扩散工艺能生产高性能的器件，但当掺杂剂沿单一方向由半导体材料部分地退进衬底300中时，超浅低阻端区610的结不是突变的。虽然晶体管600没有象其它的实施例那样有突变的超浅低阻端区，但去掉凹槽步骤确实降低了工艺的复杂性并降低了成本。
以上介绍了本发明的许多替换的实施例和细节，然而，本领域的普通技术人员应该理解，在一个实施例中的许多特征同样适用于其它实施例。此外，虽然介绍了许多特定的范围、材料、和浓度，但应该知道，这些特定的范围、材料、和浓度并不能作为一种限制。此外，本领域的普通技术人员有能力改变本发明的比例形成更大和更小的器件。本发明并不受本发明的详细介绍的限制，而由以下的权利要求所决定。
在此，我们已经对具有超浅端区的新型晶体管及其制造方法进行了介绍。

Claims (30)

1.一种形成晶体管的方法，包括以下步骤：
在半导体衬底的第一表面上形成栅介质层；
在所述栅介质层上形成栅电极；
邻接所述栅电极的相对侧形成第一对侧壁间隔层；
在所述第一表面下的所述半导体衬底中形成一对凹槽，与所述第一对侧壁间隔层的外边缘对准；及
在所述凹槽对中形成第一半导体材料以形成第一对源/漏区。
2.如权利要求1所述的方法，还包括以下步骤：
将掺杂剂从所述第一半导体材料中扩散到所述第一对侧壁间隔层下的所述衬底中。
3.如权利要求2所述的方法，还包括以下步骤：
在邻近所述第一侧壁间隔层的外边缘的所述半导体材料上形成第二对侧壁间隔层。
4.如权利要求3所述的方法，还包括以下步骤：
将离子淀积到所述第一半导体材料和所述衬底中，与所述第二对侧壁间隔层的外边缘对准。
5.如权利要求4所述的方法，其特征在于，所述离子通过离子注入淀积。
6.如权利要求3所述的方法，还包括以下步骤：
在所述半导体材料上形成硅化物，与所述第二对侧壁间隔层的外边缘对准。
7.如权利要求3所述的方法，还包括以下步骤：
在所述第一半导体材料上形成第二半导体材料，与所述第二对侧壁间隔层的外边缘对准。
8.如权利要求7所述的方法，还包括以下步骤：
在所述第二半导体材料上形成硅化物。
9.一种形成晶体管的方法，包括以下步骤：
在半导体衬底上形成栅介质层；
在所述栅介质层上形成栅电极；
邻近所述栅电极的相对侧形成第一对侧壁间隔层；
在所述半导体衬底上形成第一掺杂的半导体材料，与所述第一对侧壁间隔层的外边缘对准；
将掺杂剂从所述第一半导体材料中扩散到所述第一对侧壁间隔层下的所述衬底中，形成一对顶区；在邻近所述第一对侧壁间隔层的外边缘的所述第一半导体材料上形成第二对侧壁间隔层。
将离子注入到所述半导体材料和所述衬底中，与所述第二对侧壁间隔层的外边缘对准，以形成源/漏接触区。
10.如权利要求9所述的方法，其特征在于，第一对间隔层的厚度在50-500之间。
11.如权利要求9所述的方法，其特征在于，通过离子注入步骤掺杂所述栅电极。
12.如权利要求9所述的方法，还包括以下步骤：
在所述第一半导体材料上形成硅化物，与所述第二对侧壁间隔层的外边缘对准。
13.如权利要求9所述的方法，还包括以下步骤：
在所述第一半导体材料上形成第二半导体材料，与所述第二对侧壁间隔层的外边缘对准。
14.如权利要求13所述的方法，还包括以下步骤：
在所述第二半导体材料上形成硅化物。
15.一种晶体管，包括：
在半导体衬底的第一表面形成的栅介质层；
在所述栅介质层上形成的栅电极；
邻近所述栅电极的相对侧形成的第一对侧壁间隔层；
在所述衬底中形成的第一对超浅端区，该端区延伸在所述第一对侧壁间隔层和所述栅电极的相对侧的下面；
一对突起的端区，该区与所述第一对侧壁间隔层的外边缘对准形成，其中所述一对突起的端区包括第一淀积的半导体材料，该半导体材料至少部分在所述半导体衬底的所述第一表面之上和之下。
16.如权利要求15所述的晶体管，其特征在于，所述第一淀积的半导体材料延伸在所述半导体衬底的所述第一表面下。
17.如权利要求15所述的晶体管，还包括：
邻接所述第一对侧壁间隔层的外边缘形成第二对侧壁间隔层，所述第二对侧壁间隔层在所述的一对突起的端区上形成。
18.如权利要求15所述的晶体管，还包括：
与所述第二对侧壁间隔层对准形成一对源/漏接触区，在所述衬底内所述源/漏接触区对比所述突起的端区对形成得更深。
19.如权利要求17所述的晶体管，还包括在所述源/漏接触区对和所述栅电极上形成的硅化物。
20.如权利要求16所述的晶体管，还包括在邻接所述第二对侧壁间隔层的外边缘的第一淀积半导体材料上形成的第二半导体材料。
21.如权利要求20所述的晶体管，还包括在所述第二半导体材料上形成的硅化物。
22.如权利要求15所述的晶体管，其特征在于，所述的一对突起的端区包括淀积的多晶硅。
23.如权利要求15所述的晶体管，其特征在于，所述突起的端区对包括淀积的单晶硅。
24.如权利要求15所述的晶体管，其特征在于，所述突起的端区对包括淀积的硅/锗半导体。
25.如权利要求15所述的晶体管，其特征在于，所述第一对侧壁间隔层的厚度大约在50-500之间。
26.如权利要求15所述的晶体管，其特征在于，第二对侧壁间隔层的厚度大约在500-2500之间。
27.如权利要求15所述的晶体管，其特征在于，所述第二对源/漏区在所述半导体衬底的所述第一表面下大约20-1000延伸。
28.如权利要求15所述的晶体管，其特征在于，所述第一对源/漏区在所述半导体衬底的所述第一表面下的深度为20-1000之间，且长度大于100。
29.一种形成晶体管的方法，包括以下步骤：
在半导体衬底的第一表面上形成栅介质层；
在所述栅介质层上形成栅电极；
在所述栅电极的相对侧沿横向形成一对侧壁间隔层；
在所述侧壁间隔层的相对侧上的半导体衬底中形成一对凹槽；及
通过所述凹槽形成一对源/漏区。
30.一种形成晶体管的方法，包括以下步骤：
在半导体衬底的第一表面上的栅介质层上形成栅电极；
邻接所述栅电极的相对侧形成一对侧壁间隔层；
在所述半导体衬底中形成一对凹槽，与所述一对侧壁间隔层的外边缘对准；及
通过所述凹槽对形成一对源/漏区。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368792B2 (en) 2003-05-14 2008-05-06 Samsung Electronics Co., Ltd. MOS transistor with elevated source/drain structure
CN100449780C (zh) * 2003-06-27 2009-01-07 英特尔公司 具有凸起的结区域的pmos晶体管
CN102468164A (zh) * 2010-10-29 2012-05-23 中国科学院微电子研究所 晶体管及其制造方法

Families Citing this family (270)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3256084B2 (ja) 1994-05-26 2002-02-12 株式会社半導体エネルギー研究所 半導体集積回路およびその作製方法
JP3761918B2 (ja) * 1994-09-13 2006-03-29 株式会社東芝 半導体装置の製造方法
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US6720627B1 (en) * 1995-10-04 2004-04-13 Sharp Kabushiki Kaisha Semiconductor device having junction depths for reducing short channel effect
JP4027447B2 (ja) * 1996-04-24 2007-12-26 株式会社ルネサステクノロジ 半導体装置の製造方法
US5811350A (en) * 1996-08-22 1998-09-22 Micron Technology, Inc. Method of forming contact openings and an electronic component formed from the same and other methods
US5827769A (en) * 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
US5869866A (en) 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
US5869879A (en) * 1996-12-06 1999-02-09 Advanced Micro Devices, Inc. CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
JPH10173177A (ja) * 1996-12-10 1998-06-26 Mitsubishi Electric Corp Ｍｉｓトランジスタの製造方法
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP2925008B2 (ja) * 1997-01-30 1999-07-26 日本電気株式会社 半導体装置の製造方法
US6197645B1 (en) * 1997-04-21 2001-03-06 Advanced Micro Devices, Inc. Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls
US6518155B1 (en) * 1997-06-30 2003-02-11 Intel Corporation Device structure and method for reducing silicide encroachment
US6777759B1 (en) 1997-06-30 2004-08-17 Intel Corporation Device structure and method for reducing silicide encroachment
US6010954A (en) * 1997-07-11 2000-01-04 Chartered Semiconductor Manufacturing, Ltd. Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices
KR100302187B1 (ko) * 1997-10-08 2001-11-22 윤종용 반도체장치제조방법
US6429481B1 (en) 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
JP2967477B2 (ja) * 1997-11-26 1999-10-25 日本電気株式会社 半導体装置の製造方法
US7105411B1 (en) * 1997-12-18 2006-09-12 Micron Technology, Inc. Methods of forming a transistor gate
JP2002509361A (ja) * 1997-12-18 2002-03-26 マイクロン テクノロジー， インク． 半導体製造方法及び電界効果トランジスタ
US6121100A (en) * 1997-12-31 2000-09-19 Intel Corporation Method of fabricating a MOS transistor with a raised source/drain extension
KR100257075B1 (ko) * 1998-01-13 2000-05-15 김영환 반도체 소자 및 그의 제조방법
US6153456A (en) * 1998-01-14 2000-11-28 Vlsi Technology, Inc. Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask
US6177323B1 (en) * 1998-03-02 2001-01-23 Texas Instruments - Acer Incorporated Method to form MOSFET with an elevated source/drain for PMOSFET
US5989967A (en) * 1998-04-30 1999-11-23 Advanced Micro Devices, Inc. Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length
KR100475034B1 (ko) * 1998-06-08 2005-05-27 삼성전자주식회사 엘리베이티드소오스/드레인영역을갖는모스트랜지스터및그제조방법
US6124610A (en) 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
KR100343135B1 (ko) 1998-07-24 2002-09-18 삼성전자 주식회사 단채널효과를개선한모스트랜지스터제조방법
US6261948B1 (en) 1998-07-31 2001-07-17 Micron Technology, Inc. Method of forming contact openings
US6198142B1 (en) 1998-07-31 2001-03-06 Intel Corporation Transistor with minimal junction capacitance and method of fabrication
US6380023B2 (en) 1998-09-02 2002-04-30 Micron Technology, Inc. Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits
US5923986A (en) * 1998-09-17 1999-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a wide upper top spacer to prevent salicide bridge
JP2000156502A (ja) * 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US6887762B1 (en) 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6124627A (en) * 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
JP2003526198A (ja) * 1998-12-16 2003-09-02 インテル・コーポレーション 電界効果トランジスタのチャネル領域へのシリサイドの侵入を防ぐための基板のアモルファス化
JP4068746B2 (ja) * 1998-12-25 2008-03-26 株式会社ルネサステクノロジ 半導体集積回路装置
KR20000050568A (ko) * 1999-01-12 2000-08-05 윤종용 융기된 소스/드레인 구조를 갖는 모스 트랜지스터 및 그 제조방법
KR100308133B1 (ko) * 1999-01-12 2001-09-26 김영환 듀얼 게이트 모스 트랜지스터 제조방법
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
KR20000065719A (ko) * 1999-04-08 2000-11-15 김영환 반도체 소자 및 그 제조방법
KR100332106B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 제조 방법
WO2001003200A1 (de) * 1999-06-30 2001-01-11 Infineon Technologies Ag Isolation von gate-elektroden und herstellungsverfahren
US6737710B2 (en) * 1999-06-30 2004-05-18 Intel Corporation Transistor structure having silicide source/drain extensions
DE19943114B4 (de) * 1999-09-09 2007-12-27 Infineon Technologies Ag Verfahren zur Herstellung eines MOS-Transistors
KR100341182B1 (ko) * 1999-11-30 2002-06-20 윤종용 반도체소자의 모스 트랜지스터 형성방법
US6541343B1 (en) * 1999-12-30 2003-04-01 Intel Corporation Methods of making field effect transistor structure with partially isolated source/drain junctions
US6448129B1 (en) * 2000-01-24 2002-09-10 Micron Technology, Inc. Applying epitaxial silicon in disposable spacer flow
CN1366711A (zh) * 2000-02-17 2002-08-28 皇家菲利浦电子有限公司 具有硅－锗(Sii－x－Gex)门极MOS晶体管的集成CMOS电路的半导体装置及其生产方法
US6274420B1 (en) * 2000-02-23 2001-08-14 Advanced Micro Devices, Inc. Sti (shallow trench isolation) structures for minimizing leakage current through drain and source silicides
US6420250B1 (en) * 2000-03-03 2002-07-16 Micron Technology, Inc. Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates
US6331486B1 (en) 2000-03-06 2001-12-18 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
KR100628253B1 (ko) * 2000-08-09 2006-09-27 매그나칩 반도체 유한회사 반도체 소자의 자기 정렬 실리사이드 형성방법
JP2002124665A (ja) * 2000-10-12 2002-04-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6426247B1 (en) * 2001-01-17 2002-07-30 International Business Machines Corporation Low bitline capacitance structure and method of making same
US6323073B1 (en) * 2001-01-19 2001-11-27 United Microelectronics Corp. Method for forming doped regions on an SOI device
US6767777B2 (en) * 2001-02-06 2004-07-27 Texas Instruments Incorporated Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers
US6380043B1 (en) * 2001-02-12 2002-04-30 Advanced Micro Devices, Inc. Low temperature process to form elevated drain and source of a field effect transistor having high-K gate dielectric
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6670263B2 (en) * 2001-03-10 2003-12-30 International Business Machines Corporation Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
US6506650B1 (en) * 2001-04-27 2003-01-14 Advanced Micro Devices, Inc. Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile
US6541317B2 (en) * 2001-05-03 2003-04-01 International Business Machines Corporation Polysilicon doped transistor
US20020171107A1 (en) * 2001-05-21 2002-11-21 Baohong Cheng Method for forming a semiconductor device having elevated source and drain regions
US6413829B1 (en) * 2001-06-01 2002-07-02 Advanced Micro Devices, Inc. Field effect transistor in SOI technology with schottky-contact extensions
US6465847B1 (en) * 2001-06-11 2002-10-15 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
US6614079B2 (en) * 2001-07-19 2003-09-02 International Business Machines Corporation All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
WO2003015142A2 (en) * 2001-08-06 2003-02-20 Massachusetts Institute Of Technology Formation of planar strained layers
US6974735B2 (en) 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices
US6891209B2 (en) * 2001-08-13 2005-05-10 Amberwave Systems Corporation Dynamic random access memory trench capacitors
JP2003086798A (ja) * 2001-09-13 2003-03-20 Nec Corp 半導体装置およびその製造方法
JP2003100769A (ja) * 2001-09-20 2003-04-04 Nec Corp 半導体装置およびその製造方法
US6831292B2 (en) * 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003028106A2 (en) 2001-09-24 2003-04-03 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
US6649460B2 (en) 2001-10-25 2003-11-18 International Business Machines Corporation Fabricating a substantially self-aligned MOSFET
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
KR100406537B1 (ko) * 2001-12-03 2003-11-20 주식회사 하이닉스반도체 반도체장치의 제조 방법
JP2003188274A (ja) * 2001-12-19 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
US6891266B2 (en) * 2002-02-14 2005-05-10 Mia-Com RF transition for an area array package
US20030166323A1 (en) * 2002-03-01 2003-09-04 Infineon Technologies North America Corp. Raised extension structure for high performance cmos
US6716710B1 (en) * 2002-04-19 2004-04-06 Advanced Micro Devices, Inc. Using a first liner layer as a spacer in a semiconductor device
US6537885B1 (en) * 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
AU2003238963A1 (en) 2002-06-07 2003-12-22 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
AU2003247513A1 (en) * 2002-06-10 2003-12-22 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US20040033677A1 (en) * 2002-08-14 2004-02-19 Reza Arghavani Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
US6911695B2 (en) * 2002-09-19 2005-06-28 Intel Corporation Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain
DE10246718A1 (de) * 2002-10-07 2004-04-22 Infineon Technologies Ag Feldeffekttransistor mit lokaler Source-/Drainisolation sowie zugehöriges Herstellungsverfahren
US6727136B1 (en) * 2002-10-18 2004-04-27 Advanced Micro Devices, Inc. Formation of ultra-shallow depth source/drain extensions for MOS transistors
US6703648B1 (en) 2002-10-29 2004-03-09 Advanced Micro Devices, Inc. Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication
FR2846789B1 (fr) * 2002-11-05 2005-06-24 St Microelectronics Sa Dispositif semi-conducteur a transistors mos a couche d'arret de gravure ayant un stress residuel ameliore et procede de fabrication d'un tel dispositif semi-conducteur
KR100911986B1 (ko) 2002-12-23 2009-08-13 매그나칩 반도체 유한회사 반도체 소자의 제조 방법
US20040154083A1 (en) * 2002-12-23 2004-08-12 Mcvicker Henry J. Sports pad closure system with integrally molded hooks
KR100641494B1 (ko) * 2002-12-30 2006-10-31 동부일렉트로닉스 주식회사 반도체 소자 제조방법
KR100498475B1 (ko) * 2003-01-07 2005-07-01 삼성전자주식회사 모스 전계 효과 트랜지스터 구조 및 그 제조 방법
JP2004241755A (ja) * 2003-01-15 2004-08-26 Renesas Technology Corp 半導体装置
US6878583B2 (en) * 2003-02-05 2005-04-12 Taiwan Semiconductor Manufacturing Company Integration method to enhance p+ gate activation
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
EP1602125B1 (en) * 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation process
US6830996B2 (en) * 2003-03-24 2004-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Device performance improvement by heavily doped pre-gate and post polysilicon gate clean
US20040188765A1 (en) * 2003-03-28 2004-09-30 International Business Machines Corporation Cmos device integration for low external resistance
FR2854276A1 (fr) * 2003-04-24 2004-10-29 Koninkl Philips Electronics Nv Dispositif semiconducteur comprenant des extensions realisees en un materiau a faible temperature de fusion.
JP4305192B2 (ja) * 2003-04-25 2009-07-29 セイコーエプソン株式会社 薄膜半導体装置の製造方法、電気光学装置の製造方法
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7012024B2 (en) * 2003-08-15 2006-03-14 Micron Technology, Inc. Methods of forming a transistor with an integrated metal silicide gate electrode
KR100546369B1 (ko) * 2003-08-22 2006-01-26 삼성전자주식회사 콘택 마진을 확보할 수 있는 실리사이드막을 구비한고집적 반도체 소자 및 그 제조방법
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
DE10351008B4 (de) * 2003-10-31 2008-07-10 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Transistoren mit erhöhten Drain- und Sourcegebieten mit unterschiedlicher Höhe sowie ein Halbleiterbauelement
US6933157B2 (en) * 2003-11-13 2005-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer manufacturing methods employing cleaning delay period
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
US20050116360A1 (en) * 2003-12-01 2005-06-02 Chien-Chao Huang Complementary field-effect transistors and methods of manufacture
US7247569B2 (en) * 2003-12-02 2007-07-24 International Business Machines Corporation Ultra-thin Si MOSFET device structure and method of manufacture
US7012014B2 (en) * 2003-12-04 2006-03-14 Taiwan Semiconductor Manufacturing Co., Ltd Recessed gate structure with reduced current leakage and overlap capacitance
US20050156229A1 (en) * 2003-12-16 2005-07-21 Yeap Geoffrey C. Integrated circuit device and method therefor
US7244654B2 (en) * 2003-12-31 2007-07-17 Texas Instruments Incorporated Drive current improvement from recessed SiGe incorporation close to gate
US20050145956A1 (en) * 2004-01-05 2005-07-07 Taiwan Semiconductor Manufacturing Co. Devices with high-k gate dielectric
US20050179111A1 (en) * 2004-02-12 2005-08-18 Iwen Chao Semiconductor device with low resistive path barrier
JP3884439B2 (ja) * 2004-03-02 2007-02-21 株式会社東芝 半導体装置
US6881635B1 (en) 2004-03-23 2005-04-19 International Business Machines Corporation Strained silicon NMOS devices with embedded source/drain
US7402207B1 (en) 2004-05-05 2008-07-22 Advanced Micro Devices, Inc. Method and apparatus for controlling the thickness of a selective epitaxial growth layer
US20050274951A1 (en) * 2004-06-14 2005-12-15 Howard Gregory E MOSFET having channel in bulk semiconductor and source/drain on insulator, and method of fabrication
JP4837902B2 (ja) 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7135724B2 (en) * 2004-09-29 2006-11-14 International Business Machines Corporation Structure and method for making strained channel field effect transistor using sacrificial spacer
US7456062B1 (en) 2004-10-20 2008-11-25 Advanced Micro Devices, Inc. Method of forming a semiconductor device
US7241700B1 (en) 2004-10-20 2007-07-10 Advanced Micro Devices, Inc. Methods for post offset spacer clean for improved selective epitaxy silicon growth
US7402485B1 (en) 2004-10-20 2008-07-22 Advanced Micro Devices, Inc. Method of forming a semiconductor device
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7064025B1 (en) * 2004-12-02 2006-06-20 International Business Machines Corporation Method for forming self-aligned dual salicide in CMOS technologies
US7026232B1 (en) * 2004-12-23 2006-04-11 Texas Instruments Incorporated Systems and methods for low leakage strained-channel transistor
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7195985B2 (en) * 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
US7335959B2 (en) * 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
JP4361880B2 (ja) * 2005-01-11 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置の製造方法
CN1808268B (zh) * 2005-01-18 2010-10-06 中芯国际集成电路制造(上海)有限公司 用于应变硅mos晶体管的金属硬掩模方法和结构
US7553718B2 (en) 2005-01-28 2009-06-30 Texas Instruments Incorporated Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps
KR100593452B1 (ko) * 2005-02-01 2006-06-28 삼성전자주식회사 전체실리사이드 금속게이트전극을 갖는 모스 트랜지스터의제조방법
JP2006229040A (ja) * 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd 熱処理方法および熱処理装置
JP4369379B2 (ja) 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7211481B2 (en) * 2005-02-18 2007-05-01 Texas Instruments Incorporated Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer
JP4867176B2 (ja) * 2005-02-25 2012-02-01 ソニー株式会社 半導体装置の製造方法
JP4515305B2 (ja) * 2005-03-29 2010-07-28 富士通セミコンダクター株式会社 ｐチャネルＭＯＳトランジスタおよびその製造方法、半導体集積回路装置の製造方法
WO2006111888A1 (en) * 2005-04-20 2006-10-26 Koninklijke Philips Electronics N.V. A strained integrated circuit and a method of manufacturing the same
DE102005020133B4 (de) * 2005-04-29 2012-03-29 Advanced Micro Devices, Inc. Verfahren zur Herstellung eines Transistorelements mit Technik zur Herstellung einer Kontaktisolationsschicht mit verbesserter Spannungsübertragungseffizienz
US20060252191A1 (en) * 2005-05-03 2006-11-09 Advanced Micro Devices, Inc. Methodology for deposition of doped SEG for raised source/drain regions
JP4630728B2 (ja) * 2005-05-26 2011-02-09 株式会社東芝 半導体装置及びその製造方法
US7553732B1 (en) 2005-06-13 2009-06-30 Advanced Micro Devices, Inc. Integration scheme for constrained SEG growth on poly during raised S/D processing
US20060281271A1 (en) * 2005-06-13 2006-12-14 Advanced Micro Devices, Inc. Method of forming a semiconductor device having an epitaxial layer and device thereof
US7732289B2 (en) * 2005-07-05 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a MOS device with an additional layer
CN101218667B (zh) * 2005-07-07 2010-12-29 富士通半导体股份有限公司 半导体器件及其制造方法
CN100463143C (zh) * 2005-07-07 2009-02-18 中芯国际集成电路制造(上海)有限公司 具有氧化物间隔层的应变源漏cmos的集成方法
KR100632465B1 (ko) * 2005-07-26 2006-10-09 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US7902008B2 (en) * 2005-08-03 2011-03-08 Globalfoundries Inc. Methods for fabricating a stressed MOS device
KR100618908B1 (ko) * 2005-08-12 2006-09-05 삼성전자주식회사 게이트 저항을 개선한 반도체 소자 및 제조 방법
US7470943B2 (en) * 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US7572705B1 (en) 2005-09-21 2009-08-11 Advanced Micro Devices, Inc. Semiconductor device and method of manufacturing a semiconductor device
US7326601B2 (en) * 2005-09-26 2008-02-05 Advanced Micro Devices, Inc. Methods for fabrication of a stressed MOS device
KR100654360B1 (ko) * 2005-10-27 2006-12-08 삼성전자주식회사 반도체 집적 회로 장치와 그 제조 방법
US7947546B2 (en) * 2005-10-31 2011-05-24 Chartered Semiconductor Manufacturing, Ltd. Implant damage control by in-situ C doping during SiGe epitaxy for device applications
US7566609B2 (en) * 2005-11-29 2009-07-28 International Business Machines Corporation Method of manufacturing a semiconductor structure
US7618856B2 (en) * 2005-12-06 2009-11-17 United Microelectronics Corp. Method for fabricating strained-silicon CMOS transistors
US7560780B2 (en) * 2005-12-08 2009-07-14 Intel Corporation Active region spacer for semiconductor devices and method to form the same
KR100741908B1 (ko) * 2005-12-30 2007-07-24 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
DE602006019940D1 (de) * 2006-03-06 2011-03-17 St Microelectronics Crolles 2 Herstellung eines flachen leitenden Kanals aus SiGe
DE102006015087B4 (de) * 2006-03-31 2011-03-10 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Transistoren
DE102006015090B4 (de) * 2006-03-31 2008-03-13 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher eingebetteter Verformungsschichten in Transistoren
US7410875B2 (en) * 2006-04-06 2008-08-12 United Microelectronics Corp. Semiconductor structure and fabrication thereof
US8207523B2 (en) * 2006-04-26 2012-06-26 United Microelectronics Corp. Metal oxide semiconductor field effect transistor with strained source/drain extension layer
US7935590B2 (en) * 2006-05-11 2011-05-03 United Microelectronics Corp. Method of manufacturing metal oxide semiconductor and complementary metal oxide semiconductor
US7541239B2 (en) * 2006-06-30 2009-06-02 Intel Corporation Selective spacer formation on transistors of different classes on the same device
DE102006030264B4 (de) * 2006-06-30 2008-08-28 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Transistoren mit einem Kanal mit biaxialer Verformung, die durch Silizium/Germanium in der Gateelektrode hervorgerufen wird
KR100834741B1 (ko) 2006-07-26 2008-06-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20080076236A1 (en) * 2006-09-21 2008-03-27 Jih-Shun Chiang Method for forming silicon-germanium epitaxial layer
US7494862B2 (en) * 2006-09-29 2009-02-24 Intel Corporation Methods for uniform doping of non-planar transistor structures
US7800182B2 (en) * 2006-11-20 2010-09-21 Infineon Technologies Ag Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
US7897493B2 (en) * 2006-12-08 2011-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Inducement of strain in a semiconductor layer
DE102007004862B4 (de) * 2007-01-31 2014-01-30 Globalfoundries Inc. Verfahren zur Herstellung von Si-Ge enthaltenden Drain/Source-Gebieten in Transistoren mit geringerem Si/Ge-Verlust
US20080272437A1 (en) * 2007-05-01 2008-11-06 Doris Bruce B Threshold Adjustment for High-K Gate Dielectric CMOS
US8574979B2 (en) * 2007-05-18 2013-11-05 Texas Instruments Incorporated Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS process flow
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US7892930B2 (en) * 2007-10-08 2011-02-22 Texas Instruments Incorporated Method to improve transistor tox using SI recessing with no additional masking steps
US20090146181A1 (en) * 2007-12-07 2009-06-11 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing diffused source/drain extensions
KR101082096B1 (ko) * 2008-01-21 2011-11-10 주식회사 하이닉스반도체 샐리사이드 공정을 이용한 반도체 소자의 제조방법
US20090186475A1 (en) * 2008-01-21 2009-07-23 Shyh-Fann Ting Method of manufacturing a MOS transistor
US8293631B2 (en) 2008-03-13 2012-10-23 International Business Machines Corporation Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
KR101448172B1 (ko) * 2008-07-02 2014-10-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
DE102009006800B4 (de) * 2009-01-30 2013-01-31 Advanced Micro Devices, Inc. Verfahren zur Herstellung von Transistoren und entsprechendes Halbleiterbauelement
DE102009006884B4 (de) * 2009-01-30 2011-06-30 Advanced Micro Devices, Inc., Calif. Verfahren zur Herstellung eines Transistorbauelementes mit In-Situ erzeugten Drain- und Source-Gebieten mit einer verformungsinduzierenden Legierung und einem graduell variierenden Dotierstoffprofil und entsprechendes Transistorbauelement
US8274110B2 (en) * 2009-05-20 2012-09-25 Micron Technology, Inc. Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
JP5446558B2 (ja) * 2009-08-04 2014-03-19 富士通セミコンダクター株式会社 半導体装置の製造方法
US8487354B2 (en) * 2009-08-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving selectivity of epi process
JP5434365B2 (ja) * 2009-08-24 2014-03-05 ソニー株式会社 半導体装置及びその製造方法
US8067282B2 (en) * 2009-10-08 2011-11-29 United Microelectronics Corp. Method for selective formation of trench
US8421164B2 (en) 2010-01-05 2013-04-16 Micron Technology, Inc. Memory cell array with semiconductor selection device for multiple memory cells
CN101807605B (zh) * 2010-02-05 2015-05-06 上海华虹宏力半导体制造有限公司 一种半导体器件及其制造方法
JP5236676B2 (ja) * 2010-03-18 2013-07-17 ルネサスエレクトロニクス株式会社 スタティック・ランダム・アクセス・メモリ
US8278166B2 (en) * 2010-07-16 2012-10-02 United Microelectronics Corp. Method of manufacturing complementary metal oxide semiconductor device
US8426265B2 (en) * 2010-11-03 2013-04-23 International Business Machines Corporation Method for growing strain-inducing materials in CMOS circuits in a gate first flow
US8778767B2 (en) 2010-11-18 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and fabrication methods thereof
KR101195269B1 (ko) * 2011-02-15 2012-11-14 에스케이하이닉스 주식회사 낮은 컨택저항을 갖는 반도체소자의 제조방법
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
JP5360119B2 (ja) * 2011-04-18 2013-12-04 富士通セミコンダクター株式会社 半導体装置とその製造方法
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8969154B2 (en) 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8574995B2 (en) * 2011-11-10 2013-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain doping method in 3D devices
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
CN103325684B (zh) * 2012-03-23 2016-03-02 中国科学院微电子研究所 一种半导体结构及其制造方法
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
WO2013180244A1 (ja) * 2012-05-31 2013-12-05 富士電機株式会社 半導体装置の製造方法
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
CN103515239A (zh) * 2012-06-28 2014-01-15 中芯国际集成电路制造(上海)有限公司 超薄soi半导体器件制造方法及超薄soi半导体器件
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
JP5488675B2 (ja) * 2012-11-14 2014-05-14 ソニー株式会社 半導体装置の製造方法
US8900958B2 (en) 2012-12-19 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US8853039B2 (en) 2013-01-17 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction for formation of epitaxial layer in source and drain regions
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9142673B2 (en) * 2013-07-31 2015-09-22 Globalfoundries Inc. Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
US10157995B2 (en) * 2013-08-09 2018-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating junction formation of transistors with contact formation
WO2015099782A1 (en) 2013-12-27 2015-07-02 Intel Corporation Diffused tip extension transistor
KR102157839B1 (ko) * 2014-01-21 2020-09-18 삼성전자주식회사 핀-전계효과 트랜지스터의 소오스/드레인 영역들을 선택적으로 성장시키는 방법
US9214551B2 (en) 2014-02-19 2015-12-15 United Microelectronics Corp. Method for fabricating semiconductor device, and semiconductor device made thereby
JP2015228418A (ja) * 2014-05-30 2015-12-17 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびその製造方法
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US10084063B2 (en) * 2014-06-23 2018-09-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9716160B2 (en) * 2014-08-01 2017-07-25 International Business Machines Corporation Extended contact area using undercut silicide extensions
DE102014111140B4 (de) * 2014-08-05 2019-08-14 Infineon Technologies Austria Ag Halbleitervorrichtung mit Feldeffektstrukturen mit verschiedenen Gatematerialien und Verfahren zur Herstellung davon
US9502418B2 (en) 2014-10-02 2016-11-22 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
US20160155818A1 (en) * 2014-11-27 2016-06-02 United Microelectronics Corp. Method for fabricating semiconductor device
US9761693B2 (en) 2014-11-27 2017-09-12 United Microelectronics Corp. Method for fabricating semiconductor device
US11049939B2 (en) * 2015-08-03 2021-06-29 Semiwise Limited Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation
TWI680502B (zh) 2016-02-03 2019-12-21 聯華電子股份有限公司 半導體元件及其製作方法
CN106206316A (zh) * 2016-07-27 2016-12-07 上海集成电路研发中心有限公司 一种金属氧化物半导体场效应晶体管的制造方法
US10879354B2 (en) * 2016-11-28 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
CN113629144B (zh) * 2020-05-08 2023-07-07 长鑫存储技术有限公司 半导体器件及其制备方法
US11373696B1 (en) 2021-02-19 2022-06-28 Nif/T, Llc FFT-dram

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4133704A (en) * 1977-01-17 1979-01-09 General Motors Corporation Method of forming diodes by amorphous implantations and concurrent annealing, monocrystalline reconversion and oxide passivation in <100> N-type silicon
JPS6151959A (ja) * 1984-08-22 1986-03-14 Toshiba Corp 半導体装置の製造方法
CA1216962A (en) * 1985-06-28 1987-01-20 Hussein M. Naguib Mos device processing
JPS6313379A (ja) * 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
US4885617A (en) * 1986-11-18 1989-12-05 Siemens Aktiengesellschaft Metal-oxide semiconductor (MOS) field effect transistor having extremely shallow source/drain zones and silicide terminal zones, and a process for producing the transistor circuit
US5006476A (en) * 1988-09-07 1991-04-09 North American Philips Corp., Signetics Division Transistor manufacturing process using three-step base doping
US4876213A (en) * 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
IT1235693B (it) * 1989-05-02 1992-09-21 Sgs Thomson Microelectronics Transistore ad effetto di campo superficiale con regione di source e/o di drain scavate per dispositivi ulsi.
US5012306A (en) * 1989-09-22 1991-04-30 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron MISFET device
JP2921889B2 (ja) * 1989-11-27 1999-07-19 株式会社東芝 半導体装置の製造方法
US5231042A (en) * 1990-04-02 1993-07-27 National Semiconductor Corporation Formation of silicide contacts using a sidewall oxide process
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
JPH04350942A (ja) * 1991-05-29 1992-12-04 Nec Corp 半導体装置の製造方法
JP2727818B2 (ja) * 1991-09-17 1998-03-18 日本電気株式会社 半導体装置
US5341014A (en) * 1992-01-07 1994-08-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device and a method of fabricating the same
US5242847A (en) * 1992-07-27 1993-09-07 North Carolina State University At Raleigh Selective deposition of doped silion-germanium alloy on semiconductor substrate
US5393685A (en) * 1992-08-10 1995-02-28 Taiwan Semiconductor Manufacturing Company Peeling free metal silicide films using rapid thermal anneal
US5352631A (en) * 1992-12-16 1994-10-04 Motorola, Inc. Method for forming a transistor having silicided regions
JPH0786579A (ja) * 1993-09-14 1995-03-31 Toshiba Corp 半導体装置
US5409847A (en) * 1993-10-27 1995-04-25 Matsushita Electric Industrial Co., Ltd. Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature
US5478776A (en) * 1993-12-27 1995-12-26 At&T Corp. Process for fabricating integrated circuit containing shallow junction using dopant source containing organic polymer or ammonium silicate
US5405795A (en) * 1994-06-29 1995-04-11 International Business Machines Corporation Method of forming a SOI transistor having a self-aligned body contact
KR0135147B1 (ko) * 1994-07-21 1998-04-22 문정환 트랜지스터 제조방법
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5538909A (en) * 1995-01-19 1996-07-23 United Microelectronics Corporation Method of making a shallow trench large-angle-tilt implanted drain device
US5569624A (en) * 1995-06-05 1996-10-29 Regents Of The University Of California Method for shallow junction formation
WO1997047159A1 (fr) * 1996-06-03 1997-12-11 Kanagawa Prefectural Government Procede de fabrication d'un dispositif emettant des infrarouges et dispositif emettant des infrarouges ainsi obtenu
TW346652B (en) * 1996-11-09 1998-12-01 Winbond Electronics Corp Semiconductor production process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368792B2 (en) 2003-05-14 2008-05-06 Samsung Electronics Co., Ltd. MOS transistor with elevated source/drain structure
CN100456439C (zh) * 2003-05-14 2009-01-28 三星电子株式会社 具有抬高的源极/漏极结构的mos晶体管及其制造方法
CN100449780C (zh) * 2003-06-27 2009-01-07 英特尔公司 具有凸起的结区域的pmos晶体管
CN102468164A (zh) * 2010-10-29 2012-05-23 中国科学院微电子研究所 晶体管及其制造方法
CN102468164B (zh) * 2010-10-29 2014-10-08 中国科学院微电子研究所 晶体管及其制造方法

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US6326664B1 (en) 2001-12-04
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