CN1366711A - 具有硅－锗(Sii－x－Gex)门极MOS晶体管的集成CMOS电路的半导体装置及其生产方法 - Google Patents

具有硅－锗(Sii－x－Gex)门极MOS晶体管的集成CMOS电路的半导体装置及其生产方法 Download PDF

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CN1366711A
CN1366711A CN01800927A CN01800927A CN1366711A CN 1366711 A CN1366711 A CN 1366711A CN 01800927 A CN01800927 A CN 01800927A CN 01800927 A CN01800927 A CN 01800927A CN 1366711 A CN1366711 A CN 1366711A
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Y·波诺马雷夫
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Koninklijke Philips NV
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Abstract

包含一个具有NMOS和PMOS晶体管(A,B)的CMOS集成电路的半导体装置,其中NMOS和PMOS晶体管具有形成于硅基底层(1)的半导体区(23,24,29,30)。在门区(29,30)所在的区域向基底层表面加上一层氧化物层(11),并在该氧化物层上形成门电极(16,17)。PMOS晶体管(B)的门电极(17)在p－型掺杂的多晶硅层(14)上形成,p－型掺杂的多晶硅－锗(Si1－xGex;0<x<1)层(13)嵌在硅－锗层和门电极之间。NMOS晶体管(A)的门电极(16)在n－型掺杂的不含锗的多晶硅层(14)上形成。CMOS集成电路融合了具有p－型掺杂的多晶硅－锗层的门电极的PMOS晶体管的优点和具有n－型掺杂硅的门电极的NMOS晶体管的优点。

Description

具有硅-锗(Sii-xGex)门极MOS晶体管的 集成CMOS电路的半导体装置及其生产方法
本发明涉及带有集成CMOS电路的半导体装置，该CMOS电路包含具有半导体区域的NMOS和PMOS晶体管，半导体区是在硅基底层上形成的并与其表面相邻，该表面上有一层门极氧化物，其上的门极是在形成晶体管的半导体区的区域上形成，使得PMOS晶体管的门极就在位于多晶硅层和门极氧化物之间的p-型掺杂的多晶硅层和p-型掺杂的多晶硅-锗层中形成。
硅-锗(Sii-xGex；0＜x＜1)层可以从一种含有硅烷(SiH4)，氢化锗(GeH4)以及氮气的混合气体中用常规的方法通过一个化学气相沉积(CVD)装置沉积而成。这里，分子式中的X由混合气体中硅烷和氢化锗的量比决定。这些硅-锗层可以沉积在氧化物上，其中分子式中的X在0-1范围之间。
起始段中提到的半导体装置可从EP-A-614226中了解到，EP-A-614226中的PMOS晶体管以及NMOS晶体管都是在一个多晶硅层和一个处于多晶硅层与氧化物之间的硅-锗多晶(Sii-xGex)层中形成。门极还包括一个位于多晶硅层的上面的金属硅化物顶层。PMOS晶体管的门极呈P-型掺杂，而NMOS晶体管呈n-型掺杂。
用在集成CMOS电路中的NMOS和PMOS晶体管在实际当中设计成具有相同的绝对门槛电压值；如，“0.18微米生产线”晶体管，具有一个0.3V的目标电压。在PMOS晶体管中当一个p-型掺杂的多晶硅门极被一个p-型掺杂质的多晶硅锗门极代替时，会升高晶体管的门槛电压。通过减少晶体管门极区域的掺杂质的含量，可以使晶体管获得一个所希望的较低的门槛电压。在“0.18微米生产线”中PMOS晶体管的门槛电压是0.3V，如，附加的30at％的锗可以把表面掺杂物从5.1017减少到3.1017。门极区较低的杂质浓度是相当有益的。晶体管将具有较高的导通电流Ion和较低的关断电流Ioff以及一个较高的Ion/Ioff比率。并且还发现基底层电压对门槛电压V1的影响较小。由于硅-锗层中锗的比例较大，所以这些优点就显得非常重要，这样门极区的掺杂物含量就变得较低。但这在NMOS晶体管中是不成立的。当然，具有n-型掺杂质的硅-锗门极的NMOS晶体管的特性比具有n-型杂质但不含锗的硅门极的NMOS晶体管的特性要差，特别是，当硅-锗层中锗的含量超过30at％时。当门极中加入超过30at％的锗后，会改善PMOS晶体管的特性，然而这种附加对于上述半导体装置的互补的PMOS和NMOS晶体管中的门极来说不会起到很大的作用。
本发明的目标是针对上述问题提供一种解决方法，这种方法可以使得使用具有与在集成CMOS电路中的氧化物电极相靠近的多晶硅-锗层的门极变得有用。起始段提到的半导体装置就是用于这个目的，它的特点是NMOS晶体管的门极在一层无锗的多晶硅n-型掺杂层中形成。
使用形成于多晶硅层和嵌入在多晶硅层与PMOS晶体管中的氧化物层之间的多晶硅-锗(Sii-xGex)掺杂层的p-型掺杂门极，具有上文所述的优点。而在NMOS晶体管中n-型硅-锗门极的使用却只有坏处。加入到硅-锗门极的n-型掺杂物，如砷和磷，很难被激活，但在随后的生产过程中由于加热却很容易再次失去活性。这些杂质的无活性原子会引起所不希望的较大门区损耗。
本发明提供的方法使形成一个具有NMOS和PMOS晶体管的集成电路成为可能，这个集成电路的特性比那些具有NMOS和PMOS互补晶体管且全部由硅-锗门极组成的集成电路的特性更好，而且也比具有NMOS和PMOS互补晶体管且由不含锗的硅电极组成的集成电路的特性要好。该措施利用了在PMOS晶体管中使用硅-锗门极的优点，而避免这种门极在NMOS晶体管中使用的缺点。
当p-型层掺杂的多晶硅-锗(Sii-xGex)中，锗的含量超过30at％时(x＞0.3)，上述提到的优点就显得非常重要。如果这个p-型掺杂层沉淀在一个厚度小于5nm的非晶体硅层上面，那么该p-型掺杂层将具有较低的表面粗糙度，而不会影响上文中提及的晶体管的操作。
半导体装置的一个优选实施方案除了包括上述的PMOS晶体管外还包括另外的PMOS晶体管，该晶体管具有形成于处于门极氧化层上的p-型掺杂的无锗多晶硅层中的门极，后面的PMOS晶体管在所有其他方面跟前面的都相同。这些具有门区的PMOS晶体管与拥有硅-锗门极的PMOS晶体管具有相同掺杂物，并且具有一个较低的门槛电压。以例子的形式给出一个上述的门区杂质含量，如表面杂质浓度为3.1017原子每立方厘米(cc)时，门槛电压仅仅为-0.1V而不是-0.3V。这些在下文中将变得非常明显并能以简单的方式加入到集成电路中的晶体管，比具有更高门槛电压的晶体管更适合于，如，类似于信号放大等方面的应用。
本发明还涉及一种生产具有集成CMOS电路的半导体装置的方法，该CMOS电路包含具有半导体区域的NMOS和PMOS晶体管，半导体区是在硅基底层上形成的并与其表面相邻，该表面上有一层门极氧化物，为PMOS晶体管形成硅锗门极，为NMOS晶体管形成无锗的硅门极。门极以本方法按以下顺序生成，氧化层上沉积一层硅-锗多晶体，多晶硅-锗层上生成一层抗光掩模，该抗光掩模覆盖了硅-锗多晶体层上的PMOS晶体管区，但它不覆盖硅-锗多晶体层上的NMOS晶体管区，经蚀刻处理，从而从氧化层上除掉NMOS晶体管区的硅锗层，抗光掩模也被去除，一层多晶硅便沉积在上述方法生成的结构上，一个门极便在上述的处于多晶硅-锗层的PMOS晶体管所在区域中形成，多晶硅的覆盖层和门极在位于多晶硅层的NMOS晶体管所在区域中形成。形成晶体管源极和漏极的半导体区用常规的离子注入法生成，此前形成的门极当作掩模使用。PMOS晶体管的门极是自动的强p-型掺杂的，而NMOS晶体管的门极是自动的强n-型掺杂的。
在生成形成PMOS晶体管的活性区时，抗光掩模覆盖NMOS晶体管的表面区域，而露出PMOS晶体管区域。在生成形成NMOS晶体管的活性区时，用抗光掩模覆盖PMOS晶体管的表面区域，而露出NMOS晶体管区域，根据本发明第二个抗光掩模可同时用于覆盖PMOS晶体管区域的硅-锗层，但不覆盖NMOS晶体管所在区域的硅-锗层，用于从氧化层中除去NMOS晶体管区域的硅-锗层。这两个相同的抗光掩模可由同一种照相平版印刷膜形成。
最好，锗含量超过30at％(x＞0.3)的硅-锗(Sii-xGex)多晶层沉积在氧化物层之上。如果在多晶硅-锗层沉积之前在氧化物层上先形成一层厚度不超过5纳米的非晶体硅层，那么此后就可沉积一个表面平滑的硅-锗层。
除了具有硅-锗门极的PMOS晶体管和具有硅门极的NMOS晶体管外，具有无锗的硅门极的PMOS晶体管也可以通过简单的无需附加的抗光掩模方法来形成。门极可以在多晶硅层上形成，在该多晶硅上的PMOS晶体管区域还形成了NMOS晶体管的门极。门极用抗光掩模形成，同样NMOS晶体管的门极也由它形成。源极和漏极由抗光掩模形成，抗光掩模还用于形成别的PMOS晶体管的源极和漏极。为实现这种可选设计，需要生产所说的抗光掩模必须的照相平版印刷膜用于不同的设计。
下文中将通过参考例图来详细解释本发明，其中：
图1到13典型地图示了根据本发明生产具有NMOS晶体管和PMOS晶体管的集成电路过程的一系列生产阶段，以及
图14到15典型地图示了根据本发明的具有集成CMOS电路的半导体装置的优选实施方案的一些生产阶段。
图1到13典型地图示了根据本发明生产具有NMOS晶体管和PMOS晶体管的集成电路过程的一系列生产阶段。为能清楚说明，这些图图示的生产的电路紧紧具有一个NMOS和一个PMOS晶体管。很明显，一个集成电路可以包含许多这样的晶体管。
从硅晶片1开始，其厚度约为3微米，在它外层生长一个层2，在本例中层2经轻微掺杂，其杂质浓度约为3.1015原子每立方厘米。在常规方式下，活性区A和B在顶层2中形成，顶层2与表面3相靠近，并且同另一个氧化层4隔离。氧化物区域4通过对本区域的硅的氧化而形成，但是也可以通过别的方式，如，通过对表面3的沟槽的腐蚀后填满绝缘物质来形成。NMOS晶体管在活性区A中形成，PMOS晶体管在活性区B中形成。
氧化层形成以后，便用第一个抗光掩模5覆盖NMOS晶体管所在的活性区A，但它不覆盖PMOS晶体管所在的活性区B，从而往活性区B注入了磷离子，如虚线6所示。然后除去抗光掩模5，并且向PMOS所在的活性区B覆盖一层抗光掩模7，抗光掩模7不覆盖NMOS晶体管所在的激活区A，因而可以向活性区A注入硼离子，如虚线8所示。然后再去除抗光掩模7，之后进行加热处理，这样就可以在活性区A形成与表面3相毗邻的p-型掺杂区9，p-型掺杂区也称作p-阱，同时在活性区B形成与表面3相毗邻的n-型掺杂区10，n-型掺杂区也称作n-阱。掺杂区9和10的厚度大约为600纳米，两者都经轻微掺杂，其浓度大约为2.1017原子每立方厘米，表面3的掺杂浓度显得较高，大约为3.1017。在活性区A和B中也可以用常规的硅加热氧化方法在表面3的上面形成一层大约5纳米厚的氧化物层11。
当p-阱9，n-阱10，和氧化物层11形成后便沉积了一层大约2纳米厚的非晶体硅12，和一个大约20纳米厚的硅-锗(Sii-xGex)多晶层13。硅-锗层13是用一种含有硅烷(SiH4)，氢化锗(GeH4)以及氮气的混合气体中用常规的方法通过一个化学气相沉积(CVD)装置沉积而成。硅-锗层中锗的成分比例与混合气体中硅烷和四氢化锗的比率相一致。硅-锗(Sii-xGex)多晶层13中，锗的含量可以达到100％。所选例子中，沉积的多晶硅-锗(Sii-xGex)中锗的含量是30at％。在非晶体硅层12上面沉积的硅-锗层13具有以下优点，即这样生成的硅锗层的表面要比直接在氧化物层12沉积生成的硅-锗层的表面光洁，然而非晶体硅层12在本发明中不是必须的。
接下来，将再一次用抗光掩模7来覆盖PMOS晶体管所在的活性区B，而暴露NMOS晶体管所在的晶体管区A。用含有硝酸和氢氟酸(体积比30vol％HNO3，20vol％H2O，和体积比10vol％稀释HF[0.08％HF])的蚀刻池从活性区的非晶体硅层中腐蚀掉硅-锗层10。此前，第二个抗光掩模7用于形成p-阱9。并再次使用相同的照相平版印刷膜形成抗光掩模7。
抗光掩模7被去除之后，便在上面沉积一层大约120纳米厚的多晶硅14。在多晶硅层14上面涂上一层抗光掩模15以限定晶体管的门极。之后用等离子蚀刻法腐蚀出NMOS晶体管的门极16和PMOS晶体管的门极17。PMOS晶体管门极17在多晶硅层14和相邻层硅-锗层13以及非晶体硅层12中形成，而NMOS晶体管的门极16则只是在的多晶硅层14和非晶体硅层12中形成。本例子中，门极16和17的宽度是0.18微米。
随后就形成了晶体管的源极和漏极。首先用抗光掩模覆盖区域B而暴露区域A，然后往区域A注入砷离子，如图9的虚线18所示。在除去这层抗光掩模之后，又用另一层抗光掩模覆盖区域A而暴露区域B，然后再往区域B注入硼离子，如图9的虚线19所示。在除去抗光掩模之后用常规的方法向门极16和17提供一个氧化硅衬层20，也就是说，大约沉积一个150纳米厚的氧化硅层并对它们进行一个各向异性的蚀刻处理，使门极16和17从氧化硅层20的上层边界处露出。然后又用抗光掩模(没有示出)覆盖区域B而暴露区域A，此后再次注入砷离子，如虚线21所示。在除去这层抗光掩模后，又用另一层抗光掩模(没有示出)覆盖区域A而暴露区域B，并再次注入硼离子，如虚线22所示。当除去最后这层抗光掩模后，便对其进行加热处理，从而形成晶体管的源极和漏极区23，24。PMOS晶体管的源极和漏极区23是p-型掺杂的，其掺杂比率在区域25部分是每立方厘米大约1021个原子而掺杂比率在26部分是每立方厘米大约1020个原子，它低于门极17的浓度。NMOS晶体管源极和漏极区24是n-型掺杂的，其掺杂比率在27部分是每立方厘米大约1021个原子，而掺杂比率在28部分则是每立方厘米大约1020个原子，它低于门极16的杂质浓度。位于源极和漏极区23之间的n-阱10的29部分形成了PMOS晶体管的门区，而位于源极和漏极区24之间的p-阱9的30部分形成了NMOS晶体管的门区。源极和漏极区23及24通过注入离子并加热而形成，与此同时对PMOS晶体管的门极进行了p-型掺杂处理，而对NMOS晶体管的门极进行了n-型掺杂处理。最后，腐蚀掉与门极16及17相邻的氧化物层，并且用常规的自对准方法向门极16和17的源极和漏极区23及24铺上个一个二矽化钛(TiSi2)顶层。
这样就生成了一个具有NMOS和PMOS晶体管的半导体装置，这两个晶体管又有四个形成于硅基底层1并且同表面3相靠近的半导体区23，24，29，30，而表面3由氧化物层11在形成晶体管门区29和30的半导体区域中形成，并在这些区域中形成门极16和17，这样，PMOS晶体管的门极17便形成于p-型掺杂多晶硅层14和嵌于多晶硅层14和氧化物层11之间的p-型掺杂多晶硅-锗(Sii-xGex)层13中，同时，NMOS晶体管的门极16形成于n-型掺杂的多晶硅层14中，而区域的氧化物层11上面不含元素锗。
本例中的具有硅-锗门极17的PMOS晶体管，含有30％的锗，门区表面的杂质浓度是每立方厘米3.1017个原子，以及一个-0.3V的门槛电压，与另一种门极不含锗元素、门区表面杂质浓度是每立方厘米5.1017个原子、其他各项均相同的PMOS晶体管相比，前者的开通电流(Ion)比后者高10％左右，而关断电流(Ioff)比后者低10％左右。这些可取的特性源于晶体管门区的较低的杂质浓度。若在硅-锗层中能掺入更多的锗成分，则性能会变得更好。如果锗的含量，譬如，是60at％(x＝0.6)，则，为了实现同样的-0.3V的门槛电压，门区的表面掺杂浓度可以减低到大约1.1017原子/立方厘米，从而与不含锗元素的上述具有硅门极的晶体管相比其导通电流(Ion)提高25％、关断电流减低15％左右。因此采用一层锗含量超过30at％(x＞0.3)的p-型掺杂的多晶硅-锗层，是可取的。
然而在NMOS晶体管中使用一层硅-锗门极，却不能获得上述优点。硅-锗层中门极的n-型杂质不能被有效激活；那些没被激活的原子会引起大量的有害的门区损耗。当硅-锗门极只用于PMOS晶体管而不用在NMOS晶体管时，就可以利用前者的优点而避免后者的缺点。
图14和15典型地图示了一些具有集成CMOS电路的优选实施方案的生产步骤。除了在区域B形成具有硅-锗门极17的PMOS晶体管，以及在区域A形成了具有硅门极16的NMOS晶体管外，还生成了具有不含锗的硅门极的PMOS晶体管，而它却无需附加使用抗光掩模。为达到这个目的，除了形成活性区A和B外还形成了一个活性区C。如图14所示，区域C与区域B一样也具有一个n-阱。从区域C的非晶体硅层12中除去硅-锗层13，区域A中，多晶硅层14是直接沉积在非晶体硅层12之上的。如图15所示，在区域C的氧化物层11中形成门极16，情况如同区域A，同时区域C也形成源极和漏极区23，情况如同区域B。从而，形成于区域B和区域C的PMOS晶体管之间的差异仅仅在于门极16和17两者各自的形状而已，它们其它方面的特性完全相同。区域C中PMOS晶体管的门极16是通过使用抗光掩模来形成，这种方法同样用于形成区域A中的NMOS晶体管的门极16。区域C中PMOS晶体管的源极和漏极是通过使用抗光掩模来形成，这种方法同样用于形成区域B中的NMOS晶体管的源极和漏极。为实现这种可选设计，需要把生产所说的抗光掩模必须的照相平版印刷膜用于不同的设计。
在区域C形成的具有硅门极16的PMOS晶体管有一个门区29，并且它具有与在区域B中形成的具有硅-锗门极17的PMOS晶体管相同的掺杂质，并具有一个相应的较低的门槛电压。此处作为例子，在门区掺杂一个3.1017原子/平方厘米的表面杂质浓度，则门槛电压不会超过-0.1V，而不是-0.3V。这样的晶体管比具有相对较高门槛电压的晶体管更适合于如，类似信号放大方面的应用。

Claims (8)

1.一个具有集成CMOS电路的半导体装置，该CMOS电路包含具有半导体区域的NMOS和PMOS晶体管，半导体区是在硅基底层上形成的并与其表面相邻，该表面上有一层门极氧化物，其上的门极是在形成晶体管的半导体区的区域上形成，使得PMOS晶体管的门极就在位于多晶硅层和门极氧化物之间的p-型掺杂的多晶硅层和p-型掺杂的多晶硅-锗(Sii-xGex；0＜x＜1)层中形成，其特征在于NMOS晶体管的门极在一层不含锗的n-型掺杂的多晶硅中形成。
2.权利要求1的半导体装置，其特征在于p-型掺杂的多晶硅-锗(Sii-xGex)层中锗的含量超过30at％(x＞0.3)。
3.权利要求1或2的半导体装置，其特征在于在氧化物层和多晶硅-锗层之间形成了一个厚度小于5纳米的非晶体硅层。
4.权利要求2或3的半导体装置，其特征在于半导体装置不但包括上述的PMOS晶体管，还包括另外的具有在p-型掺杂的不含锗多晶硅层中形成的门极的PMOS晶体管，后面的PMOS晶体管与前面的在其他方面的特性完全相同
5.一种生产具有集成CMOS电路的半导体装置的方法，该CMOS电路包含具有半导体区域的NMOS和PMOS晶体管，半导体区是在硅基底层上形成的并与其表面相邻，该表面上有一层门极氧化物，其上为PMOS晶体管生成硅-锗门极以及为NMOS晶体管生成不含锗的硅门极，其特征在于
门极按照以本方法按以下顺序形成，
-在氧化物层的上面沉积一层硅-锗(Sii-xGex；0＜x＜1)多晶体
-在硅-锗多晶体层的上面形成一层抗光掩模，该抗光掩模覆盖了上述硅-锗多晶体层的PMOS晶体管所在区域而不覆盖NMOS晶体管所在区域，
-此后对其进行蚀刻处理，以除去氧化物层中NMOS晶体管区域内的硅-锗层
-去除抗光掩模，
-在上述形成的结构上沉积一层多晶硅，以及
-在硅-锗多晶体层和覆盖在其上的多晶硅层中的PMOS晶体管区域形成一个门极，同时，在多晶硅层上的上述NMOS晶体管区域中形成一个门极。
6.权利要求5的方法，其特征在于沉积在氧化物层上的硅-锗(Sii-xGex)多晶体层中，锗的含量超过了30％(x＞0.3)。
7.权利要求5或6的方法，其特征在于在氧化物层上面沉积一层硅锗之前先形成一层厚度小于5纳米的非晶体硅。
8.权利要求5，6或7的方法，其特征在于为了在PMOS晶体管的生成区域中生成具有不含锗的硅门极的PMOS晶体管，须在多晶硅层中形成门极，以及形成NMOS晶体管的门极。
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Cited By (8)

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Publication number Priority date Publication date Assignee Title
CN1312758C (zh) * 2002-09-11 2007-04-25 台湾积体电路制造股份有限公司 具有应变平衡结构的cmos元件及其制造方法
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100402381B1 (ko) * 2001-02-09 2003-10-17 삼성전자주식회사 게르마늄 함유 폴리실리콘 게이트를 가지는 씨모스형반도체 장치 및 그 형성방법
KR100487525B1 (ko) * 2002-04-25 2005-05-03 삼성전자주식회사 실리콘게르마늄 게이트를 이용한 반도체 소자 및 그 제조방법
KR20030090411A (ko) * 2002-05-23 2003-11-28 삼성전자주식회사 선택적 성장을 이용한 씨모스 게이트 및 그 제조방법
US7615390B2 (en) * 2002-10-03 2009-11-10 Nxp B.V. Method and apparatus for forming expitaxial layers
US6709912B1 (en) * 2002-10-08 2004-03-23 Chartered Semiconductor Manufacturing Ltd. Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization
US6838695B2 (en) 2002-11-25 2005-01-04 International Business Machines Corporation CMOS device structure with improved PFET gate electrode
KR100706244B1 (ko) 2005-04-07 2007-04-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP2006332687A (ja) * 2006-07-10 2006-12-07 Fujitsu Ltd Ｃｍｏｓ半導体装置
KR100924549B1 (ko) 2007-11-14 2009-11-02 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
US8053301B2 (en) * 2009-03-30 2011-11-08 International Business Machines Corporation CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess
KR20120107762A (ko) * 2011-03-22 2012-10-04 삼성전자주식회사 반도체 소자의 제조 방법
KR101993321B1 (ko) 2013-11-11 2019-06-26 에스케이하이닉스 주식회사 트랜지스터, 트랜지스터의 제조 방법 및 트랜지스터를 포함하는 전자장치
KR102133490B1 (ko) 2013-11-11 2020-07-13 에스케이하이닉스 주식회사 트랜지스터, 트랜지스터의 제조 방법 및 트랜지스터를 포함하는 전자장치
WO2017036897A1 (en) * 2015-08-28 2017-03-09 Akzo Nobel Chemicals International B.V. Formulation for the treatment of acne

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801396A (en) * 1989-01-18 1998-09-01 Stmicroelectronics, Inc. Inverted field-effect device with polycrystalline silicon/germanium channel
EP0614226A1 (en) * 1992-10-05 1994-09-07 Texas Instruments Incorporated Gate electrode using stacked layers of TiN and polysilicon
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
WO1998013880A1 (en) * 1996-09-25 1998-04-02 Advanced Micro Devices, Inc. POLY-Si/POLY-SiGe GATE FOR CMOS DEVICES
US5952701A (en) * 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US6261887B1 (en) * 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1312758C (zh) * 2002-09-11 2007-04-25 台湾积体电路制造股份有限公司 具有应变平衡结构的cmos元件及其制造方法
CN101359626B (zh) * 2008-09-12 2010-06-02 西安电子科技大学 用微米级工艺制备纳米级cmos集成电路的方法
CN101359628B (zh) * 2008-09-12 2010-06-02 西安电子科技大学 基于SiN/SiO2掩蔽技术的纳米级CMOS集成电路制备方法
CN101359629B (zh) * 2008-09-12 2010-06-09 西安电子科技大学 基于SiO2掩蔽技术的多晶SiGe栅纳米级CMOS集成电路制备方法
CN101359631B (zh) * 2008-09-12 2010-06-09 西安电子科技大学 用微米级工艺制备多晶SiGe栅纳米级CMOS集成电路方法
CN101359630B (zh) * 2008-09-12 2010-06-16 西安电子科技大学 一种SiO2掩蔽技术制备纳米级CMOS集成电路的方法
CN102203924A (zh) * 2008-10-30 2011-09-28 飞思卡尔半导体公司 具有设计的Ge分布和优化硅帽盖层的优化压缩SiGe沟道PMOS晶体管
CN103125014A (zh) * 2010-09-28 2013-05-29 国际商业机器公司 具有栅极堆叠的半导体器件
CN103125014B (zh) * 2010-09-28 2015-09-23 国际商业机器公司 具有栅极堆叠的半导体器件

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