JP5446558B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5446558B2 JP5446558B2 JP2009181166A JP2009181166A JP5446558B2 JP 5446558 B2 JP5446558 B2 JP 5446558B2 JP 2009181166 A JP2009181166 A JP 2009181166A JP 2009181166 A JP2009181166 A JP 2009181166A JP 5446558 B2 JP5446558 B2 JP 5446558B2
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- 239000004065 semiconductor Substances 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 239000010703 silicon Substances 0.000 claims description 41
- 229910021332 silicide Inorganic materials 0.000 claims description 34
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 229910008310 Si—Ge Inorganic materials 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 229920006254 polymer film Polymers 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010574 gas phase reaction Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 99
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001878 scanning electron micrograph Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013039 cover film Substances 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Description
半導体基板の活性領域上に、ゲート絶縁膜とシリコン膜とを形成する工程と、
前記シリコン膜上方にゲート電極用レジストパターンを形成する工程と、
前記レジストパターンをマスクとして、前記シリコン膜を厚さの途中までエッチングし、前記レジストパターン下方に凸部を残す工程と、
前記レジストパターンを除去した後、前記シリコン膜を覆うダミー膜を形成する工程と、
前記ダミー膜を異方性エッチングして、前記凸部の側壁上に前記ダミー膜を残存させ、平坦面上の前記ダミー膜を除去する工程と、
前記ダミー膜をマスクとして、前記シリコン膜の残りの厚さをエッチングしてゲート電極を形成する工程と、
前記ゲート電極両側の半導体基板に、ソース/ドレイン領域を形成する工程と、
前記ソース/ドレイン領域と前記ゲート電極にシリサイド領域を形成する工程と
を有し、
前記ゲート絶縁膜と前記シリコン膜とを形成する工程の後であって、前記ゲート電極用レジストパターンを形成する工程の前に、前記シリコン膜上にマスク膜を堆積する工程をさらに有し、
前記凸部を残す工程が、前記マスク膜と前記シリコン膜の積層の凸部を形成する工程であり、
前記ダミー膜は、前記シリコン膜と前記マスク膜の形成する凸部を覆うものであり、
前記シリコン膜の残りの厚さをエッチングしてゲート電極を形成する工程が、前記マスク膜と前記ダミー膜をマスクとして前記シリコン膜の残りの厚さをエッチングする工程であり、
前記シリコン膜の残りの厚さをエッチングする工程の後、前記ソース/ドレイン領域を形成する工程の前に、前記マスク膜を除去する工程
をさらに有する半導体装置の製造方法
が提供される。
12 素子分離領域、
13 ゲート絶縁膜、
14 ポリシリコン膜、
15 ハードマスク膜、
16 BARC膜、
17 フォトレジスト膜、
18 凸部、
19 ダミー膜(ポリマ膜)、
21 エクステンション領域、
22 サイドウォールスペーサ、
23 低抵抗ソース/ドレイン領域、
24,25 シリサイド領域、
26 コンタクトエッチストッパ膜、
27 絶縁膜、
28 導電性プラグ、
29 配線、
31 エクステンション領域、
33 低抵抗ソース/ドレイン領域、
34、35 凹部、
36,37 Si−Ge領域、
38,39 シリサイド領域、
STI 素子分離領域、
GI ゲート絶縁膜、
PG ポリシリコンゲート電極、
G ゲート電極、
Ext エクステンション領域、
S/D 低抵抗ソース/ドレイン領域、
SW サイドウォールスペーサ、
M メタル膜、
PL 導電性プラグ、
GS ゲート電極のシリサイド領域、
S/D・S ソース/ドレイン領域のシリサイド領域。
Claims (7)
- 半導体基板の活性領域上に、ゲート絶縁膜とシリコン膜とを形成する工程と、
前記シリコン膜上方にゲート電極用レジストパターンを形成する工程と、
前記レジストパターンをマスクとして、前記シリコン膜を厚さの途中までエッチングし、前記レジストパターン下方に凸部を残す工程と、
前記レジストパターンを除去した後、前記シリコン膜を覆うダミー膜を形成する工程と、
前記ダミー膜を異方性エッチングして、前記凸部の側壁上に前記ダミー膜を残存させ、平坦面上の前記ダミー膜を除去する工程と、
前記ダミー膜をマスクとして、前記シリコン膜の残りの厚さをエッチングしてゲート電極を形成する工程と、
前記ゲート電極両側の半導体基板に、ソース/ドレイン領域を形成する工程と、
前記ソース/ドレイン領域と前記ゲート電極にシリサイド領域を形成する工程と
を有し、
前記ゲート絶縁膜と前記シリコン膜とを形成する工程の後であって、前記ゲート電極用レジストパターンを形成する工程の前に、前記シリコン膜上にマスク膜を堆積する工程をさらに有し、
前記凸部を残す工程が、前記マスク膜と前記シリコン膜の積層の凸部を形成する工程であり、
前記ダミー膜は、前記シリコン膜と前記マスク膜の形成する凸部を覆うものであり、
前記シリコン膜の残りの厚さをエッチングしてゲート電極を形成する工程が、前記マスク膜と前記ダミー膜をマスクとして前記シリコン膜の残りの厚さをエッチングする工程であり、
前記シリコン膜の残りの厚さをエッチングする工程の後、前記ソース/ドレイン領域を形成する工程の前に、前記マスク膜を除去する工程
をさらに有する半導体装置の製造方法。 - 半導体基板の活性領域上に、ゲート絶縁膜とシリコン膜とを形成する工程と、
前記シリコン膜上方にゲート電極用レジストパターンを形成する工程と、
前記レジストパターンをマスクとして、前記シリコン膜を厚さの途中までエッチングし、前記レジストパターン下方に凸部を残す工程と、
前記レジストパターンを除去した後、前記シリコン膜を覆うダミー膜を形成する工程と、
前記ダミー膜を異方性エッチングして、前記凸部の側壁上に前記ダミー膜を残存させ、平坦面上の前記ダミー膜を除去する工程と、
前記ダミー膜をマスクとして、前記シリコン膜の残りの厚さをエッチングしてゲート電極を形成する工程と、
前記ゲート電極両側の半導体基板に、ソース/ドレイン領域を形成する工程と、
前記ソース/ドレイン領域と前記ゲート電極にシリサイド領域を形成する工程と
を有し、
前記ダミー膜が、CH2F2,CF4,CH4のいずれかを用いた気相反応で堆積したポリマ膜であり、シリコンのエッチングでエッチされ、アッシングで除去されるものである、
半導体装置の製造方法。 - 前記マスク膜、前記ダミー膜が無機絶縁膜であり、前記マスク膜を除去する工程で同時に除去される請求項1記載の半導体装置の製造方法。
- 前記ソース/ドレイン領域を形成する工程の後、前記ゲート電極を覆って前記半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜を貫通して、前記ソース/ドレイン領域に達するコンタクト孔を形成する工程と、
前記コンタクト孔内に導電性プラグを埋め込む工程と、
を有する請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。 - 前記ソース/ドレイン領域を形成する工程が、
前記ゲート電極をマスクとして前記半導体基板にエクステンション領域をイオン注入し、
前記ゲート電極側壁上に絶縁物のサイドウォールスペーサを形成し、
前記ゲート電極、前記サイドウォールスペーサをマスクとして前記半導体基板に低抵抗ソース/ドレイン領域を形成する
請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。 - 前記ソース/ドレイン領域がp型であり、
前記p型ソース/ドレイン領域内のシリコンをエッチングして凹部を形成し、
前記凹部にSi−Geをエピタキシャル成長させ、前記半導体基板表面より隆起するSi−Ge領域を形成する、
請求項1乃至5のいずれか1項に記載の半導体装置の製造方法。 - 前記p型ソース/ドレイン領域内のシリコンを前記エッチングする際、前記ゲート電極も同時にエッチングされ、
前記凹部に前記Si−Geを前記エピタキシャル成長させる際、前記エッチングされたゲート電極上に多結晶のSi−Geが成長する、
請求項6記載の半導体装置の製造方法。
Priority Applications (2)
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JP2009181166A JP5446558B2 (ja) | 2009-08-04 | 2009-08-04 | 半導体装置の製造方法 |
US12/849,795 US7989300B2 (en) | 2009-08-04 | 2010-08-03 | Method of manufacturing semiconductor device |
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JP2009181166A JP5446558B2 (ja) | 2009-08-04 | 2009-08-04 | 半導体装置の製造方法 |
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JP2011035217A JP2011035217A (ja) | 2011-02-17 |
JP5446558B2 true JP5446558B2 (ja) | 2014-03-19 |
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US20130270614A1 (en) * | 2012-04-17 | 2013-10-17 | Toshiba America Electronic Components, Inc. | Formation of a trench silicide |
US9614053B2 (en) * | 2013-12-05 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacers with rectangular profile and methods of forming the same |
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JPH0232539A (ja) * | 1988-07-22 | 1990-02-02 | Hitachi Ltd | 半導体装置の製造方法及びエッチング方法 |
JPH039529A (ja) * | 1989-06-07 | 1991-01-17 | Matsushita Electron Corp | Mosトランジスタの製造方法 |
JP3063276B2 (ja) * | 1991-09-13 | 2000-07-12 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP3325717B2 (ja) * | 1994-09-09 | 2002-09-17 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US6022782A (en) * | 1997-05-30 | 2000-02-08 | Stmicroelectronics, Inc. | Method for forming integrated circuit transistors using sacrificial spacer |
JPH11238879A (ja) * | 1998-02-20 | 1999-08-31 | Sharp Corp | 半導体装置の製造方法及び半導体装置 |
JP4270719B2 (ja) * | 1999-06-30 | 2009-06-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2002329861A (ja) * | 2001-05-01 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
JP2004095639A (ja) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6818519B2 (en) * | 2002-09-23 | 2004-11-16 | Infineon Technologies Ag | Method of forming organic spacers and using organic spacers to form semiconductor device features |
DE10351006B4 (de) * | 2003-10-31 | 2010-01-21 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Transistors mit erhöhten Drain- und Source-Gebieten, wobei eine reduzierte Anzahl von Prozessschritten erforderlich ist |
KR100579850B1 (ko) * | 2003-12-31 | 2006-05-12 | 동부일렉트로닉스 주식회사 | 모스 전계효과 트랜지스터의 제조 방법 |
JP4237660B2 (ja) * | 2004-03-19 | 2009-03-11 | 株式会社東芝 | 半導体装置の製造方法 |
JP4837902B2 (ja) * | 2004-06-24 | 2011-12-14 | 富士通セミコンダクター株式会社 | 半導体装置 |
US7723235B2 (en) * | 2004-09-17 | 2010-05-25 | Renesas Technology Corp. | Method for smoothing a resist pattern prior to etching a layer using the resist pattern |
KR100685893B1 (ko) * | 2005-06-22 | 2007-02-26 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자 및 그 제조방법 |
JP2007059812A (ja) * | 2005-08-26 | 2007-03-08 | Toshiba Corp | 半導体装置およびその製造方法 |
US7381610B2 (en) * | 2005-11-04 | 2008-06-03 | International Business Machines Corporation | Semiconductor transistors with contact holes close to gates |
JP2007200972A (ja) * | 2006-01-24 | 2007-08-09 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2008078403A (ja) | 2006-09-21 | 2008-04-03 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP5040286B2 (ja) * | 2006-12-13 | 2012-10-03 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
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US8791001B2 (en) * | 2008-09-08 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | N2 based plasma treatment and ash for HK metal gate protection |
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US7989300B2 (en) | 2011-08-02 |
US20110033997A1 (en) | 2011-02-10 |
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