TWI807104B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI807104B
TWI807104B TW108134504A TW108134504A TWI807104B TW I807104 B TWI807104 B TW I807104B TW 108134504 A TW108134504 A TW 108134504A TW 108134504 A TW108134504 A TW 108134504A TW I807104 B TWI807104 B TW I807104B
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gate
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source
recess
dummy gate
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TW108134504A
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TW202013527A (zh
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李昆穆
李彥儒
宋學昌
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台灣積體電路製造股份有限公司
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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Abstract

提供半導體裝置及其製造方法，可在第一虛設閘極與第二虛設閘極之間設置半導體層內的第一凹陷。在第一虛設閘極的側壁上形成第一間隙物，以及在第二虛設閘極的側壁上形成第二間隙物。第一和第二間隙物形成接觸第一凹陷的底面的三角形間隙物延伸部。在形成第一和第二間隙物之後，在半導體層內形成設置在第一虛設閘極與第二虛設閘極之間的第二凹陷。在第二凹陷內磊晶成長源/汲極區。

Description

半導體裝置及其製造方法
本發明實施例是關於半導體裝置的製造方法，特別是有關於具有三角形間隙物延伸部的半導體裝置及其形成方法。
半導體裝置被用於各式各樣的電子應用中，例如個人電腦、手機、數位相機和其他電子設備。典型上，半導體裝置的製造是藉著在半導體基底上依序沉積絕緣或介電層、導電層和半導體層之材料，且使用微影(lithography)將各種材料層圖案化以在半導體基底上形成電路組件及元件。
在半導體產業藉由持續地降低最小部件尺寸來改善各種電子組件(例如電晶體、二極體、電阻器、電容器等)的整合密度，使得更多的組件可整合至給定的面積中。然而，降低最小部件尺寸的同時也產生額外需處理的問題。
由於鰭式場效電晶體(FinFET)的小尺寸和高效能，其在積體電路製造的應用越來越多。完全應變的通道進一步改善了鰭式場效電晶體的效能，但仍需處理因完全應變的通道架構所產生的缺陷。
在一實施例中，半導體裝置的製造方法包含在半導體層上形成第一虛設閘極和第二虛設閘極。使用第一虛設閘極和第二虛設閘極作為第一遮罩蝕刻半導體層。蝕刻半導體層在半導體層內形成設置在第一虛設閘極與第二虛設閘極之間的第一凹陷。在第一虛設閘極的側壁上形成第一間隙物，且在第二虛設閘極的側壁上形成第二間隙物。第一間隙物和第二間隙物形成接觸第一凹陷的底面的三角形間隙物延伸部。在形成第一間隙物和第二間隙物之後，在半導體層內形成設置在第一虛設閘極與第二虛設閘極之間的第二凹陷。在第二凹陷內磊晶成長源/汲極區。
根據另一個實施例，半導體裝置的製造方法包含在基底上磊晶成長半導體層。在半導體層上形成第一閘極。使用第一閘極作為遮罩蝕刻半導體層。蝕刻半導體層在半導體層內形成與第一閘極相鄰的第一和第二凹陷。在第一閘極的側壁上形成間隙物。間隙物形成接觸第一凹陷的底面的三角形間隙物延伸部。使用間隙物作為遮罩在半導體層內形成第二凹陷。在第二凹陷內形成源/汲極區。在源/汲極區上形成接觸。
根據又一個實施例，裝置包含具有鰭的基底。自鰭延伸出第一閘極。在鰭內設置與第一閘極相鄰的源/汲極區。在源/汲極區上設置接觸。沿著第一閘極的側壁設置間隙物。間隙物形成延伸至低於第一閘極下的鰭的最頂面的三角形間隙物延伸部。
50:基底
56:隔離區
58:鰭
82:源/汲極區
92:閘極介電層
94:閘極電極
100:基底
111:輕摻雜源/汲極區
114:磊晶層
115:第一凹陷
116:半導體鰭
117:三角形間隙物延伸部
118:襯層
120:介電材料
122:絕緣材料
124:淺溝槽隔離區
130:虛設閘極層
131:虛設閘極
132:遮罩層
133:遮罩
134:第一閘極子間隙物
135:第二閘極子間隙物
136:第三閘極子間隙物
137:閘極間隙物
138:第二凹陷
139:磊晶的源/汲極區
140:第一層間介電質
142:凹陷
144:閘極介電層
146:閘極電極
147:金屬功函數層
148:填充材料
150:第二層間介電質
152:閘極接觸
154:源/汲極接觸
156:矽化物接觸
D1、D2:第一深度
H1:高度
S1:底面
S2:頂面
W1、W2:寬度
α:角度
藉由以下的詳述配合所附圖式，我們能更加理解本發明實施例的內容。需注意的是，根據產業上的標準做法，許多部 件(feature)並未按照比例繪製。事實上，為了能清楚地討論，這些部件的尺寸可能被任意地增加或減少。
第1圖是根據一些實施例，顯示鰭式場效電晶體的範例的三維(three-dimensional)示意圖。
第2-7、8A-8B、9A-9B、10-13、14A-19A、14B-19B圖是根據一些實施例，顯示形成鰭式場效電晶體的各個中間步驟的剖面示意圖。
以下揭露提供了很多不同的實施例或範例，用於實施本發明的不同部件。組件和配置的具體範例描述如下，以簡化本揭露的說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，以下敘述中提及第一部件形成於第二部件之上或上方，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本揭露可在各個範例中重複參考數字及/或字母，如此重複是為了簡化和清楚的目的，並非為了指定在此所討論的各個實施例及/或組態之間的關係。
再者，空間上的相關用語，例如「在......下方」、「下方」、「較低的」、「上方」、「較高的」及相似的用語可用於此以使本揭露更容易地敘述圖式中一個元件或部件與另一個(或另一些)元件或部件之間的關係。這些空間上的相關用語意欲涵蓋除了圖式所描繪的方向之外，使用或操作中的裝置的不同方向。設備可以其他方向定位(旋轉90度或其他方向)，且在此使用的空間相關描 述可同樣依此解讀。
儘管不是限定本揭露，鰭式場效電晶體的製造可涵蓋許多實施例。在這樣的實施例中，以下敘述的製程可在相應的鰭上實施。藉由本揭露的內容，本發明所屬技術領域中具有通常知識者將可以理解在此提供之教示的各種替代和延伸，且這些都在本揭露涵蓋的範圍內。舉例來說，雖然顯示的實施例為鰭式場效電晶體，本發明所屬技術領域中具有通常知識者將能識別出上述教示在像是平面(planar)電晶體、微機電系統(MEMS)裝置、三維積體電路(3DIC)裝置等的適用性。
本發明的一些實施例也可包含其他部件和製程。舉例而言，可包含測試結構以幫助對於三維(3D)封裝或三維積體電路(3DIC)裝置的驗證測試。舉例而言，測試結構可包含形成在重佈線層內或形成在基底上的測試墊(test pad)，以便能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等等。可對中間結構和最終結構進行驗證測試。另外，在此揭露的結構和方法可與測試方法結合使用，以提高良率並降低成本。
在此揭露的一或多個實施例的優勢部件包含因具有三角形輪廓的間隙物延伸部做為向外擴散的金屬阻擋層所產生的低源/汲極電容，進而產生更快的裝置效能、更佳的良率和產品可靠度。為了改善可靠度，手機晶片有低耗電的需求，這取決於降低源/汲極區的寄生電容。不像傳統結構中接觸金屬與源/汲極磊晶之間界面的低熱穩定度(thermal stability)可能導致低良率和較差的可靠度，在此揭露的實施例係提供以改善良率和可靠度。在此敘述及/或顯示的至少一些實施例的進一步優勢部件包含因間隙物下方的通 道輪廓而產生之較低的電容、改善的良率和穩定度。製程在不需要改變其他循環製程的情況下可相容於標準的整合製造流程。至少一些在此敘述的實施例可延伸至使用需要改變形狀之磊晶技術的其他實施例，例如微機電系統(MEMS)裝置、三維積體電路(3DIC)裝置等。
第1圖是根據一些實施例，顯示鰭式場效電晶體(FinFET)的範例的三維示意圖做為參考。鰭式場效電晶體包括在基底50(例如半導體基底)上的鰭58。在基底50內設置隔離區56，鰭58自鄰近的隔離區56突出，且突出於鄰近的隔離區56上。雖然敘述及圖式顯示隔離區56與基底50隔開，在此使用的用語「基底」可用來單指半導體基底，或包含隔離區56的半導體基底。閘極介電層92在鰭58的頂面上且沿著鰭58的側壁，且閘極電極94在閘極介電層92上。在鰭58的相對兩側內相對於閘極介電層92和閘極電極94設置源/汲極區82。第1圖進一步顯示用於接續的圖式中的參考剖面示意圖。剖面A-A是沿著閘極電極94的縱軸，且以與鰭式場效電晶體的源/汲極區82之間的電流方向垂直的方向為例。剖面B-B與剖面A-A垂直，且沿著鰭58的縱軸，例如鰭式場效電晶體的源/汲極區82之間的電流方向。剖面C-C平行於剖面A-A，且延伸穿過鰭式場效電晶體的源/汲極區82的其中一者。後續的圖式參照這些參考剖面以清楚描述。
在此討論的一些實施例是以使用閘極後製(gate-last)製程形成的鰭式場效電晶體的內容進行討論。在其他實施例中，可使用閘極先製(gate-first)製程。再者，一些實施例涵蓋用於平面(planar)裝置的方案，例如平面式場效電晶體。
第2至19B圖是根據一些實施例，製造鰭式場效電晶體的中間步驟的剖面示意圖。除了顯示多個鰭/鰭式場效電晶體以外，第2至7圖顯示第1圖中顯示的參考剖面A-A。在第8A至9B圖和第14A至19B圖中，以「A」結尾的圖式編號係顯示沿著第1圖顯示的參考剖面A-A(除了顯示多個鰭/鰭式場效電晶體以外)，而以「B」結尾的圖式編號係顯示沿著第1圖顯示的相似剖面B-B。第10至13圖係顯示沿著第1圖顯示的剖面B-B。
在第2圖中，提供基底100。基底100可為半導體基底，例如塊材半導體，絕緣體上覆半導體(semiconductor-on-insulator，SOI)基底等，基底可經摻雜(例如經P型摻質或N型摻質的摻雜)或未經摻雜(undoped)。基底100可為晶圓，例如矽晶圓。一般而言，絕緣體上覆半導體(SOI)基底為形成於絕緣層上的半導體材料層。絕緣層可例如為埋置氧化物(buried oxide，BOX)層、氧化矽層等。在基底(典型上為矽或玻璃基底)上提供絕緣層。也可使用其他基底，例如多層或梯度(gradient)基底。
基底100可具有形成在其中的N型井區或P型井區(未明確繪示)。可藉由在基底100上實施離子植入製程以在基底100內形成N型井區或P型井區。可將N型摻質(例如砷離子)植入基底100以形成N型井區。可將P型摻質(例如硼離子)植入基底100以形成P型井區。
在第3圖中，在基底100上形成磊晶層114。可例如藉由磊晶成長或其他相似的製程以形成磊晶層114。磊晶層114可包括像是矽鍺(SiGe)的材料或相似的材料，且可經摻雜(例如經P型摻質或N型摻質的摻雜)或未經摻雜。在一實施例中，磊晶層114包括SiGe，且鍺百分比在約10%與約50%之間。SiGe包括與Si相比較低的能隙 (bandgap)，允許對後續形成的P型金屬氧化物半導體(p-type metal oxide semiconductor，PMOS)裝置提供較大的電洞移動率。可在磊晶層114上實施平坦化製程。可藉由任何合適的平坦化製程將磊晶層114平坦化，例如化學機械研磨(chemical mechanical polish，CMP)、回蝕(etch-back)製程、前述的組合等。一些實施例中，在平坦化製程之後，磊晶層可具有在約100Å與約5000Å之間的厚度。
在第4圖中，蝕刻磊晶層114和基底100以形成半導體鰭116(又稱為第一半導體鰭)。一些實施例中，可藉由在磊晶層114和基底100內蝕刻溝槽以形成第一半導體鰭116。前述的蝕刻可為一或多道任何可接受的蝕刻製程，例如反應式離子蝕刻(reactive ion etch，RIE)、中性粒子束蝕刻(neutral beam etch，NBE)等、或前述的組合。前述的蝕刻可為異向性(anisotropic)。雖然顯示的半導體鰭116具有圓弧的角落和線性的邊緣，然而半導體鰭116可具有任何其他合適的形狀，例如具有漸細(tapered)的側壁。一些實施例中，半導體鰭116可具有在約10Å與約5000Å之間的高度。
可藉由任何合適的方法將半導體鰭116圖案化。舉例而言，可使用一或多道微影製程將半導體鰭116圖案化，微影製程包含雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合微影和自對準(self-aligned)製程，允許形成間距小於使用單一、直接地微影製程所獲得的間距的圖案。雖然並未另外顯示雙重圖案化或多重圖案化製程，在一實施例中，雙重圖案化或多重圖案化製程可包含在基底上形成犧牲層。使用微影製程將犧牲層圖案化。使用自對準製程沿著犧牲層的側邊形成間隙物。然後移除犧牲層，且用剩餘的間隙物將第一半導體鰭116圖案化。
在半導體鰭116內包含由例如矽鍺形成的磊晶層114，可增加隨後形成的PMOS電晶體的電洞移動率(mobility)。另外，由於鍺相較於矽具有較小的能隙，在半導體鰭116內包含磊晶層114可在隨後形成的PMOS電晶體內產生較高的電流。在預定形成N型金屬氧化物半導體(N-type metal-oxide semiconductor，NMOS)電晶體的實施例中，磊晶層114可以由可提高載子移動率的材料形成，例如碳化矽。碳化矽可經N型摻質摻雜，例如磷。
在第5圖中，在基底100和半導體鰭116上形成絕緣材料122，填入半導體鰭之間的開口中。一些實施例中，如第5圖所示，絕緣材料122包含襯層118和在襯層118上的介電材料120。襯層118可形成為共形(conformal)層，共形層的水平部分和垂直部分具有彼此相近的厚度。
一些實施例中，藉由在含氧的環境中將基底100和半導體鰭116暴露的表面氧化以形成襯層118。例如藉由局部矽氧化(local oxidation of silicon，LOCOS)，其中可在各自的製程氣體中包含氧氣(O2)。在其他的實施例中，可例如使用氫氣(H2)和氧氣(O2)的組合氣體、或水蒸氣的原位蒸氣產生(in-situ steam generation，ISSG)以氧化基底100和半導體鰭116暴露的表面。在其他的實施例中，使用沉積技術以形成襯層118，像是原子層沉積(atomic layer deposition，ALD)、化學氣相沉積(chemical vapor deposition，CVD)、次大氣壓化學氣相沉積(sub-atmospheric chemical vapor deposition，SACVD)等或前述的組合。一些實施例中，襯層118具有在約0.2Å與約100Å之間的厚度。
形成介電材料120填入半導體鰭116之間的開口的剩 餘部分。介電材料120可能溢出(overfill)半導體鰭116之間的開口，使得一部分的介電材料120延伸至半導體鰭116的頂面上。一些實施例中，介電材料120可包括氧化矽、碳化矽、氮化矽等或前述的組合，且可使用流動式化學氣相沉積(flowable chemical vapor deposition，FCVD)、旋轉塗佈(spin-on coating)、化學氣相沉積(CVD)、原子層沉積(ALD)、高密度電漿化學氣相沉積(high density plasma chemical vapor deposition，HDPCVD)、低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)等或前述的組合以形成。在沉積介電材料120之後，可實施退火/固化(curing)步驟，將流動式的介電材料120轉變為固態的介電材料。一些實施例中，由於不同的材料特性(像是不同類型的材料及/或不同密度)，襯層118和介電材料120之間的界面是可分辨的。
在第6圖中，對絕緣材料122施以平坦化製程。一些實施例中，平坦化製程包含化學機械研磨(CMP)、回蝕(etch-back)製程、前述的組合等。如第6圖所顯示，平坦化製程可露出半導體鰭116的頂面。也可藉由平坦化製程將部分的半導體鰭116平坦化。在完成平坦化製程之後，半導體鰭116和絕緣材料122的頂面為齊平的(在製程變異度內)。
在第7圖中，將絕緣材料122凹陷以形成淺溝槽隔離(shallow trench isolation，STI)區124。將絕緣材料122凹陷使得半導體鰭116自相鄰的淺溝槽隔離區124突出。使用可接受的蝕刻製程將淺溝槽隔離區124凹陷，例如對淺溝槽隔離區124的材料具有選擇性的。舉例而言，使用無電漿(plasma-less)氣體蝕刻製程(例如使用氫氟酸(HF)氣體、氨氣(NH3)等的蝕刻製程)、遠程電漿輔助乾式蝕刻製 程(例如使用氫氣(H2)、三氟化氮(NF3)和氨的副產物等的製程)，或稀釋氫氟酸(dHF)的化學氧化物移除方式。
在第8A和8B圖中，在半導體鰭116和淺溝槽隔離區124上形成虛設閘極層130，且在虛設閘極層130上形成遮罩層132。在形成虛設閘極層130之前，可在半導體鰭116和淺溝槽隔離區124上形成虛設介電層(未明確繪示)。虛設介電層可例如為氧化矽、氮化矽、前述的組合等，且根據可接受的技術進行沉積或熱成長。可在半導體鰭116上沉積虛設閘極層130，然後將虛設閘極層130平坦化，例如藉由化學機械研磨(CMP)。可在虛設閘極層130上沉積遮罩層132。虛設閘極層130可例如為非晶矽、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物和金屬。可藉由物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積(CVD)、濺鍍(sputtering)沉積、或其他已知且在本發明所屬技術領域用以沉積導電材料的技術以沉積虛設閘極層130。虛設閘極層130可由相對於隔離區的蝕刻具有高蝕刻選擇性的材料製成。遮罩層132可例如包含SiN、SiON等。
在第9A和9B圖中，使用可接受的微影和蝕刻技術將遮罩層132(見第8A和8B圖)圖案化以形成遮罩133。藉由可接受的蝕刻技術，將遮罩133的圖案轉移至虛設閘極層130以形成虛設閘極131。虛設閘極131覆蓋半導體鰭116各自的通道區。遮罩133的圖案可用以將每一個虛設閘極131與相鄰的虛設閘極131物理性地隔開。虛設閘極131也可具有縱向方向，大抵上垂直於半導體鰭116的縱向方向。
在第10圖中，使用虛設閘極131做為遮罩蝕刻磊晶層114，以在虛設閘極131的任一側形成第一凹陷115。在磊晶層114包 括矽鍺的實施例中，前述的蝕刻可包括使用Cl2、HBr、HF、SF6、CHF3、CH2F2、CF4、SO2、NH3、NF3、He、SiCl4、O2、Ar、H2及/或其他氣體蝕刻劑的乾式蝕刻製程。可在約室溫與約500℃之間的溫度下，約10-3毫托(mTorr)與約760毫托(mTorr)之間的壓力下進行前述的蝕刻，且進行的時間區段在約0.1秒與約500秒之間。如第10圖所示，由於是沿著磊晶層114的矽鍺的結晶面進行蝕刻，產生的第一凹陷115中磊晶層114的表面將具有淺的凹面。在一實施例中，第一凹陷115可具有第一深度D1，自第一凹陷115的最低點測量至與磊晶層114的頂面齊平處的第一深度D1在約1nm與10nm之間。如第10圖所示，第一凹陷115可具有寬度，在虛設閘極131的相鄰側壁之間測量的寬度在約20nm與約200nm之間，且在與磊晶層114的頂面齊平的表面與第一凹陷115的側壁之間的角度α在約5度與約60度之間。
在第11圖中，沿著虛設閘極131和遮罩133的側壁形成閘極間隙物137。在一實施例中，如第11圖所示，閘極間隙物137的形成可藉由在虛設閘極131和遮罩133的頂面和側壁上共形地沉積材料，以及隨後異向性地蝕刻前述的材料，以移除位於遮罩133的頂面上的部分，以及位於自虛設閘極131的側壁起算的寬度W1更遠的部分。閘極間隙物137的材料可為氮化矽、SiCN、SiOC、SiOCN、前述的組合等。
在各種不同的實施例中，閘極間隙物137可包括複數個閘極子間隙物(subspacer)。在第11-19B圖顯示的一實施例中，閘極間隙物137包括三個閘極子間隙物：第一閘極子間隙物134、第二閘極子間隙物135和第三閘極子間隙物136。第一閘極子間隙物134為在後續製程期間移除虛設閘極131的蝕刻停止層。第一閘極子間隙物134可 具有在約0.5nm與約5nm之間的厚度。在一實施例中，第二閘極子間隙物135降低裝置結構的電容。第二閘極子間隙物135可具有在約0.5nm與約5nm之間的厚度。在一實施例中，第三閘極子間隙物136可為虛設或犧牲間隙物層，做為後續的生產製程中的犧牲蝕刻停止層。第三閘極子間隙物136可具有在約1nm與約10nm之間的厚度。第一閘極子間隙物134和第二閘極子間隙物135可包括相同材料或可包括不同材料。在一實施例中，第三閘極子間隙物136包括至少不同於第二閘極子間隙物135的材料，以做為犧牲蝕刻停止層。
在形成第一閘極子間隙物134之後，可實施輕摻雜源/汲極(lightly doped source/drain，LDD)區111的植入。在一些例如PMOS裝置的實施例中，可在暴露的半導體鰭116內植入合適類型(例如P型)的雜質。P型雜質可為硼、BF2等。在其他例如NMOS裝置的實施例中，可在暴露的半導體鰭116內植入合適類型(例如N型)的雜質。N型雜質可為磷、砷等。輕摻雜源/汲極區111可具有約1015cm-3至約1016cm-3的雜質濃度。可使用退火以活化植入的雜質。第11圖顯示輕摻雜源/汲極區111不具限定性的範例。輕摻雜源/汲極區111也可能具有其他組態、形狀和形成方法，且完全涵蓋於本揭露的範圍內。另外，閘極間隙物可具有不同的組態，例如包含各種數量的子間隙物、各種形狀(像是L形間隙物)及/或其他相似的組態。在後續的圖式中，輕摻雜源/汲極區111並非僅為了顯示目的而繪示。
在一實施例中，閘極間隙物137將延伸至第一凹陷115的底面，形成如第11圖所示的三角形間隙物延伸部117。三角形間隙物延伸部117會阻擋金屬自金屬接觸擴散至源/汲極區，藉此降低裝置的寄生電容。在一實施例中，三角形間隙物延伸部117可包括延伸進 入第一凹陷115的三角形的輪廓。在一實施例中，如第11圖所示，三角形間隙物延伸部117包括在約1nm與約10nm之間的高度H1，以及在約1nm與約10nm之間的寬度W1。在各種不同的實施例中，高度H1與寬度W1的比值可在約0.1至10之間。這些尺寸和比值與裝置的效能和寄生電容之間具有強烈的關聯，當高度H1與寬度W1的比值大時，可能導致裝置的效能衰退，而當高度H1與寬度W1的比值小時，可能導致過高的源/汲極區寄生電容。
在第12圖中，使用閘極間隙物137做為遮罩，在磊晶層114內形成第二凹陷138。形成與第一凹陷115的深度D1相比具有較大深度D2的第二凹陷138。第二凹陷138的深度D2可在約35nm與70nm之間。一些實施例中，第二凹陷138可延伸穿過磊晶層114進入基底100。第二凹陷138可由使用Cl2、HBr、HF、SF6、CHF3、CH2F2、CF4、SO2、NH3、NF3、He、SiCl4、O2、Ar、H2及/或其他氣體蝕刻劑的異向性蝕刻以形成。可在約室溫與約500℃之間的溫度下，約10-3mTorr與約760mTorr之間的壓力下進行前述的蝕刻，且進行的時間區段在約0.1秒與約500秒之間。如第12圖所示，第二凹陷138的蝕刻可能對三角形間隙物延伸部產生寬度W2的底切(undercut)，而寬度W2在0nm與5nm之間。
在第13圖中，可在第二凹陷138內磊晶成長形成磊晶的源/汲極區139。一些實施例中，磊晶的源/汲極區139可延伸穿過磊晶層114進入基底100。一些實施例中，使用第二閘極子間隙物135將磊晶的源/汲極區139與虛設閘極131隔開適度的橫向距離，使得磊晶的源/汲極區139不會使後續形成的鰭式場效電晶體的閘極之間產生短路。
一些實施例中，磊晶的源/汲極區139可包含任何適合P型鰭式場效電晶體的可接受材料。舉例而言，磊晶的源/汲極區139可包含SiGe、SiGeB、Ge、GeSn等。可由與磊晶層114的晶格常數相比具有較大晶格常數的材料來形成磊晶的源/汲極區139，在通道區內產生壓縮應力以增加PMOS裝置的電洞移動率。在示範的實施例中，磊晶的源/汲極區139包括SiGeB，且鍺百分比與磊晶層114包括的SiGe的鍺百分比相比高約20%。磊晶的源/汲極區139可具有自半導體鰭116各自的表面抬升的表面，且可具有晶面(facet)。
在其他實施例中，磊晶的源/汲極區139可包含任何適合N型鰭式場效電晶體的可接受材料。舉例而言，磊晶的源/汲極區139可包含Si、SiC、SiCP、SiP等。可由與磊晶層114的晶格常數相比具有較小晶格常數的材料來形成磊晶的源/汲極區139，在通道區內產生拉伸應力以增加NMOS裝置的電子移動率。磊晶的源/汲極區139也可具有自半導體鰭116各自的表面抬升的表面，且可具有晶面。
相似於先前討論形成輕摻雜源/汲極區，隨後進行退火的製程，可對磊晶的源/汲極區139及/或半導體鰭116植入摻質以形成源/汲極區。源/汲極區可具有在約1019cm-3到約1021cm-3之間的雜質濃度。源/汲極區的P型雜質可為任何先前討論的雜質。一些實施例中，磊晶的源/汲極區139可在成長期間原位(in-situ)摻雜。
根據一些實施例，在第14A和14B圖中，沉積第一層間介電質(first interlayer dielectric，ILD)140。第一層間介電質140可由介電材料形成，且可藉由任何合適的方法沉積，例如化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)或流動式化學氣相沉積(FCVD)。介電材料可包含磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、摻硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、未摻雜的矽酸鹽玻璃(undoped silicate glass，USG)等。也可使用任何可接受的製程所形成的其他絕緣物。一些實施例中，在第一層間介電質140與磊晶的源/汲極區139、遮罩133和閘極間隙物137之間設置接觸蝕刻停止層(contact etch stop layer，CESL)(未明確繪示)。
在第15A和15B圖中，可實施平坦化製程(例如化學機械研磨(CMP))以使第一層間介電質140的頂面與虛設閘極131的頂面齊平。平坦化製程也可移除虛設閘極131上的遮罩133，以及閘極間隙物137沿著遮罩133側壁的部分。在平坦化製程之後，虛設閘極131、閘極間隙物137和第一層間介電質140的頂面齊平。因此，虛設閘極131的頂面由第一層間介電質140露出。
在第16A和16B圖中，在(多個)蝕刻步驟中移除虛設閘極131，使形成凹陷142。一些實施例中，藉由異向性乾式蝕刻製程移除虛設閘極131。舉例而言，蝕刻製程可包含乾式蝕刻製程，使用在不蝕刻第一層間介電質140或閘極間隙物136的情況下選擇性地蝕刻虛設閘極131的(多個)蝕刻氣體。每一個凹陷142露出各自的半導體鰭116的通道區。每一個通道區係設置在相鄰配對的磊晶的源/汲極區139之間。
在第17A和17B圖中，形成取代閘極(replacement gate)的閘極介電層144和閘極電極146。在凹陷142內共形地沉積閘極介電層144，例如在半導體鰭116的頂面和側壁上，以及在閘極間隙物137的側壁上。閘極介電層144也可形成在第一層間介電質140的頂面上。根據一些實施例，閘極介電層144包括氧化矽、氮化矽或前述的 多層。一些實施例中，閘極介電層144為高介電常數的介電材料，且在這些實施例中，閘極介電層144可具有大於7.0的介電常數值(k value)，且可包含金屬氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb的矽化物，和前述的組合。閘極介電層144的形成方法可包含分子束沉積(molecular beam deposition，MBD)、原子層沉積(ALD)、電漿增強化學氣相沉積(PECVD)等。
在閘極介電層144上形成閘極電極146，且閘極電極146填入凹陷142的剩餘部分。閘極電極146可為含金屬的材料，例如TiN、TaN、TaC、Co、Ru、Al、前述的組合或前述的多層。閘極電極146可包含一或多層的導電材料，例如金屬功函數層147和填充材料148。在填充閘極電極146之後，可實施平坦化製程(例如化學機械研磨(CMP))以移除閘極介電層144和閘極電極146的過量部分，過量部分指在第一層間介電質140的頂面上的部分。閘極介電層144和閘極電極146的剩餘部分因此形成鰭式場效電晶體的取代閘極。閘極電極146和閘極介電層144可一起稱為「閘極結構」或「閘極堆疊」。閘極結構或閘極堆疊可沿著半導體鰭116的通道區的側壁沿伸。
在第18A和18B的圖中，在第一層間介電質140上沉積第二層間介電質150。在一實施例中，第二層間介電質150為藉由流動式化學氣相沉積(FCVD)方法形成的可流動膜。一些實施例中，第二層間介電質150由介電材料形成，例如磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)、未摻雜的矽酸鹽玻璃(USG)等，且可使用任何合適的方法以沉積，例如化學氣相沉積(CVD)和電漿增強化學氣相沉積(PECVD)。
在第19A和19B圖中，形成穿過第二層間介電質150 和第一層間介電質140的閘極接觸152和源/汲極接觸154。形成穿過過第二層間介電質150和第一層間介電質140的源/汲極接觸154的開口，以及穿過第二層間介電質150的閘極接觸152的開口。可=使用可接受的微影和蝕刻技術以形成前述的開口。在一實施例中，如第19B圖所示，前述的開口延伸進入磊晶的源/汲極區139一段深度使得開口的底面在三角形間隙物延伸部117的底面S1上或與底面S1齊平，且在三角形間隙物延伸部117的頂面S2下或與頂面S2齊平。可在前述的開口內形成襯層(例如擴散阻障層、黏著層等)和導電材料。襯層可包含鈦、氮化鈦、鉭、氮化鉭等。
在形成閘極接觸152及/或源/汲極接觸154之前，可選擇性地形成矽化物接觸156。矽化物接觸156可包括鈦、鎳、鈷或鉺，且可用以降低閘極接觸152及/或源/汲極接觸154的蕭特基能障高度(Schottky barrier height)。然而，也可使用其他材料，例如鉑、鈀等。可藉由毯覆性沉積合適的金屬層，接著進行退火步驟使金屬與下方露出的矽反應以實施矽化。然後移除未反應的金屬，例如使用選擇性蝕刻製程。在示範的實施例中，在磊晶的源/汲極區139內形成矽化物接觸156，使得矽化物接觸156設置在三角形間隙物延伸部117之間。一些實施例中，如第19B圖所示，可沿著源/汲極接觸的底面和側壁的下部分以U形設置矽化物接觸156。在一實施例中，矽化物接觸156在其頂面與底面之間可具有約3至約15nm的厚度，且在相對兩側壁之間可具有約1nm與約10nm之間的寬度。
可用導電材料形成閘極接觸152和源/汲極接觸154，例如Al、Cu、W、Co、Ti、Ta、Ru、TiN、TiAl、TiAlN、TaN、TaC、NiSi、CoSi、這些的組合或其他相似的材料，然而也可使用任何合適 的材料。可使用沉積製程在第一層間介電質140和第二層間介電質150的開口內沉積閘極接觸152和源/汲極接觸154的材料以填充及/或溢出開口，沉積製程例如濺鍍、化學氣相沉積、電鍍、無電電鍍或相似的製程。填充或溢出開口之後，可使用平坦化製程(例如化學機械研磨)移除開口外的沉積材料。在形成源/汲極接觸154的期間，三角形間隙物延伸部117將阻擋不安定的金屬自源/汲極接觸154向外擴散。如此減少不安定的金屬的向外擴散將降低源/汲極區寄生電容並改善產品的可靠度。
閘極接觸152與填充材料148物理性和電性連接，且源/汲極接觸154與磊晶的源/汲極區139物理性和電性連接。第19A和19B圖顯示閘極接觸152和源/汲極接觸154在相同的剖面，然而，在其他實施例中，閘極接觸152和源/汲極接觸154可設置在不同的剖面。再者，閘極接觸152和源/汲極接觸154在第19A和19B圖的位置僅做為顯示，並非意圖以任何方式進行限定。舉例而言，閘極接觸152可垂直地對齊顯示的半導體鰭116的一者，或者可設置在填充材料148上的不同位置。另外，源/汲極接觸154可在閘極接觸152之前、同時或之後形成。
如上所討論，為了改善可靠度，手機晶片有低耗電的需求。降低耗電量取決於降低源/汲極區的寄生電容。不像傳統結構中接觸金屬與源/汲極磊晶之間界面的低熱穩定度可能導致低良率和較差的可靠度，在此揭露的實施例因具有三角形輪廓的間隙物延伸部做為向外擴散的金屬阻擋層，可降低寄生電容和耗電量，進而加速裝置效能、改善良率和可靠度。前述的製程在不需要改變其他循環製程的情況下可相容於標準的整合製造流程。至少一些在此所 描述的實施例可延伸至使用需要改變形狀之磊晶技術的任何製程，例如微機電系統(MEMS)裝置、三維積體電路(3DIC)裝置等。
在一實施例中，半導體裝置的製造方法包含在半導體層上形成第一虛設閘極和第二虛設閘極。使用第一虛設閘極和第二虛設閘極作為第一遮罩蝕刻半導體層。蝕刻半導體層在半導體層內形成設置在第一虛設閘極與第二虛設閘極之間的第一凹陷。在第一虛設閘極的側壁上形成第一間隙物，且在第二虛設閘極的側壁上形成第二間隙物。第一間隙物和第二間隙物形成接觸第一凹陷的底面的三角形間隙物延伸部。在形成第一間隙物和第二間隙物之後，在半導體層內形成設置在第一虛設閘極與第二虛設閘極之間的第二凹陷。在第二凹陷內磊晶成長源/汲極區。在一實施例中，形成第二凹陷底切三角形間隙物延伸部。在一實施例中，在源/汲極區上形成接觸。前述的接觸延伸一段深度在三角形間隙物延伸部的底面上或與三角形間隙物延伸部的底面齊平，以及在三角形間隙物延伸部的頂面下或與三角形間隙物延伸部的頂面齊平。在一實施例中，以使用第一間隙物和第二間隙物做為第二遮罩的異向性蝕刻形成第二凹陷。在一實施例中，形成三角形間隙物延伸部具有角落輪廓高度在約1nm至約10nm之間，且具有角落輪廓寬度在約1nm至約10nm之間。在一實施例中，形成三角形間隙物延伸部具有角落輪廓高度與角落輪廓寬度的比值在約0.1到1.0之間。
根據另一個實施例，半導體裝置的製造方法包含在基底上磊晶成長半導體層。在半導體層上形成第一閘極。使用第一閘極作為遮罩蝕刻半導體層。蝕刻半導體層在半導體層內形成與第一閘極相鄰的第一和第二凹陷。在第一閘極的側壁上形成間隙物。 間隙物形成接觸第一凹陷的底面的三角形間隙物延伸部。使用間隙物作為遮罩在半導體層內形成第二凹陷。在第二凹陷內形成源/汲極區。在源/汲極區上形成接觸。在一實施例中，半導體層包含SiGe，且SiGe的鍺百分比在約10%至50%之間。在一實施例中，蝕刻包含SiGe的半導體層係沿著SiGe的結晶面。在一實施例中，蝕刻半導體層為乾式蝕刻製程。在一實施例中，乾式蝕刻製程是以Cl2、HBr或HF來實施。在一實施例中，形成間隙物由形成複數個子間隙物組成。在一實施例中，為了形成接觸，蝕刻源/汲極區以形成第三凹陷至一段深度與三角形間隙物延伸部的底面齊平。在一實施例中，在第三凹陷內沉積金屬，且對金屬退火以形成矽化物。在一實施例中，形成接觸使得接觸的底面在三角形間隙物延伸部的頂面下，且在三角形間隙物延伸部的底面上。
根據又一個實施例，裝置包含具有鰭的基底。自鰭延伸出第一閘極。在鰭內設置與第一閘極相鄰的源/汲極區。在源/汲極區上設置接觸。沿著第一閘極的側壁設置間隙物。間隙物形成延伸至低於第一閘極下的鰭的最頂面的三角形間隙物延伸部。在一實施例中，三角形間隙物延伸部具有高度在約1nm與約10nm之間，以及具有寬度在約1nm與約10nm之間。在一實施例中，間隙物由複數個子間隙物組成。在一實施例中，矽化物區與三角形間隙物延伸部齊平，且接觸直接坐落於矽化物區上。在一實施例中，鰭包含SiGe，且具有約10%至約50%的鍺百分比。
以上概述數個實施例或範例之特徵，以便在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發 明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例或範例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並無悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例之精神和範圍之下，做各式各樣的改變、取代和替換。
100:基底
114:磊晶層
117:三角形間隙物延伸部
134:第一閘極子間隙物
135:第二閘極子間隙物
136:第三閘極子間隙物
137:閘極間隙物
139:磊晶的源/汲極區
140:第一層間介電質
144:閘極介電層
146:閘極電極
147:金屬功函數層
148:填充材料
150:第二層間介電質
152:閘極接觸
154:源/汲極接觸
156:矽化物接觸
S1:底面
S2:頂面

Claims (10)

  1. 一種半導體裝置的製造方法，包括：在一半導體層上形成一第一虛設閘極和一第二虛設閘極；使用該第一虛設閘極和該第二虛設閘極作為一第一遮罩蝕刻該半導體層，其中蝕刻該半導體層在該半導體層內形成設置在該第一虛設閘極與該第二虛設閘極之間的一第一凹陷；在該第一虛設閘極的側壁上形成一第一間隙物，且在該第二虛設閘極的側壁上形成一第二間隙物，其中該第一間隙物和該第二間隙物形成接觸該第一凹陷的一底面的三角形間隙物延伸部；在形成該第一間隙物和該第二間隙物之後，在該半導體層內形成設置在該第一虛設閘極與該第二虛設閘極之間的一第二凹陷；以及在該第二凹陷內形成一源/汲極區。
  2. 如請求項1之半導體裝置的製造方法，其中形成該第二凹陷而底切該三角形間隙物延伸部。
  3. 如請求項1或2之半導體裝置的製造方法，更包括在該源/汲極區上形成一接觸，該接觸延伸一段深度在該三角形間隙物延伸部的底面上或與該三角形間隙物延伸部的底面齊平，以及在該三角形間隙物延伸部的頂面下或與該三角形間隙物延伸部的頂面齊平。
  4. 一種半導體裝置的製造方法，包括：在一基底上磊晶成長一半導體層；在該半導體層上形成一第一閘極；使用該第一閘極作為遮罩來蝕刻該半導體層，其中蝕刻該半導體層在該半導體層內形成與該第一閘極相鄰的一第一凹陷和一第二凹 陷；在該第一閘極的側壁上形成一間隙物，其中該間隙物形成接觸該第一凹陷的底面的三角形間隙物延伸部；使用該間隙物作為遮罩在該半導體層內形成一第二凹陷；在該第二凹陷內形成一源/汲極區；以及在該源/汲極區上形成一接觸。
  5. 如請求項4之半導體裝置的製造方法，其中該半導體層包含SiGe，且SiGe的鍺百分比在約10%至50%之間。
  6. 如請求項5之半導體裝置的製造方法，其中蝕刻包含SiGe的該半導體層係沿著SiGe的結晶面蝕刻。
  7. 一種半導體裝置，包括：具有一鰭的一基底；一第一閘極，在該鰭上；一源/汲極區，在該鰭內且與該第一閘極相鄰；一接觸，在該源/汲極區上；以及一間隙物，沿著該第一閘極的側壁，該間隙物包括三角形間隙物延伸部，該三角形間隙物延伸部延伸至低於該第一閘極下的該鰭的最頂面。
  8. 如請求項7之半導體裝置，其中該間隙物包括複數個子間隙物。
  9. 如請求項7之半導體裝置，其中該接觸直接坐落於矽化物區上，其中該矽化物區與該三角形間隙物延伸部齊平。
  10. 如請求項7至9任一項之半導體裝置，其中該三角形間隙物延伸部在該源/汲極區的一部分的上方延伸。
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