CN110957272A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN110957272A
CN110957272A CN201910891887.0A CN201910891887A CN110957272A CN 110957272 A CN110957272 A CN 110957272A CN 201910891887 A CN201910891887 A CN 201910891887A CN 110957272 A CN110957272 A CN 110957272A
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gate
layer
source
dummy gate
semiconductor
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李昆穆
李彦儒
宋学昌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了一种半导体装置的制造方法，可在第一虚设栅极与第二虚设栅极之间设置半导体层内的第一凹陷。在第一虚设栅极的侧壁上形成第一间隙物，以及在第二虚设栅极的侧壁上形成第二间隙物。第一和第二间隙物形成接触第一凹陷的底面的三角形间隙物延伸部。在形成第一和第二间隙物之后，在半导体层内形成设置在第一虚设栅极与第二虚设栅极之间的第二凹陷。在第二凹陷内外延成长源/漏极区。

Description

半导体装置的制造方法
技术领域
本发明的一些实施例涉及半导体装置的制造方法，特别涉及具有三角形间隙物延伸部的半导体装置及其形成方法。
背景技术
半导体装置被用于各式各样的电子应用中，例如个人电脑、手机、数码相机和其他电子设备。典型上，半导体装置的制造是借着在半导体基底上按序沉积绝缘或介电层、导电层和半导体层的材料，且使用光刻(lithography)将各种材料层图案化以在半导体基底上形成电路组件及元件。
在半导体产业通过持续地降低最小部件尺寸来改善各种电子组件(例如晶体管、二极管、电阻器、电容器等)的整合密度，使得更多的组件可整合至给定的面积中。然而，降低最小部件尺寸的同时也产生额外需处理的问题。
由于鳍式场效晶体管(FinFET)的小尺寸和高效能，其在集成电路制造的应用越来越多。完全应变的通道进一步改善了鳍式场效晶体管的效能，但仍需处理因完全应变的通道架构所产生的缺陷。
发明内容
在一实施例中，半导体装置的制造方法包含在半导体层上形成第一虚设栅极和第二虚设栅极。使用第一虚设栅极和第二虚设栅极作为第一遮罩蚀刻半导体层。蚀刻半导体层在半导体层内形成设置在第一虚设栅极与第二虚设栅极之间的第一凹陷。在第一虚设栅极的侧壁上形成第一间隙物，且在第二虚设栅极的侧壁上形成第二间隙物。第一间隙物和第二间隙物形成接触第一凹陷的底面的三角形间隙物延伸部。在形成第一间隙物和第二间隙物之后，在半导体层内形成设置在第一虚设栅极与第二虚设栅极之间的第二凹陷。在第二凹陷内外延成长源/漏极区。
根据另一个实施例，半导体装置的制造方法包含在基底上外延成长半导体层。在半导体层上形成第一栅极。使用第一栅极作为遮罩蚀刻半导体层。蚀刻半导体层在半导体层内形成与第一栅极相邻的第一和第二凹陷。在第一栅极的侧壁上形成间隙物。间隙物形成接触第一凹陷的底面的三角形间隙物延伸部。使用间隙物作为遮罩在半导体层内形成第二凹陷。在第二凹陷内形成源/漏极区。在源/漏极区上形成接触。
根据又一个实施例，装置包含具有鳍的基底。自鳍延伸出第一栅极。在鳍内设置与第一栅极相邻的源/漏极区。在源/漏极区上设置接触。沿着第一栅极的侧壁设置间隙物。间隙物形成延伸至低于第一栅极下的鳍的最顶面的三角形间隙物延伸部。
附图说明
通过以下的详述配合说明书附图，我们能更加理解本发明实施例的内容。需注意的是，根据产业上的标准做法，许多部件(feature)并未按照比例绘制。事实上，为了能清楚地讨论，这些部件的尺寸可能被任意地增加或减少。
图1是根据一些实施例，显示鳍式场效晶体管的范例的三维(three-dimensional)示意图。
图2至图19B是根据一些实施例，显示形成鳍式场效晶体管的各个中间步骤的剖面示意图。
附图标记说明：
50～基底；
56～隔离区；
58～鳍；
82～源/漏极区；
92～栅极介电层；
94～栅极电极；
100～基底；
111～轻掺杂源/漏极区；
114～外延层；
115～第一凹陷；
116～半导体鳍；
117～三角形间隙物延伸部；
118～衬层；
120～介电材料；
122～绝缘材料；
124～浅沟槽隔离区；
130～虚设栅极层；
131～虚设栅极；
132～遮罩层；
133～遮罩；
134～第一栅极子间隙物；
135～第二栅极子间隙物；
136～第三栅极子间隙物；
137～栅极间隙物；
138～第二凹陷；
139～外延的源/漏极区；
140～第一层间介电质；
142～凹陷；
144～栅极介电层；
146～栅极电极；
147～金属功函数层；
148～填充材料；
150～第二层间介电质；
152～栅极接触；
154～源/漏极接触；
156～硅化物接触；
D1、D2～第一深度；
H1～高度；
S1～底面；
S2～顶面；
W1、W2～宽度；
α～角度。
具体实施方式
以下公开提供了很多不同的实施例或范例，用于实施本发明的不同部件。组件和配置的具体范例描述如下，以简化本公开的说明。当然，这些仅仅是范例，并非用以限定本发明实施例。举例而言，以下叙述中提及第一部件形成于第二部件之上或上方，可能包含第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。此外，本公开可在各个范例中重复参考数字及/或字母，如此重复是为了简化和清楚的目的，并非为了指定在此所讨论的各个实施例及/或组态之间的关系。
再者，空间上的相关用语，例如“在……下方”、“下方”、“较低的”、“上方”、“较高的”及相似的用语可用于此以使本公开更容易地叙述附图中一个元件或部件与另一个(或另一些)元件或部件之间的关系。这些空间上的相关用语意欲涵盖除了附图所描绘的方向之外，使用或操作中的装置的不同方向。设备可以其他方向定位(旋转90度或其他方向)，且在此使用的空间相关描述可同样依此解读。
尽管不是限定本公开，鳍式场效晶体管的制造可涵盖许多实施例。在这样的实施例中，以下叙述的工艺可在相应的鳍上实施。通过本公开的内容，本发明所属技术领域中技术人员将可以理解在此提供的启示的各种替代和延伸，且这些都在本公开涵盖的范围内。举例来说，虽然显示的实施例为鳍式场效晶体管，本发明所属技术领域中技术人员将能识别出上述启示在像是平面(planar)晶体管、微机电系统(MEMS)装置、三维集成电路(3DIC)装置等的适用性。
本发明的一些实施例也可包含其他部件和工艺。举例而言，可包含测试结构以帮助对于三维(3D)封装或三维集成电路装置的验证测试。举例而言，测试结构可包含形成在重布线层内或形成在基底上的测试垫(test pad)，以便能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等等。可对中间结构和最终结构进行验证测试。另外，在此公开的结构和方法可与测试方法结合使用，以提高良率并降低成本。
在此公开的一或多个实施例的优势部件包含因具有三角形轮廓的间隙物延伸部做为向外扩散的金属阻挡层所产生的低源/漏极电容，进而产生更快的装置效能、优选的良率和产品可靠度。为了改善可靠度，手机芯片有低耗电的需求，这取决于降低源/漏极区的寄生电容。不像传统结构中接触金属与源/漏极外延之间界面的低热稳定度(thermalstability)可能导致低良率和较差的可靠度，在此公开的实施例是提供以改善良率和可靠度。在此叙述及/或显示的至少一些实施例的进一步优势部件包含因间隙物下方的通道轮廓而产生的较低的电容、改善的良率和稳定度。工艺在不需要改变其他循环工艺的情况下可相容于标准的整合制造流程。至少一些在此叙述的实施例可延伸至使用需要改变形状的外延技术的其他实施例，例如微机电系统装置、三维集成电路(3DIC)装置等。
图1是根据一些实施例，显示鳍式场效晶体管的范例的三维示意图做为参考。鳍式场效晶体管包括在基底50(例如半导体基底)上的鳍58。在基底50内设置隔离区56，鳍58自邻近的隔离区56突出，且突出于邻近的隔离区56上。虽然叙述及附图显示隔离区56与基底50隔开，在此使用的用语“基底”可用来单指半导体基底，或包含隔离区56的半导体基底。栅极介电层92在鳍58的顶面上且沿着鳍58的侧壁，与门极电极94在栅极介电层92上。在鳍58的相对两侧内相对于栅极介电层92和栅极电极94设置源/漏极区82。图1进一步显示用于继续的附图中的参考剖面示意图。剖面A-A是沿着栅极电极94的纵轴，且以与鳍式场效晶体管的源/漏极区82之间的电流方向垂直的方向为例。剖面B-B与剖面A-A垂直，且沿着鳍58的纵轴，例如鳍式场效晶体管的源/漏极区82之间的电流方向。剖面C-C平行于剖面A-A，且延伸穿过鳍式场效晶体管的源/漏极区82的其中一者。后续的附图参照这些参考剖面以清楚描述。
在此讨论的一些实施例是以使用栅极后制(gate-last)工艺形成的鳍式场效晶体管的内容进行讨论。在其他实施例中，可使用栅极先制(gate-first)工艺。再者，一些实施例涵盖用于平面装置的方案，例如平面式场效晶体管。
图2至图19B是根据一些实施例，制造鳍式场效晶体管的中间步骤的剖面示意图。除了显示多个鳍/鳍式场效晶体管以外，图2至图7显示图1中显示的参考剖面A-A。在图8A至图9B和图14A至图19B中，以“A”结尾的附图编号是显示沿着图1显示的参考剖面A-A(除了显示多个鳍/鳍式场效晶体管以外)，而以“B”结尾的附图编号是显示沿着图1显示的相似剖面B-B。图10至图13是显示沿着图1显示的剖面B-B。
在图2中，提供基底100。基底100可为半导体基底，例如块材半导体，绝缘体上覆半导体(semiconductor-on-insulator，SOI)基底等，基底可经掺杂(例如经P型掺质或N型掺质的掺杂)或未经掺杂(undoped)。基底100可为晶圆，例如硅晶圆。一般而言，绝缘体上覆半导体(SOI)基底为形成于绝缘层上的半导体材料层。绝缘层可例如为埋置氧化物(buriedoxide，BOX)层、氧化硅层等。在基底(典型上为硅或玻璃基底)上提供绝缘层。也可使用其他基底，例如多层或梯度(gradient)基底。
基底100可具有形成在其中的N型井区或P型井区(未明确示出)。可通过在基底100上实施离子植入工艺以在基底100内形成N型井区或P型井区。可将N型掺质(例如砷离子)植入基底100以形成N型井区。可将P型掺质(例如硼离子)植入基底100以形成P型井区。
在图3中，在基底100上形成外延层114。可例如通过外延成长或其他相似的工艺以形成外延层114。外延层114可包括像是硅锗(SiGe)的材料或相似的材料，且可经掺杂(例如经P型掺质或N型掺质的掺杂)或未经掺杂。在一实施例中，外延层114包括SiGe，且锗百分比在约10％与约50％之间。SiGe包括与Si相比较低的能隙(bandgap)，允许对后续形成的P型金属氧化物半导体(p-type metal oxide semiconductor，PMOS)装置提供较大的空穴移动率。可在外延层114上实施平坦化工艺。可通过任何合适的平坦化工艺将外延层114平坦化，例如化学机械研磨(chemical mechanical polish，CMP)、回蚀(etch-back)工艺、前述的组合等。一些实施例中，在平坦化工艺之后，外延层可具有在约
Figure BDA0002209000360000061
与约
Figure BDA0002209000360000062
之间的厚度。
在图4中，蚀刻外延层114和基底100以形成半导体鳍116(又称为第一半导体鳍)。一些实施例中，可通过在外延层114和基底100内蚀刻沟槽以形成第一半导体鳍116。前述的蚀刻可为一或多道任何可接受的蚀刻工艺，例如反应式离子蚀刻(reactive ion etch，RIE)、中性粒子束蚀刻(neutral beam etch，NBE)等、或前述的组合。前述的蚀刻可为异向性(anisotropic)。虽然显示的半导体鳍116具有圆弧的角落和线性的边缘，然而半导体鳍116可具有任何其他合适的形状，例如具有渐细(tapered)的侧壁。一些实施例中，半导体鳍116可具有在约
Figure BDA0002209000360000071
与约
Figure BDA0002209000360000072
之间的高度。
可通过任何合适的方法将半导体鳍116图案化。举例而言，可使用一或多道光刻工艺将半导体鳍116图案化，光刻工艺包含双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光刻和自对准(self-aligned)工艺，允许形成间距小于使用单一、直接地光刻工艺所获得之间距的图案。虽然并未另外显示双重图案化或多重图案化工艺，在一实施例中，双重图案化或多重图案化工艺可包含在基底上形成牺牲层。使用光刻工艺将牺牲层图案化。使用自对准工艺沿着牺牲层的侧边形成间隙物。然后移除牺牲层，且用剩余的间隙物将第一半导体鳍116图案化。
在半导体鳍116内包含由例如硅锗形成的外延层114，可增加随后形成的PMOS晶体管的空穴移动率(mobility)。另外，由于锗相较于硅具有较小的能隙，在半导体鳍116内包含外延层114可在随后形成的PMOS晶体管内产生较高的电流。在预定形成N型金属氧化物半导体(N-type metal-oxide semiconductor，NMOS)晶体管的实施例中，外延层114可以由可提高载子移动率的材料形成，例如碳化硅。碳化硅可经N型掺质掺杂，例如磷。
在图5中，在基底100和半导体鳍116上形成绝缘材料122，填入半导体鳍之间的开口中。一些实施例中，如图5所示，绝缘材料122包含衬层118和在衬层118上的介电材料120。衬层118可形成为共形(conformal)层，共形层的水平部分和垂直部分具有彼此相近的厚度。
一些实施例中，通过在含氧的环境中将基底100和半导体鳍116暴露的表面氧化以形成衬层118。例如通过局部硅氧化(local oxidation of silicon，LOCOS)，其中可在各自的工艺气体中包含氧气(O2)。在其他的实施例中，可例如使用氢气(H2)和氧气(O2)的组合气体、或水蒸气的原位蒸气产生(in-situ steam generation，ISSG)以氧化基底100和半导体鳍116暴露的表面。在其他的实施例中，使用沉积技术以形成衬层118，像是原子层沉积(atomic layer deposition，ALD)、化学气相沉积(chemical vapor deposition，CVD)、次大气压化学气相沉积(sub-atmospheric chemical vapor deposition，SACVD)等或前述的组合。一些实施例中，衬层118具有在约
Figure BDA0002209000360000081
与约
Figure BDA0002209000360000082
之间的厚度。
形成介电材料120填入半导体鳍116之间的开口的剩余部分。介电材料120可能溢出(overfill)半导体鳍116之间的开口，使得一部分的介电材料120延伸至半导体鳍116的顶面上。一些实施例中，介电材料120可包括氧化硅、碳化硅、氮化硅等或前述的组合，且可使用流动式化学气相沉积(flowable chemical vapor deposition，FCVD)、旋转涂布(spin-on coating)、化学气相沉积(CVD)、原子层沉积(ALD)、高密度等离子体化学气相沉积(high density plasma chemical vapor deposition，HDPCVD)、低压化学气相沉积(lowpressure chemical vapor deposition，LPCVD)等或前述的组合以形成。在沉积介电材料120之后，可实施退火/固化(curing)步骤，将流动式的介电材料120转变为固态的介电材料。一些实施例中，由于不同的材料特性(像是不同类型的材料及/或不同密度)，衬层118和介电材料120之间的界面是可分辨的。
在图6中，对绝缘材料122施以平坦化工艺。一些实施例中，平坦化工艺包含化学机械研磨(CMP)、回蚀工艺、前述的组合等。如图6所显示，平坦化工艺可露出半导体鳍116的顶面。也可通过平坦化工艺将部分的半导体鳍116平坦化。在完成平坦化工艺之后，半导体鳍116和绝缘材料122的顶面为齐平的(在工艺变异度内)。
在图7中，将绝缘材料122凹陷以形成浅沟槽隔离(shallow trench isolation，STI)区124。将绝缘材料122凹陷使得半导体鳍116自相邻的浅沟槽隔离区124突出。使用可接受的蚀刻工艺将浅沟槽隔离区124凹陷，例如对浅沟槽隔离区124的材料具有选择性的。举例而言，使用无等离子体(plasma-less)气体蚀刻工艺(例如使用氢氟酸(HF)气体、氨气(NH3)等的蚀刻工艺)、远程等离子体辅助干式蚀刻工艺(例如使用氢气(H2)、三氟化氮(NF3)和氨的副产物等的工艺)，或稀释氢氟酸(dHF)的化学氧化物移除方式。
在图8A和图8B中，在半导体鳍116和浅沟槽隔离区124上形成虚设栅极层130，且在虚设栅极层130上形成遮罩层132。在形成虚设栅极层130之前，可在半导体鳍116和浅沟槽隔离区124上形成虚设介电层(未明确示出)。虚设介电层可例如为氧化硅、氮化硅、前述的组合等，且根据可接受的技术进行沉积或热成长。可在半导体鳍116上沉积虚设栅极层130，然后将虚设栅极层130平坦化，例如通过化学机械研磨(CMP)。可在虚设栅极层130上沉积遮罩层132。虚设栅极层130可例如为非晶硅、多晶硅(polysilicon)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物和金属。可通过物理气相沉积(physical vapordeposition，PVD)、化学气相沉积(CVD)、溅镀(sputtering)沉积、或其他已知且在本发明所属技术领域用以沉积导电材料的技术以沉积虚设栅极层130。虚设栅极层130可由相对于隔离区的蚀刻具有高蚀刻选择性的材料制成。遮罩层132可例如包含SiN、SiON等。
在图9A和图9B中，使用可接受的光刻和蚀刻技术将遮罩层132(见图8A和图8B)图案化以形成遮罩133。通过可接受的蚀刻技术，将遮罩133的图案转移至虚设栅极层130以形成虚设栅极131。虚设栅极131覆盖半导体鳍116各自的通道区。遮罩133的图案可用以将每一个虚设栅极131与相邻的虚设栅极131物理性地隔开。虚设栅极131也可具有纵向方向，大抵上垂直于半导体鳍116的纵向方向。
在图10中，使用虚设栅极131做为遮罩蚀刻外延层114，以在虚设栅极131的任一侧形成第一凹陷115。在外延层114包括硅锗的实施例中，前述的蚀刻可包括使用Cl2、HBr、HF、SF6、CHF3、CH2F2、CF4、SO2、NH3、NF3、He、SiCl4、O2、Ar、H2及/或其他气体蚀刻剂的干式蚀刻工艺。可在约室温与约500℃之间的温度下，约10-3毫托(mTorr)与约760毫托(mTorr)之间的压力下进行前述的蚀刻，且进行的时间区段在约0.1秒与约500秒之间。如图10所示，由于是沿着外延层114的硅锗的结晶面进行蚀刻，产生的第一凹陷115中外延层114的表面将具有浅的凹面。在一实施例中，第一凹陷115可具有第一深度D1，自第一凹陷115的最低点测量至与外延层114的顶面齐平处的第一深度D1在约1nm与10nm之间。如图10所示，第一凹陷115可具有宽度，在虚设栅极131的相邻侧壁之间测量的宽度在约20nm与约200nm之间，且在与外延层114的顶面齐平的表面与第一凹陷115的侧壁之间的角度α在约5度与约60度之间。
在图11中，沿着虚设栅极131和遮罩133的侧壁形成栅极间隙物137。在一实施例中，如图11所示，栅极间隙物137的形成可通过在虚设栅极131和遮罩133的顶面和侧壁上共形地沉积材料，以及随后异向性地蚀刻前述的材料，以移除位于遮罩133的顶面上的部分，以及位于自虚设栅极131的侧壁起算的宽度W1更远的部分。栅极间隙物137的材料可为氮化硅、SiCN、SiOC、SiOCN、前述的组合等。
在各种不同的实施例中，栅极间隙物137可包括多个栅极子间隙物(subspacer)。在第11-19B图显示的一实施例中，栅极间隙物137包括三个栅极子间隙物：第一栅极子间隙物134、第二栅极子间隙物135和第三栅极子间隙物136。第一栅极子间隙物134为在后续工艺期间移除虚设栅极131的蚀刻停止层。第一栅极子间隙物134可具有在约0.5nm与约5nm之间的厚度。在一实施例中，第二栅极子间隙物135降低装置结构的电容。第二栅极子间隙物135可具有在约0.5nm与约5nm之间的厚度。在一实施例中，第三栅极子间隙物136可为虚设或牺牲间隙物层，做为后续的生产工艺中的牺牲蚀刻停止层。第三栅极子间隙物136可具有在约1nm与约10nm之间的厚度。第一栅极子间隙物134和第二栅极子间隙物135可包括相同材料或可包括不同材料。在一实施例中，第三栅极子间隙物136包括至少不同于第二栅极子间隙物135的材料，以做为牺牲蚀刻停止层。
在形成第一栅极子间隙物134之后，可实施轻掺杂源/漏极(lightly dopedsource/drain，LDD)区111的植入。在一些例如PMOS装置的实施例中，可在暴露的半导体鳍116内植入合适类型(例如P型)的杂质。P型杂质可为硼、BF2等。在其他例如NMOS装置的实施例中，可在暴露的半导体鳍116内植入合适类型(例如N型)的杂质。N型杂质可为磷、砷等。轻掺杂源/漏极区111可具有约1015cm-3至约1016cm-3的杂质浓度。可使用退火以活化植入的杂质。图11显示轻掺杂源/漏极区111不具限定性的范例。轻掺杂源/漏极区111也可能具有其他组态、形状和形成方法，且完全涵盖于本公开的范围内。另外，栅极间隙物可具有不同的组态，例如包含各种数量的子间隙物、各种形状(像是L形间隙物)及/或其他相似的组态。在后续的附图中，轻掺杂源/漏极区111并非仅为了显示目的而示出。
在一实施例中，栅极间隙物137将延伸至第一凹陷115的底面，形成如图11所示的三角形间隙物延伸部117。三角形间隙物延伸部117会阻挡金属自金属接触扩散至源/漏极区，借此降低装置的寄生电容。在一实施例中，三角形间隙物延伸部117可包括延伸进入第一凹陷115的三角形的轮廓。在一实施例中，如图11所示，三角形间隙物延伸部117包括在约1nm与约10nm之间的高度H1，以及在约1nm与约10nm之间的宽度W1。在各种不同的实施例中，高度H1与宽度W1的比值可在约0.1至10之间。这些尺寸和比值与装置的效能和寄生电容之间具有强烈的关联，当高度H1与宽度W1的比值大时，可能导致装置的效能衰退，而当高度H1与宽度W1的比值小时，可能导致过高的源/漏极区寄生电容。
在图12中，使用栅极间隙物137做为遮罩，在外延层114内形成第二凹陷138。形成与第一凹陷115的深度D1相比具有较大深度D2的第二凹陷138。第二凹陷138的深度D2可在约35nm与70nm之间。一些实施例中，第二凹陷138可延伸穿过外延层114进入基底100。第二凹陷138可由使用Cl2、HBr、HF、SF6、CHF3、CH2F2、CF4、SO2、NH3、NF3、He、SiCl4、O2、Ar、H2及/或其他气体蚀刻剂的异向性蚀刻以形成。可在约室温与约500℃之间的温度下，约10-3mTorr与约760mTorr之间的压力下进行前述的蚀刻，且进行的时间区段在约0.1秒与约500秒之间。如图12所示，第二凹陷138的蚀刻可能对三角形间隙物延伸部产生宽度W2的底切(undercut)，而宽度W2在0nm与5nm之间。
在图13中，可在第二凹陷138内外延成长形成外延的源/漏极区139。一些实施例中，外延的源/漏极区139可延伸穿过外延层114进入基底100。一些实施例中，使用第二栅极子间隙物135将外延的源/漏极区139与虚设栅极131隔开适度的横向距离，使得外延的源/漏极区139不会使后续形成的鳍式场效晶体管的栅极之间产生短路。
一些实施例中，外延的源/漏极区139可包含任何适合P型鳍式场效晶体管的可接受材料。举例而言，外延的源/漏极区139可包含SiGe、SiGeB、Ge、GeSn等。可由与外延层114的晶格常数相比具有较大晶格常数的材料来形成外延的源/漏极区139，在通道区内产生压缩应力以增加PMOS装置的空穴移动率。在示范的实施例中，外延的源/漏极区139包括SiGeB，且锗百分比与外延层114包括的SiGe的锗百分比相比高约20％。外延的源/漏极区139可具有自半导体鳍116各自的表面抬升的表面，且可具有晶面(facet)。
在其他实施例中，外延的源/漏极区139可包含任何适合N型鳍式场效晶体管的可接受材料。举例而言，外延的源/漏极区139可包含Si、SiC、SiCP、SiP等。可由与外延层114的晶格常数相比具有较小晶格常数的材料来形成外延的源/漏极区139，在通道区内产生拉伸应力以增加NMOS装置的电子移动率。外延的源/漏极区139也可具有自半导体鳍116各自的表面抬升的表面，且可具有晶面。
相似于先前讨论形成轻掺杂源/漏极区，随后进行退火的工艺，可对外延的源/漏极区139及/或半导体鳍116植入掺质以形成源/漏极区。源/漏极区可具有在约1019cm-3到约1021cm-3之间的杂质浓度。源/漏极区的P型杂质可为任何先前讨论的杂质。一些实施例中，外延的源/漏极区139可在成长期间原位(in-situ)掺杂。
根据一些实施例，在图14A和图14B中，沉积第一层间介电质(first interlayerdielectric，ILD)140。第一层间介电质140可由介电材料形成，且可通过任何合适的方法沉积，例如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)或流动式化学气相沉积(FCVD)。介电材料可包含磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺硼磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、未掺杂的硅酸盐玻璃(undoped silicate glass，USG)等。也可使用任何可接受的工艺所形成的其他绝缘物。一些实施例中，在第一层间介电质140与外延的源/漏极区139、遮罩133和栅极间隙物137之间设置接触蚀刻停止层(contact etch stop layer，CESL)(未明确示出)。
在图15A和图15B中，可实施平坦化工艺(例如化学机械研磨(CMP))以使第一层间介电质140的顶面与虚设栅极131的顶面齐平。平坦化工艺也可移除虚设栅极131上的遮罩133，以及栅极间隙物137沿着遮罩133侧壁的部分。在平坦化工艺之后，虚设栅极131、栅极间隙物137和第一层间介电质140的顶面齐平。因此，虚设栅极131的顶面由第一层间介电质140露出。
在图16A和图16B中，在(多个)蚀刻步骤中移除虚设栅极131，使形成凹陷142。一些实施例中，通过异向性干式蚀刻工艺移除虚设栅极131。举例而言，蚀刻工艺可包含干式蚀刻工艺，使用在不蚀刻第一层间介电质140或栅极间隙物136的情况下选择性地蚀刻虚设栅极131的(多个)蚀刻气体。每一个凹陷142露出各自的半导体鳍116的通道区。每一个通道区是设置在相邻配对的外延的源/漏极区139之间。
在图17A和图17B中，形成取代栅极(replacement gate)的栅极介电层144和栅极电极146。在凹陷142内共形地沉积栅极介电层144，例如在半导体鳍116的顶面和侧壁上，以及在栅极间隙物137的侧壁上。栅极介电层144也可形成在第一层间介电质140的顶面上。根据一些实施例，栅极介电层144包括氧化硅、氮化硅或前述的多层。一些实施例中，栅极介电层144为高介电常数的介电材料，且在这些实施例中，栅极介电层144可具有大于7.0的介电常数值(k value)，且可包含金属氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb的硅化物，和前述的组合。栅极介电层144的形成方法可包含分子束沉积(molecular beam deposition，MBD)、原子层沉积(ALD)、等离子体增强化学气相沉积(PECVD)等。
在栅极介电层144上形成栅极电极146，与门极电极146填入凹陷142的剩余部分。栅极电极146可为含金属的材料，例如TiN、TaN、TaC、Co、Ru、Al、前述的组合或前述的多层。栅极电极146可包含一或多层的导电材料，例如金属功函数层147和填充材料148。在填充栅极电极146之后，可实施平坦化工艺(例如化学机械研磨(CMP))以移除栅极介电层144和栅极电极146的过量部分，过量部分指在第一层间介电质140的顶面上的部分。栅极介电层144和栅极电极146的剩余部分因此形成鳍式场效晶体管的取代栅极。栅极电极146和栅极介电层144可一起称为“栅极结构”或“栅极堆叠”。栅极结构或栅极堆叠可沿着半导体鳍116的通道区的侧壁沿伸。
在图18A和图18B的图中，在第一层间介电质140上沉积第二层间介电质150。在一实施例中，第二层间介电质150为通过流动式化学气相沉积方法形成的可流动膜。一些实施例中，第二层间介电质150由介电材料形成，例如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等，且可使用任何合适的方法以沉积，例如化学气相沉积(CVD)和等离子体增强化学气相沉积(PECVD)。
在图19A和图19B中，形成穿过第二层间介电质150和第一层间介电质140的栅极接触152和源/漏极接触154。形成穿过过第二层间介电质150和第一层间介电质140的源/漏极接触154的开口，以及穿过第二层间介电质150的栅极接触152的开口。可使用可接受的光刻和蚀刻技术以形成前述的开口。在一实施例中，如图19B所示，前述的开口延伸进入外延的源/漏极区139一段深度使得开口的底面在三角形间隙物延伸部117的底面S1上或与底面S1齐平，且在三角形间隙物延伸部117的顶面S2下或与顶面S2齐平。可在前述的开口内形成衬层(例如扩散阻障层、粘着层等)和导电材料。衬层可包含钛、氮化钛、钽、氮化钽等。
在形成栅极接触152及/或源/漏极接触154之前，可选择性地形成硅化物接触156。硅化物接触156可包括钛、镍、钴或铒，且可用以降低栅极接触152及/或源/漏极接触154的萧特基能障高度(Schottky barrier height)。然而，也可使用其他材料，例如铂、钯等。可通过毯覆性沉积合适的金属层，接着进行退火步骤使金属与下方露出的硅反应以实施硅化。然后移除未反应的金属，例如使用选择性蚀刻工艺。在示范的实施例中，在外延的源/漏极区139内形成硅化物接触156，使得硅化物接触156设置在三角形间隙物延伸部117之间。一些实施例中，如图19B所示，可沿着源/漏极接触的底面和侧壁的下部分以U形设置硅化物接触156。在一实施例中，硅化物接触156在其顶面与底面之间可具有约3至约15nm的厚度，且在相对两侧壁之间可具有约1nm与约10nm之间的宽度。
可用导电材料形成栅极接触152和源/漏极接触154，例如Al、Cu、W、Co、Ti、Ta、Ru、TiN、TiAl、TiAlN、TaN、TaC、NiSi、CoSi、这些的组合或其他相似的材料，然而也可使用任何合适的材料。可使用沉积工艺在第一层间介电质140和第二层间介电质150的开口内沉积栅极接触152和源/漏极接触154的材料以填充及/或溢出开口，沉积工艺例如溅镀、化学气相沉积、电镀、无电电镀或相似的工艺。填充或溢出开口之后，可使用平坦化工艺(例如化学机械研磨)移除开口外的沉积材料。在形成源/漏极接触154的期间，三角形间隙物延伸部117将阻挡不安定的金属自源/漏极接触154向外扩散。如此减少不安定的金属的向外扩散将降低源/漏极区寄生电容并改善产品的可靠度。
栅极接触152与填充材料148物理性和电性连接，且源/漏极接触154与外延的源/漏极区139物理性和电性连接。图19A和图19B显示栅极接触152和源/漏极接触154在相同的剖面，然而，在其他实施例中，栅极接触152和源/漏极接触154可设置在不同的剖面。再者，栅极接触152和源/漏极接触154在图19A和图19B的位置仅做为显示，并非意图以任何方式进行限定。举例而言，栅极接触152可垂直地对齐显示的半导体鳍116的一者，或者可设置在填充材料148上的不同位置。另外，源/漏极接触154可在栅极接触152之前、同时或之后形成。
如上所讨论，为了改善可靠度，手机芯片有低耗电的需求。降低耗电量取决于降低源/漏极区的寄生电容。不像传统结构中接触金属与源/漏极外延之间界面的低热稳定度可能导致低良率和较差的可靠度，在此公开的实施例因具有三角形轮廓的间隙物延伸部做为向外扩散的金属阻挡层，可降低寄生电容和耗电量，进而加速装置效能、改善良率和可靠度。前述的工艺在不需要改变其他循环工艺的情况下可相容于标准的整合制造流程。至少一些在此所描述的实施例可延伸至使用需要改变形状的外延技术的任何工艺，例如微机电系统(MEMS)装置、三维集成电路装置等。
在一实施例中，半导体装置的制造方法包含在半导体层上形成第一虚设栅极和第二虚设栅极。使用第一虚设栅极和第二虚设栅极作为第一遮罩蚀刻半导体层。蚀刻半导体层在半导体层内形成设置在第一虚设栅极与第二虚设栅极之间的第一凹陷。在第一虚设栅极的侧壁上形成第一间隙物，且在第二虚设栅极的侧壁上形成第二间隙物。第一间隙物和第二间隙物形成接触第一凹陷的底面的三角形间隙物延伸部。在形成第一间隙物和第二间隙物之后，在半导体层内形成设置在第一虚设栅极与第二虚设栅极之间的第二凹陷。在第二凹陷内外延成长源/漏极区。在一实施例中，形成第二凹陷底切三角形间隙物延伸部。在一实施例中，在源/漏极区上形成接触。前述的接触延伸一段深度在三角形间隙物延伸部的底面上或与三角形间隙物延伸部的底面齐平，以及在三角形间隙物延伸部的顶面下或与三角形间隙物延伸部的顶面齐平。在一实施例中，以使用第一间隙物和第二间隙物做为第二遮罩的异向性蚀刻形成第二凹陷。在一实施例中，形成三角形间隙物延伸部具有角落轮廓高度在约1nm至约10nm之间，且具有角落轮廓宽度在约1nm至约10nm之间。在一实施例中，形成三角形间隙物延伸部具有角落轮廓高度与角落轮廓宽度的比值在约0.1到1.0之间。
根据另一个实施例，半导体装置的制造方法包含在基底上外延成长半导体层。在半导体层上形成第一栅极。使用第一栅极作为遮罩蚀刻半导体层。蚀刻半导体层在半导体层内形成与第一栅极相邻的第一和第二凹陷。在第一栅极的侧壁上形成间隙物。间隙物形成接触第一凹陷的底面的三角形间隙物延伸部。使用间隙物作为遮罩在半导体层内形成第二凹陷。在第二凹陷内形成源/漏极区。在源/漏极区上形成接触。在一实施例中，半导体层包含SiGe，且SiGe的锗百分比在约10％至50％之间。在一实施例中，蚀刻包含SiGe的半导体层是沿着SiGe的结晶面。在一实施例中，蚀刻半导体层为干式蚀刻工艺。在一实施例中，干式蚀刻工艺是以Cl2、HBr或HF来实施。在一实施例中，形成间隙物由形成多个子间隙物组成。在一实施例中，为了形成接触，蚀刻源/漏极区以形成第三凹陷至一段深度与三角形间隙物延伸部的底面齐平。在一实施例中，在第三凹陷内沉积金属，且对金属退火以形成硅化物。在一实施例中，形成接触使得接触的底面在三角形间隙物延伸部的顶面下，且在三角形间隙物延伸部的底面上。
根据又一个实施例，装置包含具有鳍的基底。自鳍延伸出第一栅极。在鳍内设置与第一栅极相邻的源/漏极区。在源/漏极区上设置接触。沿着第一栅极的侧壁设置间隙物。间隙物形成延伸至低于第一栅极下的鳍的最顶面的三角形间隙物延伸部。在一实施例中，三角形间隙物延伸部具有高度在约1nm与约10nm之间，以及具有宽度在约1nm与约10nm之间。在一实施例中，间隙物由多个子间隙物组成。在一实施例中，硅化物区与三角形间隙物延伸部齐平，且接触直接坐落于硅化物区上。在一实施例中，鳍包含SiGe，且具有约10％至约50％的锗百分比。
以上概述数个实施例或范例的特征，以便在本发明所属技术领域中技术人员可以更理解本发明实施例的观点。在本发明所属技术领域中技术人员应该理解，他们能以本发明实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例或范例相同的目的及/或优势。在本发明所属技术领域中技术人员也应该理解到，此类等效的结构并无悖离本发明实施例的构思与范围，且他们能在不违背本发明实施例的构思和范围之下，做各式各样的改变、取代和替换。

Claims (1)

1.一种半导体装置的制造方法，包括：
在一半导体层上形成一第一虚设栅极和一第二虚设栅极；
使用该第一虚设栅极和该第二虚设栅极作为一第一遮罩蚀刻该半导体层，其中蚀刻该半导体层在该半导体层内形成设置在该第一虚设栅极与该第二虚设栅极之间的一第一凹陷；
在该第一虚设栅极的侧壁上形成一第一间隙物，且在该第二虚设栅极的侧壁上形成一第二间隙物，其中该第一间隙物和该第二间隙物形成接触该第一凹陷的一底面的三角形间隙物延伸部；
在形成该第一间隙物和该第二间隙物之后，在该半导体层内形成设置在该第一虚设栅极与该第二虚设栅极之间的一第二凹陷；以及
在该第二凹陷内形成一源/漏极区。
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