TW201631693A - 自對準製程 - Google Patents

自對準製程 Download PDF

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TW201631693A
TW201631693A TW105100582A TW105100582A TW201631693A TW 201631693 A TW201631693 A TW 201631693A TW 105100582 A TW105100582 A TW 105100582A TW 105100582 A TW105100582 A TW 105100582A TW 201631693 A TW201631693 A TW 201631693A
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plasma
substrate
patterned substrate
gap
etching
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TW105100582A
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帕迪特瑪達爾Ｂ
王安川
英格爾尼汀Ｋ
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應用材料股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32412—Plasma immersion ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357—Generation remote from the workpiece, e.g. down-stream
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
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Abstract

在圖案化基材上形成自對準結構的方法係被描述。此方法可用以形成金屬線或通孔，而不需要一單獨的光微影圖案定義操作的使用。自對準接觸件可被製造，無論間隙壁構件是否存在。此方法包括方向性地離子佈植一間隙填充氧化矽層的一間隙填充部分，以佈植到間隙填充部分內，而不實質上離子佈植間隙填充氧化矽層的剩餘部分(側壁)。然後，使用一含氟前驅物來形成一遠端電漿以蝕刻圖案化基材，以致氧化矽的間隙填充部分相對於其他暴露部分而選擇性地被蝕刻，其中該其他暴露部分係平行於離子佈植方向。沒有離子佈植，由於蝕刻製程期間電漿激發的遠端本質，蝕刻操作將是等向性的。

Description

自對準製程
本發明關於自對準製程。
藉由在基材表面上製造複雜地圖案化材料層的製程使和積體電路的製造可行。在基材上製造圖案化材料是藉由移除暴露材料的受控方法來達成。化學蝕刻用於各種目的，包括將光阻劑中的圖案轉移到下伏層內、薄化層、或薄化已經存在於表面上的特徵結構的橫向尺寸。時常期望具有一蝕刻製程可蝕刻一材料比另一材料更快，其有助於例如圖案轉移製程進行。這樣的蝕刻製程被稱為第一材料相對於第二材料具有選擇性。由於各式各樣的材料、電路與製程，蝕刻製程已經被發展成朝各種材料具有選擇性。
乾式蝕刻製程時常期望用於從半導體基材選擇性地移除材料。此期望係源自可從小型結構緩和地移除材料而具有最小的實體干擾的能力。乾式蝕刻製程亦容許蝕刻速率可藉由移除氣相試劑而急遽地被停止。一些乾式蝕刻製程涉及基材暴露於從一或更多個前驅物形成的遠端電漿副產物。例如，三氟化氮的遠端電漿產生與離子抑制技術的結合致使當電漿流出物流動到基材處理區域內時，矽可從一圖案化基材選擇性地被移除。
需要方法來擴張乾式蝕刻製程的製程彈性。
在圖案化基材上形成自對準結構的方法係被描述。此方法可用以形成金屬線或通孔，而不需要一單獨的光微影圖案定義操作的使用。自對準接觸件可被製造在受限制的維度中，其受到一間隙壁構件限制，但亦沿著在不受到多個間隙壁構件限制的維度中。此方法包括直接地離子佈植一間隙填充氧化矽層的一間隙填充部分，以向下佈植到間隙填充部分內，而不實質上離子佈植間隙填充氧化矽層的剩餘部分(側壁)。然後，使用一含氟前驅物來形成一遠端電漿以蝕刻圖案化基材，以致間隙填充氧化矽層的暴露水平部分(間隙填充部分)相對於對準離子佈植方向的暴露部分而選擇性地被蝕刻。沒有離子佈植，由於蝕刻製程期間電漿激發的遠端本質，蝕刻操作將是等向性的。
本發明的實施例包括蝕刻一圖案化基材的方法。該方法包括離子佈植該圖案化基材。離子佈植該圖案化基材的步驟包括離子佈植該圖案化基材上的一氧化矽層中的一間隙的一暴露底部。該暴露底部與該間隙的一暴露側壁部分各包括氧化矽。該方法更包括使一含氟前驅物流動到一遠端電漿區域內，該遠端電漿區域藉由一噴頭而流體地耦接到一基材處理區域，同時在該遠端電漿區域中形成一遠端電漿以產生電漿流出物。該方法更包括使一含氫與氧前驅物流動到該基材處理區域內， 而不使該含氫與氧前驅物先通過該遠端電漿區域。該含氫與氧前驅物包含一O-H鍵。該方法更包括結合該些電漿流出物與該含氫與氧前驅物在該基材處理區域中，以蝕刻該暴露底部比蝕刻該暴露側壁部分更快速。
離子佈植該圖案化基材可包括離子佈植該氧化矽層中的該間隙的該暴露底部到介於該暴露底表面與一下伏矽部分之間的一界面。離子佈植該圖案化基材可包括以硼、氟、水、氦、磷、或氫的一或更多者來離子佈植該圖案化基材。蝕刻該暴露底部可比蝕刻該暴露側壁部分更快速至少15：1的比例。該暴露底部可具有比該暴露側壁部分更高的摻質濃度。
本發明的實施例包括蝕刻一圖案化基材的方法。該方法包括離子佈植該圖案化基材。離子佈植該圖案化基材的步驟包括離子佈植該圖案化基材上的一間隙的底部處的間隙填充氧化矽。該方法更包括非等向性地蝕刻該圖案化基材，以致間隙填充氧化矽係蝕刻比側壁氧化矽更快速。
離子佈植該圖案化基材可包括沿著一方向加速離子到該圖案化基材上的該間隙內。非等向性地蝕刻該圖案化基材的操作可以是一乾式蝕刻製程。離子佈植該圖案化基材可以是一局部電漿製程。非等向性地蝕刻該圖案化基材係移除所有的間隙填充氧化矽以暴露下伏矽。
本發明的實施例包括蝕刻一圖案化基材的方法。該方法包括離子佈植該圖案化基材。離子佈植該圖案化基材的步驟包括離子佈植該圖案化基材上的一氧化矽層中的一間隙的一暴露底部。該暴露底部與該間隙的一暴露側壁部分各包含氧化矽。該方法更包括放置該圖案化基材在一基材製程腔室的一基材處理區域中。該方法更包括使一含氟前驅物流動到一遠端電漿區域內，該遠端電漿區域藉由一噴頭而流體地耦接到該基材處理區域，同時在該遠端電漿區域中形成一遠端電漿以產生電漿流出物。該方法更包括使水蒸氣流動到該基材處理區域內，而不使該水蒸氣先通過該遠端電漿區域。該方法更包括結合該些電漿流出物與該水蒸氣在該基材處理區域中。該方法更包括蝕刻該圖案化基材，其中蝕刻該圖案化基材的操作係蝕刻該暴露底部比蝕刻該暴露側壁部分更快速。
使水蒸氣流動到該基材處理區域內可更包括使一醇流動到該基材處理區域內，亦不先使該醇通過該遠端電漿區域。蝕刻該圖案化基材的操作期間，該基材處理區域中的一電子溫度可以小於0.5eV。該水蒸氣可以或不可以被形成在該基材處理區域外面的任何遠端電漿所激發。該含氟前驅物包含選自由以下群組所構成的一前驅物：原子氟、二原子氟、三氟化氮、四氟化碳、 氟化氫、與二氟化氙。該含氟前驅物與該些電漿流出物基本上缺乏氫。
額外的實施例與特徵部分地被公開在以下說明，且對於熟習此技藝之人士在閱讀說明書後將變得清楚或可藉由實現實施例來瞭解。可藉由本說明書所述的設施、組合、方法來瞭解和獲得實施例的特徵與優點。
101‧‧‧自對準接觸件製造過程
110~150‧‧‧操作
201‧‧‧元件
210‧‧‧矽
220‧‧‧閘極堆疊
230‧‧‧間隙壁氮化矽
240-1‧‧‧間隙填充氧化矽層
240-2‧‧‧間隙填充氧化矽層
240-3‧‧‧間隙填充氧化矽層
250‧‧‧罩幕
1001‧‧‧基材製程腔室
1002‧‧‧遠端電漿系統(RPS)
1003‧‧‧冷卻板
1005‧‧‧氣體輸入組件
1010‧‧‧流體供應系統
1014‧‧‧上板
1015‧‧‧腔室電漿區域
1016‧‧‧下板
1017‧‧‧面板
1018‧‧‧容積
1019‧‧‧第一流體通道
1020‧‧‧絕緣環
1021‧‧‧第二流體通道
1023‧‧‧離子抑制件
1025‧‧‧噴頭
1027‧‧‧孔洞
1031‧‧‧穿孔
1033‧‧‧基材處理區域
1055‧‧‧基材
1058‧‧‧氣體供應區域
1065‧‧‧基材支撐件(載座)
1101‧‧‧處理系統
1102‧‧‧前開式整合艙
1104‧‧‧機械手臂
1106‧‧‧低壓固持區域
1108a~f‧‧‧基材製程腔室
1110‧‧‧第二機械手臂
可藉由參照說明書與圖式的剩餘部分來知悉實施例的本質和優點的進一步瞭解。
第1圖是根據實施例之一自對準接觸件製造過程的流程圖。
第2A、2B、2C和2D圖是根據實施例之在自對準接觸件製造過程期間各個階段的元件的剖視圖。
第3A圖顯示根據實施例之基材處理腔室的示意剖視圖。
第3B圖顯示根據實施例之基材處理腔室的一部分的示意剖視圖。
第3C圖顯示根據實施例之一噴頭的仰視圖。
第4圖顯示根據實施例之一示範性基材處理系統的俯視圖。
在隨附圖式中，類似的部件與/或特徵結構可具有相同的元件符號。又，相同類型的各種部件可藉由在元件符號後面的破折號與第二符號(其區分類似的部 件)來區分。若說明書中僅使用第一元件符號，說明係應用到具有相同第一元件符號的任何一類似部件，而不論第二元件符號為何。
在圖案化基材上形成自對準結構的方法係被描述。此方法可用以形成金屬線或通孔，而不需要一單獨的光微影圖案定義操作的使用。自對準接觸件可被製造，而具有非水平的滲透的維度，其受到一間隙壁構件限制，但亦在不受到多個間隙壁構件限制的區域中。此方法包括直接地離子佈植一間隙填充氧化矽層的一間隙填充部分，以向下佈植到間隙填充部分內，而不實質上離子佈植間隙填充氧化矽層的剩餘部分(側壁)。然後，使用一含氟前驅物來形成一遠端電漿以蝕刻圖案化基材，以致間隙填充氧化矽層的暴露水平部分(間隙填充部分)相對於暴露表面對準離子佈植方向的暴露部分而選擇性地被蝕刻。沒有離子佈植，由於蝕刻製程期間電漿激發的遠端本質，蝕刻操作將是等向性的。
本發明的實施例關於以選擇性方式從一圖案化基材移除間隙填充氧化矽層的一間隙填充部分，以促進導電特徵結構的自對準。導電特徵結構的自對準係移除光微影操作，其有助於控制成本，並且在一些實施例中，減少電晶體之間的空間。減少電晶體之間的空間將延伸摩爾定律(Moore’s law)關於縮小速度的壽命。在短長度規模的自對準製程是藉由發展適當的蝕刻製程來 達到，其中該蝕刻製程具有高選擇性的適當材料系統。圖案化基材被離子佈植，以在向下方向摻雜間隙填充氧化矽層的間隙填充部分，以致一遠端電漿蝕刻可接著被使用來非等向性地蝕刻間隙填充氧化矽層的間隙填充部分。非等向性蝕刻係從間隙的開口垂質地移除間隙填充部分(或更大致上，非水平(other-than-horizontal))。在離子佈植之前，間隙填充氧化矽層的間隙填充部分在此可稱為未佈植氧化矽。在離子佈植之後，間隙填充氧化矽層的間隙填充部分將稱為佈植氧化矽。在此將使用「頂部」、「之上」、「向上」來描述垂質地距離基材平面且在垂直方向進一步遠離基材的質量中心的部分/方向。「垂直」將被用以描述朝向「頂部」對準「向上」方向的物件。其他類似的用語可被使用，其意義現在將清楚。
為了更加瞭解與知悉本發明的實施例，現在參照第1圖，第1圖是一示範性自對準接觸件製造過程101的流程圖。在整個自對準接觸件製造過程101的階段的元件201的剖視圖被顯示在第2A-2D圖。元件201包括矽210，矽210可以是單結晶或多結晶矽(為了簡化典型地稱為「多晶矽」)。根據實施例，矽210可包括被生長在一基底基材上(特別是向上到溝槽內)的磊晶單晶矽或多晶矽。在實施例中，元件201被形成在一圖案化基材上且更包括閘極堆疊220與顯示在任一側或圍繞閘極堆疊220的間隙壁氮化矽230。
間隙壁氮化矽230形成鄰近閘極堆疊220的一間隙，其中閘極堆疊220含有矽210的一「間隙填充」部分(磊晶生長部分)與間隙填充氧化矽層240-1的間隙填充部分。然而，間隙填充氧化矽層240-1的間隙填充部分的兩側沿著正交維度(進入與離開此頁面)受到間隙壁氮化矽230所限制，沒有間隙壁氮化矽存在來限制蝕刻操作。沿著正交維度的間隙壁氮化矽的缺乏使得在此所述的蝕刻操作的方向性是有益的。間隙填充部分(及接著的導電接觸件)可在正交維度相較於第2A圖的平面中所示的寬度更長。若間隙壁氮化矽圍繞接觸件孔洞/間隙填充部分240-1的間隙填充氧化矽層，一簡單的等向性蝕刻將是足夠的。在實施例中，間隙壁氮化矽230的厚度可小於10nm、小於9nm、或小於8nm，而使得在此所述的蝕刻操作的高選擇性是有益的。在示範性自對準接觸件製造過程101中，間隙將後來被改變，以對矽210具有導電接觸。若間隙壁氮化矽230的蝕刻速率是相當大的，導電接觸件與閘極堆疊220之間的電氣短路會發生。製造過程101的一優點是避免形成這樣的電氣短路。結合方向性蝕刻與高選擇性蝕刻的另一優點是容許在基材的平面的二維度(左-右與進入第2A圖的頁面)中電路構件被放置在一起更近，以致使半導體工業中進一步的元件密度比例化。
第2A圖顯示元件201在一包括罩幕250的起始階段，並且一反應性離子蝕刻製程被執行以移除正 好在氧化矽層240-1的間隙填充部分之上的間隙填充氧化矽層240-1的上部，以形成間隙填充氧化矽層240-2。移除間隙填充氧化矽層240-1的該部分可暴露間隙填充氧化矽層240-1的間隙填充部分，但亦可暴露間隙壁氮化矽230，如第2B圖所示。
接著，圖案化基材被放置在一離子佈植腔室中，該離子佈植腔室可以是一束線佈植腔室或一偏壓電漿佈植腔室。一束線佈植腔室被用在示範性自對準接觸件製造過程101。在操作110，硼從束線從上方被加速朝向圖案化基材。硼被佈植到間隙填充氧化矽層240-2的至少上部及間隙壁氮化矽230內。根據實施例，佈植垂質地發生到圖案化基材的構件內，無論是使用一束線佈植腔室或一偏壓電漿佈植腔室而以硼來佈植圖案化基材。在實施例中，這可確保選擇性具有後面在示範性自對準接觸件製造過程101中描述之希望的性質。大致上來說，圖案化基材能以硼、氟、水、氦、磷、或氫的一或更多者來佈植。
在操作120中，圖案化基材接著被放置在一基材處理區域中。接著，三氟化氮流被引進到一獨立的電漿區域中(非等向性蝕刻製程101的操作130)，其中三氟化氮被激發成一在獨立電漿區域中觸發的遠端電漿。該獨立電漿區域在此可稱為一遠端電漿區域，並且可位在和製程腔室不同的模組內，或位在藉由一可滲透阻障物和基材處理區域分離的製程腔室內的一艙內。大 致上，一含氟前驅物可被流動到遠端電漿區域內，並且含氟前驅物包含選自由以下群組所構成的至少一前驅物：原子氟、二原子氟、三氟化硼、三氟化氯、三氟化氮、氟化氫、氟化碳氫化合物、六氟化硫、與二氟化氙。
持續進行示範性自對準接觸件製造過程101的實施例，被形成在遠端電漿區域中的電漿流出物接著被流動到基材處理區域內(操作140)且與水蒸氣(H2O)結合，其中水蒸氣(H2O)在實施例中可同時地被流動到基材處理區域內。電漿流出物可透過噴頭中的穿孔進入基材處理區域，其中噴頭將遠端電漿區域和基材處理區域分離且保持水蒸氣不會回流到遠端電漿區域。水蒸氣沒有被過遠端電漿區域且因此僅藉由與電漿流出物的交互反應而被激發。根據實施例，在水蒸氣進入基材處理區域之前，水蒸氣沒有被通過任何電漿。
在操作150，水蒸氣與電漿流出物結合以選擇性地且以垂直方向蝕刻圖案化基材。大致上來說，蝕刻可進行在對準離子佈植方向的任何其他非水平方向。蝕刻移除(現在摻雜硼)間隙填充氧化矽層240-2的間隙填充部分以形成間隙填充氧化矽層240-3且進行於向下方向。蝕刻可被描述為自限制(self-limiting)，這是因為在間隙填充氧化矽的摻雜部分被消耗之後，蝕刻進行如此顯著地減緩。示範性自對準接觸件製造過程101因此可稱為一非等向性蝕刻製程，這是因為在蝕刻間隙填充氧化矽時，蝕刻101保留一些氧化矽(側壁)。根據 實施例，間隙填充氧化矽層240-2的間隙填充部分被佈植有硼且蝕刻比側壁更快速得多，其中側壁沒有被佈植或被佈植太少程度。第2C圖顯示在操作150之後元件201的輪廓。反應性化學物種從基材處理區域被移除，並且接著基材從基材處理區域被移除。遠端電漿區域在示範性自對準接觸件製造過程101的操作130-150期間可缺乏氫。
間隙填充氧化矽層240-1的間隙填充部分可在兩側上受到間隙壁氮化矽230所限制，並且此限制可以是垂直的或沿著非水平的方向。離子佈植方向可經選擇以對準非水平方向，而確保適當的間隙填充部分的摻雜。沿著正交維度(進入與離開此頁面)，沒有間隙壁氮化矽存在，並且此對準可以或不可以是垂直的，但當然在正交維度亦是非水平。在此所述的蝕刻操作的方向性可嚴格地受到在佈植操作110電漿佈植腔室的使用的控制。正交維度的關鍵尺寸(critical dimension)可從間隙填充氧化矽層240-2的離子佈植間隙填充部分的尺寸增加小於2nm、小於1.5nm、或小於1nm。緊密容忍度的優點是最終積體電路上的元件(例如電晶體)的堆疊密度的增加。
在實施例中，間隙填充氧化矽層240-3可不具有間隙填充部分(參見第2C圖)，但為了連續性與簡易性將被稱為一「間隙填充」氧化矽層。可藉由確保在操作110期間摻質(例如在此實例中是硼)被一路佈植通過 間隙填充部分來促進間隙填充氧化矽層240-2的間隙填充部分的完全移除。一些元件201可受益自避免過渡的矽210的硼摻雜，或至少藉由控制硼摻質穿透多少與多深。可藉由選擇適當的摻質的加速電壓以及間隙填充氧化矽層240-2的間隙填充部分的深度來調整離子佈植深度。無論是否一束線佈植腔室或一電漿佈植腔室被使用，可達到這些調整。接著，一導電層(例如鎢)被沉積在間隙中且被研磨以形成第2D圖顯示的元件201。最終導電非水平(例如垂直)連接可稱為接觸件、插塞(例如在此實例中是鎢插塞)且有時候被稱為通孔。一金屬矽化物(例如矽化鎳)層、鈦與/或氮化鈦可在沉積用於鎢的鎢插塞之前被形成。插塞可被形成在一電晶體的一源極與/或汲極部分上方。
根據實施例，摻質濃度(例如在此實例中是硼)可具有大於1%、大於2%、大於3%、或大於4%重量百分比的間隙填充氧化矽層240-2的間隙填充部分。間隙填充部分可或者稱為間隙的暴露底部。在實施例中，摻質濃度可具有每立方公分大於2×1020、大於5×1020、大於1×1021、或大於2×1021原子的絕對濃度。根據實施例，在離子佈植之前，間隙的暴露底部可稱為未佈植氧化矽且可具有低於0.5%、低於0.1%、低於0.02%、或低於0.001%(重量百分比)的摻質濃度。在實施例中，佈植之前的暴露底部部分(與暴露側壁部分)可具有每立方公分小於1×1020、小於2×1019、小於 5×1018、或小於1×1018原子的絕對摻質濃度。根據實施例，佈植之後的暴露側壁部分可具有低於1%、低於0.5%、低於0.1%、或低於0.02%(重量百分比)的摻質濃度。在實施例中，佈植之後的暴露側壁部分可具有每立方公分小於2×1020、小於1×1020、小於2×1019、或小於5×1018原子的絕對摻質濃度。根據實施例，間隙填充氧化矽層240-2的間隙填充部分的厚度可介於100Å與2000Å之間、介於200Å與1500Å之間、或介於300Å與1000Å之間。離子佈植的深度可位在間隙填充氧化矽層240-2的間隙填充部分的厚度的30%之內、20%之內、或10%之內，以確保適當的間隙填充部分的移除且限制任何下伏矽210的佈植。
示範性自對準接觸件製造過程101使用傳統的束線佈植腔室用於離子佈植操作110。更甚者，電漿佈植腔室被使用，而形成設以將離子朝向圖案化基材偏壓的局部電漿。在實施例中，無論使用何種腔室，一摻質前驅物可被流動到束線佈植腔室或電漿佈植腔室內，以用硼、氟、水、氦、磷或氫的一或更多者來摻雜前驅物，並且摻質前驅物可包含硼、氟、水、氦、磷或氫的一或更多者。當一電漿佈植腔室被使用時，操作110包括在偏壓電漿佈植腔室時，施加能量到摻質源(例如含硼前驅物)以產生用以佈植該圖案化基材的離子(操作110)。可使用已知技術(例如射頻激發、電容式耦合功率、感應式耦合功率等)來產生電漿。能量可被施加成一 局部電漿功率到電容式耦合電漿單元。根據實施例，局部電漿功率可介於約10瓦與約500瓦之間、介於約20瓦與約400瓦之間、介於約30瓦與約300瓦之間、或介於約50瓦與約200瓦之間。電漿功率與操作壓力可用以調整撞擊離子的電流與動能，並且可用以調整間隙填充氧化矽層240-2的間隙填充部分的尺寸。
一DC加速電壓亦可被施加，以致被形成在局部電漿中的正含硼離子進一步地被加速在圖案化基材的方向。例如，可藉由施加一DC偏壓功率來形成局部電漿，以致局部電漿功率包含AC部分與DC部分。在實施例中，DC偏壓功率係供應可大於400伏特、大於500伏特、大於600伏特、或大於700伏特的DC加速電壓。DC電壓可小於2000伏特、小於1500伏特、小於1300伏特、或小於1100伏特，以保存暴露柔弱特徵結構的完整性。根據實施例，偏壓電漿佈植腔室中的壓力可介於約0.5毫托與約50毫托之間、介於約2毫托與約200毫托之間、或介於約5毫托與約100毫托之間。
示範性自對準接觸件製造過程101亦包括在遠端電漿區域時施加能量到含氟前驅物以產生電漿流出物(操作130)。如同此技術領域中具有通常知識者所瞭解，電漿可包括多個帶電與中性物種，包括自由基和離子。可使用已知技術(例如射頻激發、電容式耦合功率、感應式耦合功率等)來產生電漿。在此實例中，使用一電容式耦合電漿單元來施加能量。在實施例中，遠端電漿 源可介於約10瓦與約5000瓦之間、介於約100瓦與約3000瓦之間、介於約250瓦與約2000瓦之間、或介於約500瓦與約1500瓦之間。根據實施例，遠端電漿區域中的壓力與/或基材處理區域的壓力可介於0.01托與50托之間或介於0.1托與5托之間。在實施例中，所施加用於在此所述的局部或遠端電漿的RF頻率可以是小於200kHz的低RF頻率、介於10MHz與15MHz之間的高RF頻率、或大於1GHz的微波頻率。
根據實施例，在此展現的方法係呈現摻雜間隙填充氧化矽材料相對於側壁氧化矽材料的高蝕刻選擇性。根據實施例，摻雜間隙填充氧化矽材料相對於側壁氧化矽材料的蝕刻選擇性可大於15：1、大於30：1、或大於40：1。根據實施例，摻雜間隙填充氧化矽材料相對於暴露氮化矽材料的蝕刻選擇性可大於25：1、大於40：1、或大於50：1。根據實施例，摻雜間隙填充氧化矽材料相對於暴露矽材料的蝕刻選擇性(一旦間隙填充氧化矽已經被移除)可大於50：1、大於75：1、或大於100：1。
到電漿佈植腔室的局部電漿內的摻質前驅物的流動以及到蝕刻腔室的遠端電漿內的含氟前驅物的流動各可更包括一或更多個相當惰性氣體，諸如He、N2、Ar。惰性氣體可用以改善電漿穩定性、電漿觸發能力、與/或製程均勻性。氬作為添加劑以促進穩定電漿的形成是有幫助的。當氦被包括時，製程均勻性大致上被增加。 這些添加劑存在於本說明書的實施例中。氣體的流速與比例可用以控制蝕刻速率與摻質特性與蝕刻選擇性。
在此展現的實例涉及從上方觀看是低深寬比間隙的接觸件的形成。大致上來說，根據在此所述的實施例所蝕刻之圖案化基材中的間隙可以是通孔或溝槽。通孔可以是低深寬比間隙，並且從坦平的圖案化基材上方觀看可以是例如圓形。溝槽可以是高深寬比間隙而具有長度對寬度比例為至少10：1。根據實施例，通孔的寬度可小於30nm、小於25nm、小於20nm、或小於15nm。在實施例中，通孔的深度可大於10nm、大於15nm、大於20nm、或大於25nm。通孔的深度包括間隙壁(例如氮化矽)之間的部分。在實施例中，溝槽的寬度可小於40nm、小於35nm、小於20nm、或小於15nm。根據實施例，溝槽的深度可大於15nm、大於20nm、大於25nm、或大於30nm。
在實施例中，一離子抑制件(其可以是噴頭)可用以提供用於氣相蝕刻的自由基與/或中性物種。離子抑制件亦可稱為離子抑制構件。在實施例中，例如，離子抑制件用以過濾從遠端電漿區域到基材處理區域途中的蝕刻電漿流出物。離子抑制件可用以提供具有比離子更高濃度的自由基之一反應性氣體。電漿流出物係通過設置在遠端電漿區域與基材處理區域之間的離子抑制件。離子抑制件的作用在於戲劇性地減少或實質上去除從電漿產生區域行進到基材的離子物種。在此所述的離 子抑制件僅是一種在此所述的氣相蝕刻製程期間在基材處理區域中達到低電子溫度的方式。
在實施例中，一電子束以平行於基材的平面被通過基材處理區域，以降低電漿流出物的電子溫度。若一電子束以此方式被施加，可使用一更簡單的噴頭。在實施例中，電子束可以設置在基材上方的層疊片被通過。在實施例中，電子束提供中和負電荷的來源，並且提供用以減少正電荷離子朝向基材流動且增加蝕刻選擇性的更積極方式。控制電子束的運作之電漿流出物的流動與各種參數可被調整以降低基材處理區域中所測量的電子溫度。
於遠端電漿中的電漿的激發期間，可使用蘭摩爾探針(Langmuir probe)在基材處理區域中測量溫度。在實施例中，電子溫度可小於0.5eV、小於0.45eV、小於0.4eV、或小於0.35eV。這些電子溫度的極低值是藉由電子束、噴頭、與/或離子抑制件的存在來達到。不帶電的中性與自由基物種可通過電子束與/或離子抑制件中的開口而在基材處反應。相較於包括濺鍍與轟擊的傳統電漿蝕刻製程，這樣使用自由基與其他中性物種的製程可減少電漿損壞。相對於傳統濕式蝕刻製程(其中液體的表面張力可造成小特徵結構的彎曲與剝離)，本發明的實施例也是有利的。
在此所述的蝕刻製程期間，基材處理區域在此可被描述成「無電漿」。「無電漿」不必然意謂此區 域沒有電漿。被產生在電漿區域內的離子化物種與自由電子可以非常小濃度行進通過分隔件(噴頭)中的細孔(孔縫)。腔室電漿區域中的電漿的邊界能透過噴頭中的孔縫以小程度侵佔基材處理區域。又，一低強度電漿可被產生在基材處理區域中，而不去除在此所述的蝕刻製程的期望特徵結構。在激發電漿流出物的產生期間，具有比腔室電漿區域更低得多強度離子密度的電漿的所有原因係沒有悖離在此所使用的「無電漿」的範疇。
第3A圖顯示一示範性基材製程腔室1001的剖視圖，該示範性基材製程腔室1001在製程腔室內具有一分隔的電漿產生區域。在膜蝕刻期間，一製程氣體可透過一氣體輸入組件1005被流動到腔室電漿區域1015內。一遠端電漿系統(RPS)1002係可選地被包括在此系統中，且可處理一第一氣體，該第一氣體接著行進通過氣體輸入組件1005。在進入腔室電漿區域1015之前，製程氣體可在RPS 1002內被激發。因此，在實施例中，以上討論的含氟前驅物例如可通過RPS 1002或繞過RPS單元。
根據實施例，一冷卻板1003、面板1017、離子抑制件1023、噴頭1025、與一基材支撐件1065(亦為所知的載座)(其具有設置在其上的一基材1055)被顯示出，並且可各被包括。載座1065可具有一熱交換通道，一熱交換流體係流動通過熱交換通道以控制基材的溫度。此組態可容許基材1055溫度被冷卻或被加熱，以 維持相當低的溫度，諸如介於-20℃與200℃之間。載座1065亦可使用一嵌設加熱器構件而電阻式被加熱到相當高的溫度，諸如介於100℃與1100℃之間。
示範性組態可包括使氣體輸入組件1005開放到氣體供應區域1058內，氣體供應區域1058藉由面板1017與腔室電漿區域1015分隔，以致氣體/物種流動通過面板1017中的孔洞到腔室電漿區域1015內。結構與操作的特徵可經選擇以避免電漿從腔室電漿區域1015返回到供應區域1058、氣體輸入組件1005、與流體供應系統1010內之顯著的回流。結構特徵可包括面板1017中孔縫的尺寸與剖視幾何型態的選擇，以抑制回流電漿。操作特徵可包括維持氣體供應區域1058與腔室電漿區域1015之間的壓力差，而維持電漿通過噴頭1025的單方向流動。面板1017、或腔室的導電頂部、與噴頭1025被顯示具有介於該些特徵之間的一絕緣環1020，絕緣環1020容許AC電位相對於噴頭1025與/或離子抑制件1023被施加到面板1017。絕緣環1020可被定位在面板1017與噴頭1025與/或離子抑制件1023之間，使得一電容式耦合電漿(capacitively coupled plasma,CCP)被形成在腔室電漿區域中。
離子抑制件1023中的複數個孔洞可設以控制活化氣體(即離子、自由基、與/或中性物種)經由離子抑制件1023的通過。例如，孔洞的深寬比、或孔洞直徑對長度、與/或孔洞的幾何型態可受到控制，以致通過離 子抑制件1023的活化氣體中的離子化帶電物種的流量被減少。離子抑制件1023中的孔洞可包括一面對腔室電漿區域1015的錐狀部分以及一面對噴頭1025的圓柱形部分。圓柱形部分的形狀與尺寸可控制通過到噴頭1025的離子物種的流量。一可調整電偏壓亦可被施加到離子抑制件1023，作為控制通過抑制件的離子物種的流量的額外方式。離子抑制構件1023的作用可在於減少或去除從電漿產生區域行進到基材的離子化帶電物種的量。不帶電中性與自由基物種仍可通過離子抑制件中的開口，以與基材反應。
電漿功率可具有各種頻率或多個頻率的組合。在示範性處理系統中，可藉由RF功率提供電漿，而相對於離子抑制件1023與/或噴頭1025被輸送到面板1017。在實施例中，RF功率可介於約10瓦與約5000瓦之間、介於約100瓦與約2000瓦之間、介於約200瓦與約1500瓦之間、或介於約200瓦與約1000瓦之間。在示範性處理系統中所施加的RF頻率可以是的小於200kHz的低RF頻率、介於10MHz與15MHz之間的高RF頻率、或大於1GHz的微波頻率。電漿功率可以是電容式耦合(CCP)或感應式耦合(ICP)到遠端電漿區域內。
一前驅物(例如一含氟前驅物)可藉由在此所述的噴頭的實施例被流動到基材處理區域1033內。從腔室電漿區域1015中的製程氣體所衍生的激發物種可行 進通過離子抑制件1023中的孔縫、與/或噴頭1025，並且與從噴頭的一分離部分流動到基材處理區域1033內的一增補未激發前驅物(例如水蒸氣)反應。在遠端電漿蝕刻製程期間，幾乎沒有或沒有電漿可存在於基材處理區域1033中。前驅物的激發衍生物可在基材上方的區域中與/或在基材上結合，以蝕刻結構或從基材移除物種。在實施例中，增補未激發前驅物可以是一醇或水蒸氣(H2O)，以改善氧化矽的蝕刻選擇性。根據實施例，增補未激發前驅物可以是一含氫與氧前驅物且可含有O-H鍵。在實施例中，增補未激發前驅物可以是水蒸氣與醇的組合，這有助於保持極柔弱特徵結構的結構而同時保持高摻雜氧化矽蝕刻速率。
製程氣體可在腔室電漿區域1015中被激發，並且可在激發狀態被通過噴頭1025到基材處理區域1033。當一電漿可被產生在基材處理區域1033中時，一電漿或者可不被產生在處理區域中。在一實例中，僅製程氣體的激發或前驅物可來自激發腔室電漿區域1015中的製程氣體，以在基材處理區域1033中彼此反應。如前所討論，這可保護被圖案化在基材1055上的結構。
第3B圖顯示影響製程氣體散佈穿透面板1017的特徵結構的細節視圖。用在製程腔室區塊1001的氣體散佈組件(諸如噴頭1025)可稱為雙通道噴頭(dual channel showerhead,DCSH)，並且額外詳 細地被顯示於在此第3A圖及第3C圖中所描述的實施例中。在被輸送到處理區域內之前，雙通道噴頭可提供蝕刻製程，該蝕刻製程容許處理區域1033外面的蝕刻劑的分離，以提供受限的和腔室部件與彼此的交互作用。
噴頭1025可包含一上板1014與一下板1016。該些板可彼此耦接以界定該些板之間的一容積1018。該些板的耦接可因此提供通過上與下板的第一流體通道1019，及通過下板1016的第二流體通道1021。所形成的通道可設以提供流體從容積1018單獨經由第二流體通道1021通過下板1016的連通，並且第一流體通道1019可和容積1018流體地隔離而介於該些板與該些第二流體通道1021之間。容積1018可流體地連通到氣體散佈組件1025的一側。儘管第3A-3C圖的示範性系統包括一雙通道噴頭，可瞭解的是可利用替代性散佈組件，其中該替代性散佈組件維持第一與第二前驅物在進入基材處理區域1033之前流體地隔離。例如，可利用一經穿孔的板與在該板下方的管，儘管其他組態可操作而具有減少的效率或沒有提供如所述雙通道噴頭的均勻處理。
在所顯示的實施例中，噴頭1025可經由第一流體通道1019散佈製程氣體，其中該些製程氣體含有在腔室電漿區域1015中被一電漿激發的電漿流出物。在實施例中，被引進到RPS 1002與/或腔室電漿區域1015的製程氣體可含有氟，例如NF3。製程氣體亦可包括一 承載氣體，諸如氦、氬、氮(N2)等。電漿流出物可包括製程氣體的離子化或中性衍生物，並且在此亦可稱為一自由基-氟前驅物(其係參照被引進到基材處理區域1033內的製程氣體的原子構成物)。
第3C圖是在實施例中併同製程腔室使用的一噴頭1025的仰視圖。噴頭1025對應於第3A圖中的噴頭。穿孔1031(其顯示第一流體通道1019的視圖)可具有複數個形狀與組態，以控制且影響通過噴頭1025的前驅物的流動。小孔洞1027(其顯示第二流體通道1021的視圖)可實質上均勻地被散佈在噴頭的表面上，甚至是在該些穿孔1031之間，這可有助於當前驅物離開時提供比其他配置更均勻的前驅物的混合。
腔室電漿區域1015或RPS中的一區域可稱為一遠端電漿區域。在實施例中，自由基-氟前驅物被產生在遠端電漿區域中且行進到基材處理區域內而與一增補未激發前驅物結合。在實施例中，該增補未激發前驅物僅被自由基-氟及電漿流出物的剩餘者所激發。在實施例中，電漿功率可實質上僅被施加到遠端電漿區域，以確保自由基-氟提供主導的激發。
乾式蝕刻系統的實施例可被併入到更大的用以生產積體電路晶片的製造系統。第4圖顯示在實施例中沉積、蝕刻、烘烤與硬化腔室之這樣的處理系統(主框架)1101。在此圖中，一對前開式整合艙(裝載閉鎖腔室1102)供應各種尺寸的基材，該些基材被機械手臂1104 接收且在被放置到基材製程腔室1108a-f的一者之前被放置到一低壓固持區域1106中。一第二機械手臂1110可用以從固持區域1106傳送基材晶圓到基材製程腔室1108a-f並返回。各個基材製程腔室1108a-f可被配備以執行多個基材處理操作，包括在此所述的乾式蝕刻製程，此外還有循環層沉積(cyclical layer deposition,CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、蝕刻、預清潔、去氣、定向、與其他基材製程。
在實施例中，三氟化氮(或另一含氟前驅物)可以介於約1sccm與約400sccm之間、介於約3sccm與約250sccm之間、或介於約5sccm與約100sccm之間的速率被流動到腔室電漿區域1020內。在實施例中，氦可以介於0slm(標準升每分鐘)與3slm之間且氮(N2)可以介於0slm與3slm之間的流速被流動到腔室電漿區域1020內。根據實施例，一增額未激發前驅物(例如水蒸氣)可以介於1sccm與400sccm之間、介於5sccm與100sccm之間、介於10sccm與50sccm之間、或介於15sccm與25sccm之間的速率被流動到基材處理區域1070內。在實施例中，摻質前驅物以介於約5sccm(標準立方公分每分鐘)與400sccm之間、氦以介於約0slm(標準升每分鐘)與3slm之間且氮以介於約0slm與3slm之間的流速被供應到電漿佈植腔室內。此技藝中具有通常知識者可瞭解的是其他氣體與/ 或流動可被使用，取決於多個因素，包括製程腔室組態、基材尺寸、與/或被蝕刻的特徵結構的幾何型態和佈局。在實施例中，於在此所述的離子佈植與蝕刻製程期間，基材的溫度可介於約-20℃與約200℃之間。
由於此兩個不同到基材處理區域內的路徑，噴頭可稱為雙通道噴頭。自由基氟可被流動通過雙區塊噴頭中的穿孔，並且任何未激發前驅物可通過雙通道噴頭中的分離區塊。該些分離區塊可開放到基材處理區域內，而沒有到遠端電漿區域內，如上所述。
到基材處理區域內的結合的電漿流出物的流速可解釋總氣體混合物的0.05%至約20%體積；剩餘者是承載氣體。在實施例中，被流動到遠端電漿區域內的含氟前驅物具有和自由基氟或電漿流出物相同的體積流速。在含氟前驅物的情況中，在含氟氣體進入到遠端電漿區域內之前，沖洗或承載氣體可先被起始進入到遠端電漿區域內，以穩定化遠端電漿區域內的壓力。
在上述說明中，為了解釋目的，已經公開許多細節以提供本發明的各種實施例的瞭解。然而，熟習此技藝之人士可瞭解的是可實施特定實施例而不需要這些細節的一些細節或具有額外的細節。
如在此所使用，「基材」可以是具有或不具有層形成在其上的一支撐基材。圖案化基材可以是一絕緣體或一具有各種摻雜濃度和輪廓的半導體，並且可以是例如用在製造積體電路的類型的半導體基材。圖案化 基材的暴露「矽」主要是矽，但可包括少量濃度的其他元素構成物(諸如氮、氧、氫、或碳)。暴露「矽」可由或基本上可由矽構成。圖案化基材的暴露「氮化矽主要是Si3N4，但可包括少量濃度的其他元素構成物(諸如氧、氫、與碳)。「暴露氮化矽」可基本上由或由矽與氮構成。圖案化基材的暴露「氧化矽」主要是SiO2，但可包括少量濃度的其他元素構成物(諸如氮、氫、碳、與在此所述的其他摻質)。在實施例中，使用在此教示的方法來蝕刻的氧化矽膜基本上由或由矽與氧構成。圖案化基材的暴露「鎢」主要是鎢，但可包括少量濃度的其他元素構成物(諸如氮、矽、氧、氫、與碳)。在實施例中，鎢膜基本上由或由鎢構成。圖案化基材的暴露「矽化鎳」主要是鎳與矽，但可包括少量濃度的其他元素構成物(諸如諸如氮、氧、氫、與碳)。在實施例中，矽化鎳膜基本上由或由鎳與矽構成。矽化鎳與鎢是在此所使用的含金屬膜的實例。其他含金屬膜(諸如「鈦」與「氮化鈦」)的定義遵循類似的定義，並且從這些代表性實例現在將可被瞭解。
用語「前驅物」用以指稱參與一反應以從表面移除材料或沉積材料到表面上的任何製程氣體。「電漿流出物」描述從腔室電漿區域離開且進入基材處理區域的氣體。電漿流出物處於「激發狀態」，其中至少一些氣體分子處於震動地激發、分解、與/或離子化狀態。一「自由基前驅物」用以描述電漿流出物(處於激發狀態 而離開電漿的一氣體)，其參與以反應以從表面移除材料或材料到表面上。「自由基-氟」是含有氟的自由基前驅物，但可含有其他元素構成物。「自由基-氧-氫」可含有氧與氫，但可含有其他元素構成物。詞語「惰性氣體」係指當蝕刻或被併入到一膜時不會形成化學鍵的任何氣體。示範性惰性氣體包括貴族氣體，但可包括其他氣體，只要當(典型地)極少量被捕獲在一膜中沒有化學鍵被形成。
用語「間隙」被用在整篇本文而沒有暗示被蝕刻的幾何型態具有大的水平深寬比。從上方觀看，間隙可呈現為圓形、橢圓形、多邊形、或各種其他形狀。一間隙可具有圍繞一材料島的壕溝的形狀。用語「通孔」用以指稱低深寬比間隙(從上方觀看)，其可以或不可以被填充有金屬以形成一非水平電氣連接件。用語「溝槽」用以指稱一高深寬比間隙(從上方觀看)，而具有至少10：1(長度：寬度)的深寬比。如在此所使用，一共形蝕刻製程係指和一表面上相同形狀之表面上的材料的大致上均勻移除，即被蝕刻的層的表面與預蝕刻表面係大致上平行。此技藝中具有通常知識者可瞭解的是被蝕刻的界面不可能100%共形的，並且用語「大致上」容許可接受的容忍度。
已經揭示一些實施例，熟習此技藝之人士可瞭解的是可使用各種變更、替代性構造、與均等物，而不悖離所揭示的實施例的精神。此外，許多已知的製程 與元素沒有被描述，以為了避免不必要地模糊化本發明。因此，上述說明不應被視為會對本發明的範疇構成限制。
當提供數值範圍時，除非文字中另外清楚指明，應瞭解亦詳細揭露介於該範圍的上下限值之間各個區間值至下限值單位的十分之一。涵蓋了所陳述範圍中的任何陳述數值或區間數值與該陳述範圍中任何其他陳述或區間數值之間的每一個較小範圍。這些較小範圍的上限值與下限值可獨立被包含在該範圍中或被排除在該範圍外，且各範圍(其中極限值的其中一個、極限值的兩者、或沒有極限值被包括在該較小範圍中)亦被涵蓋在本發明內，除非在該陳述範圍中有特別排除之限制。當所陳述之範圍包括極限值的其中一個或兩個時，亦包括排除那些包括的極限值的一個或兩個的範圍。
如在此所使用與如在隨附的申請專利範圍中所使用，單數形式「一」、「一個」與「該」包括複數形式，除非文字中另外清楚指明。因此，舉例而言，「製程」意指包括複數個這樣的製程，而「介電質材料」意指熟習此技藝之人士所知道的一或更多個介電質材料與均等物，及諸如此類者。
又，說明書與隨附的申請專利範圍中使用的「包含」、「含有」與「包括」字眼是意指所陳述之特徵、整合件、部件或步驟的存在，但其並不排除一個或 更多個其他特徵、整合件、部件、步驟、作動或群組的存在或增加。
101‧‧‧自對準接觸件製造過程
110~150‧‧‧操作

Claims (17)

  1. 一種蝕刻一圖案化基材的方法，包括以下步驟：離子佈植該圖案化基材，其中離子佈植該圖案化基材的步驟包括以下步驟：離子佈植該圖案化基材上的一氧化矽層中的一間隙的一暴露底部，其中該暴露底部與該間隙的一暴露側壁部分各包括氧化矽；使一含氟前驅物流動到一遠端電漿區域內，該遠端電漿區域藉由一噴頭而流體地耦接到一基材處理區域，同時在該遠端電漿區域中形成一遠端電漿以產生電漿流出物；使一含氫與氧前驅物流動到該基材處理區域內，而不使該含氫與氧前驅物先通過該遠端電漿區域，其中該含氫與氧前驅物包含一O-H鍵；結合該些電漿流出物與該含氫與氧前驅物在該基材處理區域中，以蝕刻該暴露底部比蝕刻該暴露側壁部分更快速。
  2. 如請求項1所述之方法，其中離子佈植該圖案化基材的操作包括以下步驟：離子佈植該氧化矽層中的該間隙的該暴露底部到介於該暴露底表面與一下伏矽部分之間的一界面。
  3. 如請求項1所述之方法，其中離子佈植該圖案化基材的操作包括以下步驟：以硼、氟、水、氦、磷、或氫的一或更多者來離子佈植該圖案化基材。
  4. 如請求項1所述之方法，其中蝕刻該暴露底部比蝕刻該暴露側壁部分更快速至少15：1的比例。
  5. 如請求項1所述之方法，其中該暴露底部具有比該暴露側壁部分更高的一摻質濃度。
  6. 如請求項1所述之方法，其中離子佈植該圖案化基材的操作是一自限制蝕刻，其在該暴露底部被移除之後停止，儘管該些電漿流出物的持續存在。
  7. 一種蝕刻一圖案化基材的方法，該方法包括以下步驟：離子佈植該圖案化基材，其中離子佈植該圖案化基材的步驟包括沿著一離子佈植方向而離子佈植該圖案化基材上的一間隙的底部處的間隙填充氧化矽；及非等向性地蝕刻該圖案化基材，以致間隙填充氧化矽係蝕刻比側壁氧化矽更快速。
  8. 如請求項7所述之方法，其中離子佈植該圖案化基材的操作包括以下步驟：垂直地加速離子到該圖案化基材上的該間隙內。
  9. 如請求項7所述之方法，其中非等向性地蝕刻該圖案化基材的操作是一乾式蝕刻製程。
  10. 如請求項7所述之方法，其中非等向性地蝕刻該圖案化基材的操作係移除所有的間隙填充氧化矽與暴露下伏矽。
  11. 如請求項7所述之方法，其中離子佈植該圖案化基材的操作是一局部電漿製程。
  12. 一種蝕刻一圖案化基材的方法，該方法包括以下步驟：離子佈植該圖案化基材，其中離子佈植該圖案化基材的步驟包括以下步驟：離子佈植該圖案化基材上的一氧化矽層中的一間隙的一暴露底部，其中該暴露底部與該間隙的一暴露側壁部分各包含氧化矽；放置該圖案化基材在一基材製程腔室的一基材處理區域中；使一含氟前驅物流動到一遠端電漿區域內，該遠端電漿區域藉由一噴頭而流體地耦接到該基材處理區域，同時在該遠端電漿區域中形成一遠端電漿以產生電漿流出物；使水蒸氣流動到該基材處理區域內，而不使該水蒸氣先通過該遠端電漿區域；結合該些電漿流出物與該水蒸氣在該基材處理區域中；及蝕刻該圖案化基材，其中蝕刻該圖案化基材的操作 係蝕刻該暴露底部比蝕刻該暴露側壁部分更快速。
  13. 如請求項12所述之方法，其中使水蒸氣流動到該基材處理區域內的操作更包括以下步驟：使一醇流動到該基材處理區域內，亦不先使該醇通過該遠端電漿區域。
  14. 如請求項12所述之方法，其中蝕刻該圖案化基材的操作期間，該基材處理區域中的一電子溫度小於0.5eV。
  15. 如請求項12所述之方法，其中該水蒸氣沒有被形成在該基材處理區域外面的任何遠端電漿所激發。
  16. 如請求項12所述之方法，其中該含氟前驅物包含選自由以下群組所構成的一前驅物：原子氟、二原子氟、三氟化氮、四氟化碳、氟化氫、與二氟化氙。
  17. 如請求項12所述之方法，其中該含氟前驅物與該些電漿流出物基本上缺乏氫。
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