JP2007537601A - 選択的堆積プロセスを使用したｍｏｓｆｅｔデバイスの作製方法 - Google Patents

選択的堆積プロセスを使用したｍｏｓｆｅｔデバイスの作製方法 Download PDF

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JP2007537601A
JP2007537601A JP2007513252A JP2007513252A JP2007537601A JP 2007537601 A JP2007537601 A JP 2007537601A JP 2007513252 A JP2007513252 A JP 2007513252A JP 2007513252 A JP2007513252 A JP 2007513252A JP 2007537601 A JP2007537601 A JP 2007537601A
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silicon
range
containing layer
seem
flow rate
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JP2007537601A5 (enExample
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アーカダイ ヴィー． サモイロフ，
イーワン キム，
アロル サンチェス，
ニコラス シー． ダリダ，
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Applied Materials Inc
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Applied Materials Inc
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
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    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP2007513252A 2004-05-14 2005-05-10 選択的堆積プロセスを使用したｍｏｓｆｅｔデバイスの作製方法 Pending JP2007537601A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/845,984 US7132338B2 (en) 2003-10-10 2004-05-14 Methods to fabricate MOSFET devices using selective deposition process
PCT/US2005/016160 WO2005112577A2 (en) 2004-05-14 2005-05-10 Methods to fabricate mosfet devices using selective deposition processes

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JP2007537601A true JP2007537601A (ja) 2007-12-20
JP2007537601A5 JP2007537601A5 (enExample) 2008-07-17

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US (2) US7132338B2 (enExample)
EP (1) EP1745503A2 (enExample)
JP (1) JP2007537601A (enExample)
CN (2) CN101593680B (enExample)
TW (1) TWI442448B (enExample)
WO (1) WO2005112577A2 (enExample)

Cited By (9)

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JP2008524858A (ja) * 2004-12-17 2008-07-10 インテル コーポレイション 深く炭素がドーピングされた領域並びに隆起したドナーがドーピングされたソース及びドレインを特徴とする歪みｎＭＯＳトランジスタ
JP2009004604A (ja) * 2007-06-22 2009-01-08 Fujitsu Microelectronics Ltd 半導体装置の製造方法、半導体装置および半導体層の形成方法
JP2009043938A (ja) * 2007-08-09 2009-02-26 Renesas Technology Corp 半導体装置および半導体装置の製造方法
JP2009517867A (ja) * 2005-12-27 2009-04-30 インテル・コーポレーション リセスのあるストレイン領域を有すマルチゲートデバイス
JP2009521801A (ja) * 2005-12-22 2009-06-04 エーエスエム アメリカ インコーポレイテッド ドープされた半導体物質のエピタキシャル堆積
WO2009093328A1 (ja) * 2008-01-25 2009-07-30 Fujitsu Microelectronics Limited 半導体装置及びその製造方法
JP2010177331A (ja) * 2009-01-28 2010-08-12 Hitachi Kokusai Electric Inc 半導体装置の製造方法及び基板処理装置
JP2011061042A (ja) * 2009-09-10 2011-03-24 Fujitsu Semiconductor Ltd 半導体装置
JP2013062524A (ja) * 2012-11-14 2013-04-04 Sony Corp 半導体装置の製造方法

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JP4866534B2 (ja) * 2001-02-12 2012-02-01 エーエスエム アメリカ インコーポレイテッド 半導体膜の改良された堆積方法
US7601225B2 (en) * 2002-06-17 2009-10-13 Asm International N.V. System for controlling the sublimation of reactants
JP5005170B2 (ja) * 2002-07-19 2012-08-22 エーエスエム アメリカ インコーポレイテッド 超高品質シリコン含有化合物層の形成方法
US7294582B2 (en) * 2002-07-19 2007-11-13 Asm International, N.V. Low temperature silicon compound deposition
US7186630B2 (en) * 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
US6921913B2 (en) * 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
JP5288707B2 (ja) * 2003-03-12 2013-09-11 エーエスエム アメリカ インコーポレイテッド シリコンゲルマニウムの、平坦化及び欠陥密度を減少させる方法
US7682947B2 (en) * 2003-03-13 2010-03-23 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7238595B2 (en) * 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
KR20060056331A (ko) * 2003-07-23 2006-05-24 에이에스엠 아메리카, 인코포레이티드 절연체-상-실리콘 구조 및 벌크 기판 상의 ＳｉＧｅ 증착
WO2005013326A2 (en) * 2003-07-30 2005-02-10 Asm America, Inc. Epitaxial growth of relaxed silicon germanium layers
KR20060054387A (ko) * 2003-08-04 2006-05-22 에이에스엠 아메리카, 인코포레이티드 증착 전 게르마늄 표면 처리 방법
US8501594B2 (en) * 2003-10-10 2013-08-06 Applied Materials, Inc. Methods for forming silicon germanium layers
US7132338B2 (en) 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20100120235A1 (en) * 2008-11-13 2010-05-13 Applied Materials, Inc. Methods for forming silicon germanium layers
US7354815B2 (en) * 2003-11-18 2008-04-08 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
JP3901696B2 (ja) * 2004-02-19 2007-04-04 株式会社東芝 半導体装置及びその製造方法
WO2005084231A2 (en) 2004-02-27 2005-09-15 Asm Aemrica, Inc. Germanium deposition
JP4874527B2 (ja) * 2004-04-01 2012-02-15 トヨタ自動車株式会社 炭化珪素半導体基板及びその製造方法
WO2005116304A2 (en) * 2004-04-23 2005-12-08 Asm America, Inc. In situ doped epitaxial films
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
US7172933B2 (en) * 2004-06-10 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed polysilicon gate structure for a strained silicon MOSFET device
TWI463526B (zh) * 2004-06-24 2014-12-01 Ibm 改良具應力矽之ｃｍｏｓ元件的方法及以該方法製備而成的元件
DE102004031743B4 (de) * 2004-06-30 2006-10-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Epitaxieschicht für erhöhte Drain-und Sourcegebiete durch Entfernen von Oberflächendefekten der anfänglichen Kristalloberfläche
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