CN106847875B - 非平面栅极全包围器件及其制造方法 - Google Patents

非平面栅极全包围器件及其制造方法 Download PDF

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CN106847875B
CN106847875B CN201611070116.8A CN201611070116A CN106847875B CN 106847875 B CN106847875 B CN 106847875B CN 201611070116 A CN201611070116 A CN 201611070116A CN 106847875 B CN106847875 B CN 106847875B
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lattice constant
embedded
nanowire
drain
channel
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CN106847875A (zh
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W·拉赫马迪
R·皮拉里塞泰
V·H·勒
J·T·卡瓦列罗斯
R·S·周
J·S·卡治安
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Sony Corp
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Abstract

说明了一种非平面栅极全包围器件及其制造方法。在一个实施例中，器件包括衬底，所述衬底包含具有第一晶格常数的顶部表面。嵌入式外延源极区和嵌入式外延漏极区形成在所述衬底的顶部表面上。嵌入式外延源极区和嵌入式外延漏极区具有与所述第一晶格常数不同的第二晶格常数。具有第三晶格的沟道纳米线形成于嵌入式外延源极区和嵌入式外延漏极区之间，并与它们耦合。在一个实施例中，第二晶格常数和第三晶格常数与第一晶格常数不同。沟道纳米线包括最底部的沟道纳米线，底部栅极隔离物形成于最底部的沟道纳米线下方的衬底的顶部表面上。栅极电介质层形成于每一条沟道纳米线之上和周围。栅极电极形成于栅极电介质层上，并围绕每一条沟道纳米线。

Description

非平面栅极全包围器件及其制造方法
本申请为分案申请，其原申请的申请日是2014年8月22日，申请号为201180076433.X，发明名称为“非平面栅极全包围器件及其制造方法”。
技术领域
本发明的实施例涉及半导体器件领域，更具体地，涉及非平面栅极全包围器件及其制造方法。
背景技术
集成器件制造商不断收缩晶体管器件的特征尺寸，以实现更大的电路密度和更高的性能，对于下一代器件，需要增强晶体管驱动电流，同时减小短沟道效应，例如寄生电容和截止状态泄漏。增大晶体管驱动电流的一个方式是使用高载流子迁移率半导体材料以形成沟道。沟道中的高载流子迁移率支持较高晶体管驱动电流。载流子迁移率是载流子在外部单位电场下流入半导体材料的速度的测量。半导体基体上的过程感应应力(有时称为应力)是增大驱动电流的另一个方式。在半导体基体上感应应力增强了载流子迁移率，从而增大了晶体管器件中的驱动电流。
诸如三栅极晶体管的非平面晶体管是半导体工艺中用于控制短沟道效应的最近发展。就三栅极晶体管来说，栅极与沟道区的三个侧相邻。因为栅极结构围绕三个表面上的鳍状物，晶体管基本上具有三个栅极，控制通过鳍状物或沟道区的电流。由于更陡峭的亚阈值电流摆动(SS)和较小的漏极感应势垒降低(DIBL)，这三个栅极允许鳍状物中更充分的耗尽，导致较小的短沟道效应。不幸的是，第四个侧，沟道的底部远离栅极电极，因而不受附近的栅极控制。由于晶体管尺寸不断缩小到亚20-25nm技术节点，在源极与漏极之间的寄生泄漏路径对于三栅极晶体管成为了问题。
附图说明
在附图的图中示例性而非限制性地示出了本公开内容的实施例，其中：
图1A至1D示出了根据本发明实施例的具有嵌入式外延层源极区和漏极区的非平面栅极全包围器件。
图1E是没有嵌入式源极区和漏极区的非平面栅极全包围器件的图示。
图2是根据本发明实施例的表示形成非平面栅极全包围器件的方法中的步骤的流程图。
图3A至3M示出了根据本发明实施例的表示形成非平面栅极全包围器件的方法中的步骤的三维试图和二维视图。
图4示出了根据本发明的一个实现方式的计算设备400。
具体实施方式
本发明是创新的栅极全包围晶体管及制造方法。在以下说明中，阐述了多个细节以便提供对本发明的透彻理解。但显然，对于本领域技术人员来说，可以无需这些特定细节来实践本发明。在其他实例中，没有详细说明公知的半导体工艺和制造技术，以避免使得本发明模糊不清。在本说明书通篇中对“实施例”的提及表示结合该实施例说明的特定的特征、结构、功能或特性包括在本发明的至少一个实施例中。因而，说明书中多处出现的短语“在实施例中”不一定全都指代本发明同一实施例。而且，特定的特征、结构、功能或特性可以以任意适合的方式组合到一个或多个实施例中。例如，第一实施例可以与第二实施例组合，只要两个实施例不相互排斥。
本发明的实施例包括非平面栅极全包围晶体管器件，所述非平面栅极全包围晶体管器件具有由栅极电介质层和栅极电极完全包围的沟道纳米线。具有完全围绕沟道纳米线的栅极电极增大了栅极控制，由于完全切断了寄生泄漏路径而导致改进的短沟道效应。沟道纳米线布置在源极与漏极区之间。在本发明的一个或多个实施例中，沟道纳米线由未掺杂锗组成，并且受单轴晶格应力。未掺杂锗提供了比传统硅更高的载流子迁移率，单轴晶格应力进一步增强了沟道纳米线中的载流子迁移率，从而实现了极高的晶体管器件驱动电流。在本发明的实施例中，通过蚀刻掉与沟道纳米线相邻的鳍状物的部分，随后从衬底外延生长半导体材料以形成“嵌入式外延”源极区和漏极区来形成源极区和漏极区。嵌入式外延源极区和嵌入式外延漏极区对沟道纳米线提供了额外的力或支撑点，这有助于维持或增强，或者维持和增强沟道纳米线中的单轴晶格应力。另外，在本发明的实施例中，栅极全包围晶体管包括形成于衬底与底部沟道纳米线之间的底部栅极隔离层，以使得可以在无需容性耦合到衬底的情况下，完全包围底部沟道纳米线形成栅极电极。本发明的一个或多个实施例可以包括非平面栅极全包围晶体管器件，其中，具有嵌入式外延源极区和嵌入式外延漏极区或形成于衬底与底部沟道纳米线之间的底部栅极隔离层之一或者二者。
图1A至1D示出了根据本发明实施例的非平面栅极全包围器件100。图1A是电介质层101内的器件100的三维俯视/侧视图，图1B是通过嵌入式外延源极106和漏极107得到的横截面视图，图1C是通过栅极电极118得到的横截面视图。图1D是无电介质层101的器件100的三维俯视/侧视图。器件100包括衬底102，具有顶部表面104。嵌入式外延源极106和漏极107区布置在衬底102的顶部表面104上，沟道纳米线110耦合在嵌入式外延源极106和漏极107区之间。嵌入式外延源极106和漏极107区可以统称为嵌入式外延源极/漏极对。栅极电介质层116形成于每一条沟道纳米线110上并完全包围它，除了在沟道纳米线110的端部，在此，沟道纳米线110耦合到嵌入式外延源极106和漏极107区。栅极电极118形成于栅极电介质层116上，并完全围绕每一条沟道纳米线110。
在实施例中，衬底102的顶部表面104、嵌入式外延源极106和漏极107区和沟道纳米线110分别包括具有一晶格常数的材料。顶部表面104的晶格常数与嵌入式外延源极106和漏极107区和沟道纳米线110的晶格常数不同。在一个特定实施例中，嵌入式外延源极106和漏极107区和沟道纳米线110的晶格常数大于顶部表面104的晶格常数。在一个此类实施例中，衬底102的顶部表面104是硅锗，沟道纳米线110是未掺杂锗，嵌入式外延源极106和漏极107区是锗。在嵌入式外延源极106和漏极107区、沟道纳米线110与顶部表面104之间的晶格失配(例如晶格常数失配)导致沟道纳米线110与嵌入式外延源极106和漏极107区中的晶格应力。在一个实施例中，沟道纳米线110与嵌入式外延源极106和漏极107区在平行于沟道纳米线110的长度120的方向上被施加单轴晶格应力，在垂直于沟道纳米线110的长度120的方向上受晶格弛豫。在实施例中，在顶部表面104与嵌入式外延源极106和漏极107区之间的晶格常数失配还导致嵌入式外延源极106区和漏极107区对沟道纳米线110提供力。这个力可以有助于维持沟道纳米线110中的单轴晶格应力。
在实施例中，沟道纳米线110可以包括载流子迁移率大于单晶体硅的单晶材料。较高的载流子迁移率允许器件100实现较高的驱动电流和较大的性能。在一个特定实施例中，沟道纳米线110是未掺杂锗(Ge)。没有掺杂剂使得电荷载流子的散射最小且有助于使得沟道纳米线110中的载流子迁移率最大。
在本发明的实施例中，如图1A和1B所示的，嵌入式外延源极106和漏极107区可以布置在源极/漏极沟道108中，其中衬底102的顶部表面104被凹陷到浅沟槽隔离层105的顶部表面之下。在源极/漏极沟槽108中形成嵌入式外延源极106和漏极107区有助于限制嵌入式外延源极106和漏极107区的生长。但嵌入式源极106和漏极107区不一定形成于沟槽中，可以在衬底102的顶部表面104上，它与隔离区103在同一平面或在其之上。嵌入式外延源极106和漏极107区可以是<111>-刻面，其中，在嵌入式外延源极106和漏极107区的底部的宽度122大于在顶部的宽度124。在这个实施例中，对应于侧壁126和128的平面是嵌入式外延源极106和漏极107区的<111>晶格取向。
在实施例中，器件100包括底部栅极隔离物114，所述底部栅极隔离物114布置在衬底102的顶部表面104上且在最底部的沟道纳米线115之下。底部栅极隔离物114充当容性隔离势垒，以防止衬底102的顶部表面104通过栅极电极118寄生耦合。底部栅极隔离物114作为容性隔离势垒的有效性取决于形成它的材料及其厚度。在一个实施例中，底部栅极隔离物114由任何电介质材料形成(例如，氧化硅、氮化硅、氮氧化硅、低k电介质材料等)，其防止衬底102的顶部表面104通过栅极电极118的寄生耦合。在一个特定实施例中，底部栅极隔离物114由氧化硅层组成。在一个实施例中，底部栅极隔离物的厚度足以隔离衬底102的顶部表面104免于通过栅极电极118的容性耦合。在一个特定实施例中，底部栅极隔离物114在约
Figure BDA0001165023410000041
之间。底部栅极隔离物114使得最底部的沟道纳米线115能够由栅极电极118完全包围。如果底部栅极隔离物114不存在，则底部沟道纳米线115就需要由三栅极或类似的结构控制，以便防止在栅极电极118与衬底102的顶部表面之间的容性耦合，从而避免在“导通”器件时在衬底中形成不期望有的导电沟道。
在本发明的实施例中，衬底102可以包括一个或多个生长在不同的晶体衬底(硅、锗、砷化镓、兰宝石等)顶上的外延单晶半导体层(例如，硅、锗、硅锗、砷化镓、磷化铟、砷化铟镓、砷化铝镓等)。在一个此类实施例中，外延生长的半导体层是一个或多个缓冲层109，具有与不同晶体衬底的晶格常数不同。缓冲层109可以用于分级从不同晶体衬底到顶部表面104的晶格常数。例如，衬底102可以包括在不同晶体硅衬底上外延生长的硅锗(SiGe)缓冲层109。SiGe缓冲层109的锗浓度可以从在最底部的缓冲层的30％的锗增大到在最顶部的缓冲层的70％的锗，从而逐渐增大晶格常数。
在实施例中，浅沟槽隔离(STI)区103可以布置在衬底102上。STI区103用于减小在彼此相邻形成的器件100之间的电流泄漏。STI层105可以布置在STI区103中。STI层105可以包括任何公知的电介质材料，例如但不限于，氧化硅、氮化硅、氮氧化硅、低k电介质，及其任何组合。
如图1B所示的，沟道纳米线110形成在衬底102的顶部表面104上并在嵌入式外延源极106区与嵌入式外延漏极107区之间。沟道纳米线110可以由任何公知的材料构成，例如但不限于，Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、InP和碳纳米管。沟道纳米线110可以由任何公知的材料构成，其可以通过施加外电场从绝缘状态相对地改变为导电状态。理论上，为了较高的器件性能，在另一个实施例中，沟道纳米线110由未掺杂受晶格应力的单晶半导体材料构成，其具有大于单晶硅的载流子迁移率。如前解释的，沟道纳米线110中没有掺杂剂使得电荷载流子的散射最小，有助于使得载流子迁移率最大，从而增大驱动电流。沟道纳米线110中的晶格应力还增强了载流子迁移率并改进了器件性能。典型地，沟道纳米线受压缩应力，用于p型晶体管器件中增强的空穴迁移率，和受拉伸应力，用于n型晶体管器件中增强的电子迁移率。在一个实施例中，沟道纳米线110在平行于沟道纳米线110的长度120的方向上受单轴晶格应力，但在垂直于沟道纳米线110的长度120的方向上受晶格弛豫。在另一个实施例中，沟道纳米线110可以是掺杂的单晶半导体材料。例如，纳米线110可以由掺杂单晶硅构成。在掺杂沟道纳米线110时，典型地在形成NOMS晶体管器件时将沟道纳米线110掺杂为p型导电类型，且在形成POMS晶体管器件时将沟道纳米线110掺杂为n型导电类型。
如图1B所示的，沟道纳米线110可以与顶部表面104平行地延伸并形成沟道纳米线110的垂直阵列。在一个实施例中，在嵌入式外延源极106和漏极107区之间的沟道纳米线的数量是3到6条。更大数量的沟道纳米线110允许通过器件100的更大的驱动电流。沟道纳米线110具有厚度130、宽度132和长度120。在本发明的一个实施例中，厚度130在约5－30nm之间，宽度132在约5－50nm之间，长度120在10－100nm之间。在一个实施例中，沟道纳米线110可以是带状纳米线，其中，沟道纳米线的宽度132大于厚度130。在进一步的实施例中，沟道纳米线110的横截面可以是圆形或椭圆形，而不是矩形的。沟道纳米线的长度120实质上限定晶体管器件100的栅极长度(Lg)。沟道纳米线110的有效栅极“宽度”(Wg)是沟道纳米线110的周长。例如，对于具有矩形横截面的沟道纳米线，沟道纳米线110的有效栅极“宽度”是沟道纳米线110的宽度132的两倍与厚度130的两倍的总和。晶体管器件100的有效栅极“宽度”(Wg)是沟道纳米线110的周长的总和。
如图1B所示的，嵌入式外延源极106区和嵌入式外延漏极107区形成于沟道纳米线110的相对端部上并耦合到沟道纳米线110。嵌入式外延源极106和漏极107区可以由具有晶格常数的任何公知的材料构成。理论上，嵌入式外延源极106和漏极107区由外延生长的单晶半导体构成，例如但不限于，Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在一个实施例中，嵌入式外延源极106和漏极107区由具有不同于衬底102的顶部表面104的晶格常数的单晶半导体材料构成。如前所述的，在嵌入式外延源极106和漏极107区与衬底102的顶部表面104之间的晶格常数失配在嵌入式外延源极106和漏极107区中产生晶格应力，从而改进了电子迁移率和晶体管性能。在一个实施例中，嵌入式外延源极106和漏极107区在平行于长度120的方向上被施加单轴晶格应力，在垂直于长度120的方向上受晶格弛豫。在嵌入式外延源极106和漏极107区与衬底102的顶部表面104之间的晶格常数失配还导致嵌入式外延源极106和漏极107区在沟道纳米线110上施加力，这有助于维持沟道纳米线110中的晶格应力。在实施例中，嵌入式外延源极106区和嵌入式外延漏极107区由与用于构成沟道纳米线110相同的单晶半导体材料构成。
在特定实施例中，嵌入式外延源极106和漏极107区的晶格常数大于衬底102的顶部表面104的晶格常数。在这个实施例中，嵌入式外延源极106区和嵌入式外延漏极107区受压缩应力，并对沟道纳米线110提供压缩力。在一个特定实施例中，嵌入式外延源极106和漏极107区是外延单晶锗，衬底102的顶部表面104是外延单晶硅锗。锗源极106和漏极107区在沟道纳米线110上施加压缩力。在一个实施例中，半导体衬底102的顶部表面104可以由具有第一晶格常数的半导体材料构成(例如硅锗)，沟道纳米线110由具有大于第一晶格常数的第二晶格常数的第二半导体材料构成(例如锗)，嵌入式外延源极106和漏极107区可以由具有第三晶格常数的第三半导体材料构成(例如砷化镓(GaAs))，第三晶格常数大于沟道纳米线110的晶格常数(第二晶格常数)，以进一步增强沟道纳米线110中的压缩应力。
在另一个实施例中，嵌入式外延源极106和漏极107区的晶格常数小于衬底102的顶部表面104的晶格常数。在这个实施例中，嵌入式外延源极106和漏极107区受拉伸应力，并对沟道纳米线110提供拉伸力。在一个实施例中，半导体衬底102的顶部表面104可以由具有第一晶格常数的单晶半导体材料构成，沟道纳米线110由具有小于第一晶格常数的第二晶格常数的第二半导体材料构成，嵌入式外延源极106和漏极107区可以由具有第三晶格常数的第三半导体材料构成，第三晶格常数小于沟道纳米线110的晶格常数(第二晶格常数)以进一步增强沟道纳米线110中的拉伸应力。
典型地，嵌入式外延源极106和漏极107在构成NMOS晶体管器件时被构成为n型导电类型，且在构成PMOS晶体管器件时被构成为p型导电类型。在本发明的一个实施例中，嵌入式外延源极106和漏极107区具有在1E18个原子/cm3到1E21个原子/cm3之间的掺杂浓度。嵌入式外延源极106和漏极107区可以形成为具有一致的浓度，或者可以包括不同浓度或掺杂分布图的子区域。在一个实施例中，在将器件100形成为对称晶体管时，嵌入式外延源极106和漏极107区具有相同的掺杂浓度和分布图。在另一个实施例中，将器件100形成为非对称晶体管，且嵌入式外延源极106和嵌入式外延漏极107区的掺杂浓度分布图可以变化，以便实现本领域中公知的任何特定电气特性。
将源极106和漏极107区称为嵌入式外延源极106区和嵌入式外延漏极107区，因为它们形成为如以下将更详细说明的那样，通过首先去除鳍状物的用于产生受应力的沟道纳米线110的部分，随后外延生长源极和漏极对。例如，在一个实施例中，去除用于产生受应力的纳米线110的部分鳍状物，随后从衬底102的顶部表面104外延生长源极和漏极对。外延沉积的源极和漏极对的晶格从衬底的顶部表面104的晶格继续。即下层衬底的晶格指定上覆盖的嵌入式外延源极106和漏极107区的晶格方向和生长。嵌入式外延源极106和漏极107区的使用通过向沟道纳米线提供附加力并通过向沟道纳米线提供支撑点，以帮助维持由诸如鳍状物构图之类的较早制造过程而已经存在的沟道纳米线110中的单轴应力来改进器件性能。嵌入式外延源极区和嵌入式外延漏极区受应力，因而进一步向相邻纳米线沟道施加应力。可以通过使用具有与用于形成沟道纳米线的半导体材料不同晶格常数的半导体材料来进一步增强沟道纳米线中的应力。
另外，尽管半导体器件100理论上包括嵌入式外延源极106和漏极107区以增强沟道纳米线110中的应变，但实施例不一定包括嵌入式源极区和嵌入式漏极区。在本发明的一个实施例中，如图1E所示的，晶体管150可以包括源极156和漏极157区，由用于产生受单轴应力的沟道纳米线110的鳍状物膜叠层形成。例如，源极156和漏极157区可以由用于产生受应力的沟道纳米线110的半导体材料160和牺牲材料170(例如分别为锗和硅锗)及衬底102的交替层构成。在此情况下，源极156和漏极157区由单晶半导体薄膜的异质叠层构成。如本领域公知的，可以将源极156和漏极157区掺杂为期望的导电类型和程度。另外，如果期望的话，可以通过在源极156区和漏极157区上沉积额外的外延半导体材料(未示出)来形成升高的源极区和漏极区，以增大源极区和漏极区的厚度并降低电流拥挤，从而减小器件的接触电阻。晶体管150包括栅极隔离物114，用以隔离在最底部的纳米线115以下的栅极118免于与衬底102的容性耦合。
如图1B和1C所示的，栅极电介质层116形成于每一条沟道纳米线110上并完全包围每一条沟道纳米线110。栅极电介质层116可以是任何公知的栅极电介质层，例如但不限于，SiO2、SiON和SiN。在一个实施例中，栅极电介质层116是高k栅极电介质层，例如金属氧化物电介质(例如Ta2O5、TiO2、HfO2、HfSiOx、ZrO2等)。栅极电介质层116也可以是其他类型的高k电介质层，例如但不限于PZT和BST。栅极电介质层也可以是以上电介质材料的任何组合。栅极电介质层116可以形成为约
Figure BDA0001165023410000091
之间的厚度。在特定实施例中，栅极电介质层116是HfO2且形成为约1-6纳米之间的厚度。
栅极电极118形成于栅极电介质层116上且完全围绕每一条沟道纳米线110。栅极电极118在垂直于沟道纳米线110的长度120的方向上延伸。栅极电极118可以由任何适合的栅极电极材料构成。在一个实施例中，栅极电极118可以是金属栅极电极，例如但不限于，Ti、TiN、TaN、W、Ru、TiAl及其任意组合。在器件100是NMOS晶体管器件的实施例中，栅极电极118由具有在3.9-4.2eV之间的逸出功的材料构成。在器件PMOS晶体管器件的实施例中，栅极电极118由具有在4.8-5.2eV之间的逸出功的材料构成。在器件100中的沟道纳米线110未掺杂或极轻掺杂的实施例中，栅极电极118可以由具有在4.3-4.7eV之间的中能隙逸出功的材料构成。在特定实施例中，栅极电极118是TiAl。
因为栅极电极118和栅极电介质层116完全围绕每一条沟道纳米线110，器件100可以是以完全耗尽方式工作的晶体管，其中，当器件100“导通”时，沟道纳米线110完全耗尽，从而提供完全耗尽的晶体管器件的有利电气特性和性能。当器件100“导通”时，连同在每一条沟道纳米线的表面的反型层一起在每一条沟道纳米线110中形成耗尽区。反型层具有与嵌入式外延源极106和漏极107区相同的导电类型，在嵌入式外延源极106和漏极107区之间形成导电沟道以允许电流在其之间流动。耗尽区耗尽了来自反型层下面的自由载流子。除了反型层以外，每一条沟道纳米线110都耗尽了载流子，因而晶体管可以称为“完全耗尽”晶体管。完全耗尽晶体管具有高于非完全耗尽的或部分耗尽的晶体管的改进的电气性能特性。以完全耗尽方式操作晶体管给与晶体管理想的或极为陡峭的亚阈值斜度。极为陡峭的亚阈值斜度导致改进的短沟道效应，例如改进的漏极感应势垒降低(DIBL)。
图2是根据本发明实施例的表示制造非平面栅极全包围器件的方法的流程图200。图3A至3M示出了根据本发明实施例的表示制造非平面栅极全包围器件的方法中的步骤的三维和二维横截面图。方法在流程图200中的步骤202处通过提供具有形成于其上的鳍状物304的衬底301开始。衬底301是在其上形成非平面栅极全包围器件的材料。衬底301包含具有晶格常数的顶部表面303。在一个实施例中，衬底301包括具有晶格常数的上单晶层。在一个此类实施例中，衬底301可以包括一个或多个缓冲层311，生长在不同单晶衬底与上单晶层之间。缓冲层311可以用于将晶格常数从不同晶体衬底的晶格常数逐渐改变为上单晶层的晶格常数。缓冲层311可以由外延生长的单晶半导体材料构成，例如但不限于，Si、Ge、GeSn、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在其上形成缓冲层311的不同晶体衬底可以是具有晶格常数的任何单晶材料(例如，硅、锗、砷化镓、兰宝石等)。在一个特定实施例中，衬底301可以包括外延生长在不同单晶硅衬底上的硅锗(SiGe)缓冲层。SiGe缓冲层的锗浓度可以从用于最底部的缓冲层的30％的锗增大到用于最顶部的缓冲层的弛豫的70％的锗。
在实施例中，鳍状物304形成为具有半导体材料308和牺牲材料310的交替层。半导体材料308的层随后形成于沟道纳米线343中。牺牲材料310的层通过与半导体材料308的层晶格常数失配而引起在半导体材料308的层上的晶格应力。在一个实施例中，半导体材料308的层与牺牲材料310的层可以由具有晶格常数的任何公知的材料构成。理论上，半导体材料308的层与牺牲材料310的层由单晶半导体材料构成，例如但不限于，Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb和InP。在一个实施例中，半导体材料308的层具有与牺牲材料310的层和衬底301的顶部表面303的晶格常数不同的晶格常数。作为在顶部表面303、半导体材料308的层和牺牲材料310的层之间晶格失配的结果，鳍状物304受晶格应力。在一个特定实施例中，半导体材料308的层的晶格常数大于牺牲材料310的层与顶部表面303的晶格常数。例如，半导体材料308的层可以是未掺杂的锗，顶部表面303可以是具有70％锗浓度的硅锗，牺牲材料310的层可以是具有70％锗浓度的硅锗。对于这个实施例，在材料之间的晶格失配导致半导体材料308的层在鳍状物304中受压缩晶格应力。在另一个实施例中，半导体材料308的层的晶格常数小于牺牲材料310的层与顶部表面303的晶格常数。例如，半导体材料308的层可以是硅，顶部表面303可以硅锗，牺牲材料310的层可以是硅锗。对于这个实施例，在材料之间的晶格常数导致半导体材料308的层在鳍状物304中受拉伸晶格应力。由于牺牲材料层310和半导体材料层308以不同的晶格常数交替，半导体材料层由下面的牺牲材料层310施加双轴应力。
可以使用传统外延化学气相沉积法通过首先在衬底301的顶部表面303上均厚沉积半导体材料308与牺牲材料310的交替层来形成鳍状物304。接下来，使用传统光刻和蚀刻法形成半导体材料308和牺牲材料310的覆盖层的图案来限定鳍状物304。在本发明的一个实施例中，同样蚀刻衬底301以使得鳍状物304的底部包括衬底部309，如图3A所示的。以此方式，鳍状物的衬底部309充当鳍状物304的牺牲材料310的底部。在一个实施例中，使得鳍状物304的衬底部309比牺牲材料层310后，以便在衬底与最底部的沟道纳米线之间提供额外的空间，以使得底部栅极隔离膜与栅极电极、栅极电介质可以形成在衬底与底部沟道纳米线之间。在一个实施例中，在形成图案过程中，也可以形成衬底301的图案以构成与鳍状物304和STI(浅沟槽隔离)区315连续的衬底区312。STI区315用于减小在彼此相邻形成的非平面栅极全包围器件之间的电流泄漏。在一个实施例中，与鳍状物304连续的至少部分衬底区312可以包括衬底301的缓冲层311。在一个实施例中，以STI电介质层305填充STI区315。STI电介质层305可以是任何公知的电介质层，例如但不限于，氧化硅、氮化硅、氮氧化硅、的k电介质及其任何组合。使用传统化学气相沉积法通过首先在衬底301上和鳍状物304上均厚沉积STI电介质层305来形成STI电介质层305。STI电介质层305最初沉积为大于鳍状物304与衬底区312的组合厚度的厚度。接下来，使用传统化学机械平面化方法使STI电介质层305平面化。随后使用传统蚀刻法使STI电介质层305凹陷，以暴露出鳍状物304，如图3A所示的。在一个实施例中，使得STI电介质凹陷到低于衬底301的顶部表面303，以使得鳍状物304的底部由衬底301构成，如图3A所示的。以此方式，鳍状物304包括衬底部309，其充当鳍状物304的底部牺牲材料310。在一个实施例中，鳍状物304的衬底部309比上面的牺牲材料层310厚，以便在衬底与最底部的沟道纳米线之间提供额外的空间，以使得可以在衬底与底部沟道纳米线之间形成底部栅极隔离膜和栅极电极/栅极电介质。或者，可以在顶部表面303与最底部的半导体材料层308之间形成不同的牺牲层。
鳍状物304具有侧壁302和306、鳍状物高度316、鳍状物宽度318和鳍状物长度320。在鳍状物304的形成中，侧壁302和306是无约束的平面，其允许鳍状物304在垂直于鳍状物长度320的方向上晶格弛豫。即将上述的受双轴应力层减小到在鳍状物形成时的基本上受单轴应力层。在一个事实力中，鳍状物304在平行于鳍状物长度320的方向上受单轴晶格应力，在垂直于鳍状物长度320的方向上受晶格弛豫。在一个实施例中，鳍状物304形成为具有小于30nm，理想地小于25nm的鳍状物宽度318。在一个实施例中，鳍状物高度316小于开始出现集成问题的高度，例如鳍状物倾倒，鳍状物剖面变形、和鳍状物临界尺寸中较差的均匀性。在特定实施例中，鳍状物高度316在30-75nm之间。
半导体材料308的层和牺牲材料310的层的厚度影响沟道纳米线343的电气特性和器件100的集成与性能。在一个实施例中，半导体材料308的层的厚度足以避免形成具有过多表面散射及因此的高沟道电阻和低载流子迁移率的沟道纳米线343。半导体材料308的层还足够薄以形成允许器件100以完全耗尽方式工作的沟道纳米线343。牺牲材料310的层的厚度影响在沟道纳米线343之间随后的间隔，因而影响完全包围每一条沟道纳米线343形成栅极电介质层350与栅极电极352的能力。在实施例中，牺牲材料310的层足够厚，以使得栅极电介质层350随后可以完全包围沟道纳米线343形成，栅极电极352可以在栅极电介质层350上形成，以完全围绕沟道纳米线343。半导体材料308的层与牺牲材料310的层的厚度还影响鳍状物高度316。在一个实施例中，半导体材料308的层与牺牲材料310的层足够薄，以实现鳍状物高度316小于开始出现集成问题的高度。在特定实施例中，半导体材料308的层形成为约5-50nm之间的厚度，且牺牲材料310的层形成为约5-30nm之间的厚度。
半导体材料308和牺牲材料310的交替层的总数影响器件的鳍状物高度316和驱动电流容量。半导体材料308的层数对应于随后形成的沟道纳米线343的数量。较大数量的沟道纳米线343允许较大的器件100的驱动电流容量。但半导体材料308和牺牲材料310过多的层导致无法集成的鳍状物高度316。在实施例中，层308和310的数量足够低，以实现可集成的鳍状物高度316。在特定实施例中，鳍状物304具有约3-6层的半导体材料308和3-6层的牺牲材料310。
参考流程图200中的步骤204及相应的图3B和3C，在鳍状物304的沟道区328上方形成牺牲栅极电极352。牺牲栅极电极352限定晶体管器件的沟道区。通过在鳍状物304上首先均厚沉积牺牲栅极电介质层322来形成牺牲栅极电极352。牺牲栅极电介质层322沉积在鳍状物304的顶上和侧壁上。牺牲栅极电介质层322可以沉积为约
Figure BDA0001165023410000131
之间的厚度。如图3B所示的，随后在牺牲栅极电介质层322和鳍状物304上均厚沉积牺牲栅极层324。牺牲栅极层324沉积为超过鳍状物厚度316的厚度。可以使用传统化学机械平面化方法使牺牲栅极层324平面化。接下来，如图3C所示的，通过使用传统光刻和蚀刻方法形成牺牲栅极层324的图案来形成牺牲栅极326。牺牲栅极电极326形成于鳍状物304的沟道区328上，具有大于鳍状物高度316的厚度329。牺牲栅极电极326随后用于在去除鳍状物304的牺牲部分332期间保护鳍状物304的沟道区328。
在形成牺牲栅极电极的图案期间，在牺牲栅极电极352的相对侧上暴露出鳍状物304的牺牲部分332上的牺牲栅极电介质层322。牺牲栅极电介质层322在牺牲栅极电极326的图案形成和形成过程中充当蚀刻停止层，从而使鳍状物304免于受损。在一个实施例中，牺牲栅极电介质层322和牺牲栅极层324由具有足够不同的蚀刻选择性的材料构成，其中，牺牲栅极电介质层322可以充当用于蚀刻牺牲栅极层324的蚀刻停止层。在一个特定实施例中，牺牲栅极电介质层322是电介质层(例如氧化硅、氮化硅、和氮氧化硅)，牺牲栅极层324由半导体材料构成(例如多晶硅)。可以使用传统化学气相沉积法来沉积牺牲栅极电介质层322和牺牲栅极层324。接下来，使用传统湿法蚀刻工艺从鳍状物304的牺牲部分322的顶上和侧壁302、306去除牺牲栅极电介质层322，以暴露出鳍状物304的牺牲部分322。在牺牲栅极电介质层322是氧化硅层的实施例中，使用稀释HF湿法蚀刻来去除牺牲栅极电介质层322。
参考流程图200的步骤206及相应地图3C，在牺牲栅极电极326的相对侧壁334上形成一对侧壁间隔物330。可以使用本领域中已知的形成选择性间隔物的传统方法形成侧壁间隔物330对。在一个实施例中，首先在包括鳍状物304和牺牲栅极电极326的全部结构上均厚沉积保形电介质间隔物层，例如但不限于，氧化硅、氮化硅、氮氧化硅及其组合。保形方式沉积电介质间隔物层，以使得它在诸如侧壁302、306、334的垂直表面和诸如牺牲栅极电极326的顶部的水平表面上形成为基本上相等的厚度。可以使用诸如低压化学气相沉积(LPCVD)和等离子体增强化学气相沉积(PECVD)的传统化学气相沉积法沉积电介质间隔物层。在一个实施例中，将电介质间隔物层沉积为约2-10纳米之间的厚度。接下来，使用诸如活性离子蚀刻(RIE)的传统各向异性蚀刻法在电介质间隔物层上执行无图案形成的各向异性蚀刻。在各向异性蚀刻过程中，从水平表面去除了大多数电介质间隔物层，在垂直表面上留下电介质间隔物层，例如牺牲栅极电极326的侧壁334和鳍状物304的侧壁302、306。因为牺牲栅极电极306的厚度329大于鳍状物高度316，各向异性蚀刻后剩余的电介质间隔物层在牺牲栅极电极326的侧壁334上的厚度大于在鳍状物304的侧壁302、306上的。这个厚度差允许侧壁间隔物330在牺牲栅极电极326的侧壁334上的选择性形成。接下来，执行无图案形成的各向异性蚀刻，以从鳍状物304的侧壁302、306去除剩余电介质间隔物层，在牺牲栅极电极326的相对侧壁334上留下一对侧壁间隔物330。在一个实施例中，各向异性蚀刻是湿法蚀刻过程。在电介质间隔物层是氮化硅或氧化硅的一个特定实施例中，各向异性蚀刻使用分别包括磷酸(H3PO4)或缓冲氧化物蚀刻(BOE)的液体蚀刻剂溶液。在可替换的实施例中，各向异性蚀刻是干法蚀刻过程。在一个此类实施例中，在下游的等离子体反应器中采用NF3用以各向异性蚀刻电介质间隔物层。
参考流程图200中的步骤208及相应的图3D，去除鳍状物304的牺牲部分332，以暴露出衬底301的源极/漏极区334。可以使用诸如湿法蚀刻或等离子体干法蚀刻的传统蚀刻方法去除鳍状物304的牺牲部分332。在鳍状物304包括锗308和硅锗310的交替层的实施例中，诸如氢氧化铵(NH4OH)或氢氧化四甲铵(TMAH)溶液的液体蚀刻剂用于选择性蚀刻掉鳍状物304的牺牲部分332。由牺牲栅极326和侧壁间隔物330对保护鳍状物304的沟道区328免于蚀刻。在一个实施例中，在去除鳍状物304的牺牲部分332的过程中使衬底301的顶部表面303凹陷，以形成源极/漏极沟槽336。源极/漏极沟槽336用于容纳随后的嵌入式外延源极338和漏极339区的生长。在一个实施例中，源极/漏极沟槽336形成为20至40nm之间的深度。或者，去除鳍状物304的牺牲部分332，以使得衬底301的顶部表面303在STI电介质层305上方或与之在同一平面。
参考流程图200的步骤210及相应的图3E，嵌入式外延源极338区和嵌入式外延漏极339区形成于衬底301的源极/漏极区334上。在一个实施例中，嵌入式外延源极338和漏极339区使用传统外延沉积方法来形成，例如低压化学气相沉积、气相外延和分子束外延。在一个实施例中，嵌入式外延源极338和漏极339区形成于源极/漏极沟槽336中。嵌入式外延源极338和漏极339区与鳍状物304的沟道区328耦合，上升到STI电介质层305的顶部表面以上。嵌入式外延源极338和漏极339区可以由具有晶格常数的任何公知的材料构成。理论上，嵌入式外延源极338和漏极339区由单晶半导体材料构成，例如但不限于，Si、Ge、SiGe、GeSn、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、GaN、GaP和InP。在实施例中，嵌入式外延源极338和漏极339区由与衬底301的顶部表面303具有不同晶格常数的单晶半导体材料构成。在特定实施例中，嵌入式外延源极338区和嵌入式外延漏极339区具有比衬底301的顶部表面303的晶格常数大的晶格常数。
在特定实施例中，嵌入式外延源极338和漏极339区由锗构成，衬底301的顶部表面303是硅锗。在本发明的一个实施例中，嵌入式外延源极338和漏极339区由与用于构成晶体管的沟道纳米线的相同的半导体材料(例如Ge)构成。在本发明的一个实施例中，嵌入式外延源极338和漏极339区由具有晶格常数的材料(例如，GaAs)构成，其晶格常数大于衬底301的顶部表面303的半导体材料(例如(SiGe)的晶格常数，并且大于用于构成沟道纳米线的半导体材料(例如Ge)308的晶格常数，以便进一步增强沟道纳米线中的单轴压缩晶格应力。
在另一个特定实施例中，嵌入式外延源极338区和嵌入式外延漏极339区由硅构成，衬底301的顶部表面303是硅锗。在本发明的一个实施例中，嵌入式外延源极338和漏极339区由与用于构成晶体管的沟道纳米线的相同的半导体材料(例如Si)构成。在本发明的一个实施例中，嵌入式外延源极338和漏极339区由具有晶格常数的材料(例如碳化硅或碳掺杂硅)构成，其晶格常数小于衬底301的顶部表面303的半导体材料(例如SiGe)的晶格常数，并且小于用于构成沟道纳米线的半导体材料(例如Si)308的晶格常数，以便进一步增强沟道纳米线中的单轴拉伸晶格应力。
在嵌入式外延源极338和嵌入式外延漏极339区与衬底301的顶部表面303之间的晶格常数失配产生晶格应力，其中，嵌入式外延源极338和嵌入式外延漏极339区在平行于鳍状物304的长度320方向上受单轴晶格应力。嵌入式外延源极338和漏极339区在垂直于鳍状物304的长度329方向上晶格弛豫，因为对应于侧壁335和337的平面在形成嵌入式外延源极338和漏极339区的过程中无约束。晶格常数失配还导致嵌入式外延源极338和漏极339区在鳍状物304的沟道区328上施加力。因为鳍状物304的沟道区328中的半导体材料308的层随后会变为沟道纳米线，嵌入式外延源极338和漏极339区随后将在沟道纳米线343上施加力，这有助于维持沟道纳米线343中的晶格应力。在一个实施例中，嵌入式外延源极338和漏极339区的晶格常数大于301衬底的顶部表面303。在这个实施例中，嵌入式外延源极338和漏极339区受压缩应力，并对沟道纳米线343提供压缩力。在另一个实施例中，嵌入式外延源极338和漏极339区的晶格常数小于301衬底的顶部表面303。在这个实施例中，嵌入式外延源极338和嵌入式外延漏极339区受拉伸应力，并对沟道纳米线343提供拉伸力。
总之，在实施例中，在对纳米线形成层与居间牺牲层的叠层的鳍状物构图期间，沿纳米线形成层的沟道区形成初始单轴应力。随后通过蚀刻掉鳍状物的外侧部分，并随后在其位置形成外延源极区和漏极区，来形成嵌入式外延源极区和嵌入式外延漏极区。在一个此类实施例中，从鳍状物下面的衬底的晶体表面生长嵌入式外延源极区和嵌入式外延漏极区。在去除的外侧部分与交替的不同成分的纳米线形成层和居间牺牲层异质的情况下，通过外延生长以嵌入式源极区和漏极区的替换以成分同质的区域取代异质的部分。因而，将新晶格失配增加到蚀刻的鳍状物的任一侧上。嵌入式外延源极区和嵌入式外延漏极区于是进一步增强已经存在于纳米线形成层中的单轴应力。而且，在随后去除居间牺牲层时，嵌入式外延源极区和嵌入式外延漏极区起作用以固定随后形成的分离的纳米线。由于从下层衬底外延生长嵌入式外延源极区和嵌入式外延漏极区，固定对于在鳍状物构图过程中维持沿纳米线形成层的沟道区形成的初始单轴应力是有效的。因而，嵌入式外延源极区和嵌入式外延漏极区都维持并增强最终形成的纳米线沟道部分的单轴应力。注意，以上以同质层取代异质层可以通过使用与纳米线形成层相同的材料来执行。但在另一个实施例中，为了进一步增强单轴应力，可以外延生长与用于异质叠层的任何材料都不同的材料以形成嵌入式外延源极区和嵌入式外延漏极区。例如，在一个实施例中，由晶格常数大于异质鳍状物中任何材料的材料形成嵌入式外延源极区和嵌入式外延漏极区。在该实施例中，在最终形成的纳米线沟道部分中进一步增强单轴压缩应力。在另一个实施例中，由晶格常数小于异质鳍状物中任何材料的材料形成嵌入式外延源极区和嵌入式外延漏极区。在该实施例中，在最终形成的纳米线沟道部分中进一步增强单轴拉伸应力。
在实施例中，衬底301的源极/漏极区334的顶部表面303是具有<100>取向的单晶材料，其充当嵌入式外延源极338和漏极339区的外延生长的种子层。嵌入式外延源极338和漏极339区因而在<100>取向上生长。在嵌入式外延源极338和漏极339区的形成过程中，对应于侧壁335和337的<111>平面可以以更有利的速率生长，导致嵌入式外延源极338和漏极339区是<111>-刻面的。
应当意识到，如图3D和3D所示的，尽管期望通过蚀刻掉鳍状物304的牺牲部分332，随后外延生长以形成源极区和漏极区，来形成嵌入式外延源极338和漏极339区，以便增强沟道纳米线的应力，但不必如此。在可替换的实施例中，不蚀刻掉鳍状物304的牺牲部分332，并保留以形成器件的源极区和漏极区，例如图1E中所示的。此时，可以借助诸如离子注入的公知技术掺杂鳍状物304的牺牲部分332，以形成期望导电类型和浓度级别的源极区和漏极区。另外，如果期望的话，可以在鳍状物304的牺牲部分334的顶部上和侧壁上生长外延半导体膜，用以形成升高的源极区和漏极区，从而减小电流拥挤。
接下来，参考图3F，将夹层电介质(ILD)层340均厚沉积在所有结构上，包括升高的源极338和漏极339区、牺牲栅极电极326和侧壁间隔物334对。可以使用传统化学气相沉积法(例如等离子体增强化学气相沉积和低压化学气相沉积)来沉积覆盖ILD层340。在一个实施例中，ILD层340由任何公知的电介质材料构成，例如但不限于，未掺杂的氧化硅、掺杂的氧化硅(例如BPSG、PSG)、氮化硅和氮氧化硅。随后使用传统化学机械平面化方法抛光ILD层340，以暴露出牺牲栅极电极326的顶部和侧壁间隔物334对的顶部。
参考流程图200中的步骤212及相应的图3G和3H，去除牺牲栅极电极326，以暴露出鳍状物304的沟道区328。图3H是图3H的二维对应横截面视图。ILD层340在去除牺牲栅极电极326的过程中保护嵌入式外延源极338和漏极339区。可以使用诸如等离子体干法蚀刻或湿法蚀刻的传统蚀刻方法去除牺牲栅极电极326。在牺牲栅极电极326是多晶硅，ILD层340是氧化硅的实施例中，诸如TMAH溶液的液体蚀刻剂可以用于选择性去除牺牲栅极电极326。在鳍状物304的沟道区328上的牺牲栅极电介质层322充当蚀刻停止层，在去除牺牲栅极电极326的过程中保护鳍状物304的沟道区328。接下来，使用传统蚀刻方法去除牺牲栅极电介质层322，以在流程图200中的步骤214之前暴露出鳍状物304的沟道区328。在牺牲栅极电介质层322是氧化硅的实施例中，稀释的HF湿法蚀刻可以用于去除牺牲栅极电介质层322。
参考流程图200中的步骤214及相应的图3I，在鳍状物304的沟道区328中的半导体材料308的层之间去除牺牲材料310的层，以形成沟道纳米线343。牺牲材料310的层可以使用任何公知的蚀刻剂来去除，其对于半导体材料308的层具有选择性，在此，蚀刻剂以明显高于半导体材料308的层的速度蚀刻牺牲材料310的层。在一个实施例中，蚀刻剂选择性地蚀刻半导体材料308的层，同时不蚀刻牺牲材料310的层。在半导体材料308的层是锗，牺牲材料310的层是硅锗的实施例中，牺牲材料310的层可以使用液体蚀刻剂来选择性去除，包括但不限于，氢氧化铵(NH4OH)、氢氧化四甲铵(TMAH)、乙二胺邻苯二酚(EDP)、或氢氧化钾(KOH)溶液。在半导体材料308的层是硅，牺牲材料310的层是硅锗的实施例中，牺牲材料310的层可以使用液体蚀刻剂来选择性去除，包括但不限于，羧酸/硝酸/HF水溶液和柠檬酸/硝酸/HF水溶液。牺牲材料310的层的去除在半导体材料308的层之间留下空隙342。在半导体材料308的层之间的空隙342具有约5－30nm之间的厚度。剩余的半导体材料308的层形成沟道纳米线343的垂直陈列，其耦合到嵌入式外延源极338和漏极339区。形成的沟道纳米线343具有约5-50nm之间的厚度。沟道纳米线343平行于表面303延伸且彼此对准，以形成单列的沟道纳米线343，其中，最底部的沟道纳米线344位于列的最底部。
在实施例中，如图3I所示的，去除在嵌入式外延源极区和嵌入式外延漏极区之间的所有牺牲材料310，包括在侧壁间隔物330之下的部分。蚀刻间隔物之下的部分简化了制造，因为牺牲材料310的去除可以基于蚀刻相对于牺牲材料与嵌入式外延源极区和嵌入式外延漏极区的选择性，实现了将过蚀刻用于去除牺牲材料。但间隔物330之下的牺牲材料310的去除可以导致在最顶部的沟道纳米线343之上的间隔物330之间形成的略大的开口。这可以导致与最顶部的沟道纳米线之上的栅极长度相比，随后形成的栅极电极在沟道纳米线之间具有略大的栅极长度。在一个实施例中，利用定时蚀刻，以使得牺牲材料310与嵌入式外延源极区和嵌入式外延漏极区相邻的部分在蚀刻牺牲材料310以形成沟道纳米线343之后，保留在间隔物330之下。以此方式，随后形成的栅极电极可以相邻于沟道纳米线的所有表面而具有相同的栅极长度。
参考流程图200中的步骤216及相应的图3J和3K，在衬底301的顶部表面303之上和最底部的沟道纳米线343下方形成底部栅极隔离物348。通过首先在沟道纳米线343周围及上面均厚沉积电介质层346来形成底部栅极隔离物348，如图3J所示的。电介质层346完全填充在沟道纳米线343之间的空隙342，包括在最底部的沟道纳米线344与衬底301的顶部表面303之间区域。电介质层346还形成于ILD层340的顶部表面上。在一个实施例中，电介质层346由任何公知的电介质材料构成，例如但不限于，氧化硅、氮化硅、和氮氧化硅。在一个特定实施例中，电介质层346由氧化硅构成。理论上，电介质层346使用高保形沉积方法来形成，例如低压化学气相沉积(LPCVD)、原子层沉积(ALD)或旋涂电介质工艺，以确保完全填充在沟道纳米线343之间空隙342。接下来，如图3K所示的，使用传统各向同性电介质蚀刻方法使电介质层346从顶部向下凹陷。在电介质层346是氧化硅的特定实施例中，将定时HF湿法蚀刻法用于使电介质层346凹陷。在电介质层346的凹陷过程中，去除了大部分电介质层346，留下在衬底301的顶部表面303上和最底部的沟道纳米线344下的薄层，其构成底部栅极隔离物348。底部栅极隔离物348的厚度取决于使电介质层346凹陷的时间长度。在实施例中，执行凹陷足够长的时间，以使得底部栅极隔离物厚度达到足以将衬底301的顶部表面303与通过栅极电极352的容性耦合隔离的厚度。在实施例中，执行凹陷足够长的时间，以使得底部栅极隔离物厚度达到足够薄，从而使得在最底部的沟道纳米线344与底部栅极隔离物348之间的空隙足够大，以便完全包围最底部的沟道纳米线形成栅极电介质层350且围绕最底部的沟道纳米线344形成栅极电极352。在实施例中，所形成的底部栅极隔离物348的厚度足够厚，以将衬底301的顶部表面303与通过栅极电极352的容性耦合隔离，且所述厚度足够薄，以便栅极电介质层350和栅极电极352围绕最底部的沟道纳米线344。在特定实施例中，底部栅极隔离物348的厚度在约
Figure BDA0001165023410000201
之间。
参考流程图200中的步骤218及相应的图3L和3M，围绕每一条沟道纳米线343形成栅极电介质层350，并且栅极电极352形成在栅极电介质层350上并围绕每一条沟道纳米线343。图3M是图3L的相应三维横截面视图。栅极电介质层350可以由如前所述的任何公知的栅极电介质材料构成。使用诸如原子层沉积(ALD)的高保形沉积工艺形成栅极电介质层350，以便确保栅极电介质层的形成围绕每一条沟道纳米线343具有一致的厚度。在一个特定实施例中，栅极电介质层是HfO2，沉积为1-6纳米之间的厚度。均厚沉积栅极电介质层350，其还形成于ILD层340的顶部表面上。接下来，在栅极电介质层350上均厚沉积栅极电极材料，以形成栅极电极352。栅极电极352可以由如前所述的任何公知的栅极电极材料构成。使用诸如原子层沉积(ALD)的保形沉积工艺沉积栅极电极材料，以确保栅极电极352形成于栅极电介质层350上，在每一条沟道纳米线343周围和之间。随后化学机械平面化沉积在ILD层340的顶上的覆层栅极电极材料和栅极电介质层350，直至暴露出ILD层340的顶部表面，如图3L和3M所示的。根据本发明的实施例，使用流程图200中所述方法形成的合成器件300是非平面栅极全包围器件。
图4示出了根据本发明的一个实现方式的计算设备400。计算设备400容纳板402。板402可以包括多个组件，包括但不限于，处理器404和至少一个通信芯片406。处理器404物理且电耦合到板402。在一些实现方式中，至少一个通信芯片406也物理且电耦合到板402。在进一步的实现方式中，通信芯片406是处理器404的部分。
取决于其应用，计算设备400可以包括其他组件，其会或不会物理且电耦合到板402。这些其他组件包括但不限于，易失性存储器(例如，DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如，硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。
通信芯片406实现了无线通信，用于往来于计算设备400传送数据。术语“无线”及其派生词可以用于描述可以通过非固态介质借助使用调制电磁辐射传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线，尽管在一些实施例中它们可以不包含。通信芯片406可以实施多个无线标准或协议中的任意一个，包括但不限于，Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物，以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备400可以包括多个通信芯片406。例如，第一通信芯片406可以专用于近距离无线通信，例如Wi-Fi和蓝牙，第二通信芯片406可以专用于远距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备400的处理器404包括封装在处理器404内的集成电路晶片。在本发明的一些实现方式中，处理器的集成电路晶片包括诸如根据本发明的实现方式形成的非平面栅极全包围晶体管器件的一个或多个器件。术语“处理器”可以指代任何设备或设备的部分，其处理来自寄存器和/或存储器的电子数据，将该电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片406也包括封装在通信芯片406内的集成电路晶片。根据本发明的另一个实现方式，通信芯片的集成电路晶片包括诸如根据本发明的实现方式形成的非平面栅极全包围晶体管器件的一个或多个器件。
在进一步的实现方式中，容纳在计算设备400内的另一个组件可以包含集成电路晶片，其包括诸如根据本发明的实现方式形成的非平面栅极全包围晶体管器件的一个或多个器件。
在多个实现方式中，计算设备400可以是膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机。在进一步的实现方式中，计算设备400可以是处理数据的任何其他电子设备。
因而，并发明的一个或多个实施例可以包括非平面栅极全包围晶体管器件，其中，具有形成于衬底与底部沟道纳米线之间的嵌入式外延源极区和嵌入式外延漏极区或者底部栅极隔离物层之一或者二者。

Claims (14)

1.一种半导体器件，包括：
包括第一材料的半导体衬底，所述第一材料具有第一晶格常数；
位于所述半导体衬底之上的嵌入式外延源极区，所述嵌入式外延源极区包括第二材料，所述第二材料具有与所述第一晶格常数不同的第二晶格常数；
位于所述半导体衬底之上的嵌入式外延漏极区，所述嵌入式外延漏极区包括所述第二材料；
纳米线，所述纳米线被耦合至所述嵌入式外延源极区且被耦合至所述嵌入式外延漏极区，所述纳米线包括第三材料，所述第三材料具有与所述第二晶格常数相同的第三晶格常数；
栅极电介质层，所述栅极电介质层位于所述纳米线的至少一部分的周围；以及
栅极电极，所述栅极电极位于所述纳米线的至少一部分的周围，并且所述栅极电极至少通过所述栅极电介质层与所述纳米线分隔开。
2.根据权利要求1所述的器件，其中，所述第二晶格常数大于所述第一晶格常数。
3.根据权利要求1所述的器件，其中，所述第二材料与所述第三材料相同。
4.根据权利要求1所述的器件，其中，所述嵌入式外延源极区和所述嵌入式外延漏极区都具有有角度的侧壁。
5.根据权利要求1所述的器件，其中，所述嵌入式外延源极区在位于所述半导体衬底之上的第一位置处具有第一宽度，所述嵌入式外延源极区在位于所述半导体衬底之上的第二位置处具有第二宽度，所述第二位置与所述第一位置距离所述半导体衬底的距离不同，并且所述第一宽度大于所述第二宽度。
6.根据权利要求5所述的器件，其中，所述嵌入式外延源极区的所述第一宽度大于所述纳米线的最大宽度。
7.根据权利要求1所述的器件，进一步包括位于所述半导体衬底的第一部分上方的隔离区层，其中，所述半导体衬底的第二部分向上延伸超过所述隔离区层的底部表面。
8.根据权利要求7所述的器件，其中，所述半导体衬底的所述第二部分没有向上延伸到所述隔离区层的顶部表面。
9.根据权利要求7所述的器件，其中，所述纳米线的至少部分位于所述半导体衬底的所述第二部分的正上方，而不与所述半导体衬底的所述第二部分直接接触。
10.根据权利要求1所述的器件，其中，所述嵌入式外延漏极区具有侧壁，并且所述嵌入式外延漏极区的所述侧壁是[111]-刻面。
11.根据权利要求1所述的器件，其中，所述第一材料是硅锗，并且所述第二材料和所述第三材料是硅。
12.一种半导体器件，包括：
衬底，所述衬底具有顶部表面，所述顶部表面具有第一晶格常数；
嵌入式外延源极区和嵌入式外延漏极区，所述嵌入式外延源极区和所述嵌入式外延漏极区布置在所述衬底的所述顶部表面上，所述嵌入式外延源极区和所述嵌入式外延漏极区具有与所述第一晶格常数不同的第二晶格常数；
沟道纳米线，所述沟道纳米线具有与所述第一晶格常数不同的第三晶格常数，其中，所述第三晶格常数与所述第二晶格常数相同，所述沟道纳米线耦合到所述嵌入式外延源极区和所述嵌入式外延漏极区；
栅极电介质层，所述栅极电介质层布置在所述沟道纳米线的一个轴上且包围所述沟道纳米线的所述一个轴；以及
栅极电极，所述栅极电极布置在所述栅极电介质层上并围绕所述沟道纳米线的所述一个轴。
13.根据权利要求12所述的半导体器件，其中，所述外延源极区和所述外延漏极区是[111]-刻面的。
14.根据权利要求12所述的半导体器件，进一步包括底部栅极隔离物，所述底部栅极隔离物布置在所述衬底的所述顶部表面上且在所述沟道纳米线之下，其中，所述底部栅极隔离物具有的厚度足够厚，以将所述衬底的所述顶部表面与通过所述栅极电极的容性耦合隔离。
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