FR3060841B1 - Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes - Google Patents

Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes Download PDF

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FR3060841B1
FR3060841B1 FR1662532A FR1662532A FR3060841B1 FR 3060841 B1 FR3060841 B1 FR 3060841B1 FR 1662532 A FR1662532 A FR 1662532A FR 1662532 A FR1662532 A FR 1662532A FR 3060841 B1 FR3060841 B1 FR 3060841B1
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drain
source
stack
spacers
semiconductor device
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FR3060841A1 (fr
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Shay Reboh
Emmanuel Augendre
Remi Coquand
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to US15/837,217 priority patent/US10269930B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • HELECTRICITY
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/42392Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66439Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Procédé de réalisation d'un dispositif semi-conducteur (100), comportant : - réalisation d'un empilement comprenant une première portion (114) semi-conductrice cristalline destinée à former un canal et disposée sur au moins une deuxième portion pouvant être gravée sélectivement vis-à-vis de la première portion, - réalisation d'une grille factice et d'espaceurs externes (112), - gravure de l'empilement, une partie restante de l'empilement sous la grille factice et les espaceurs externes étant conservée, - réalisation de source/drain (118, 120) par épitaxie depuis la partie restante de l'empilement ; - suppression de la grille factice et de la deuxième portion, - oxydation de portions des source/drain depuis des parties des source/drain révélées par la suppression de la deuxième portion, formant des espaceurs internes (126), - réalisation d'une grille (128) isolée électriquement des source/drain par les espaceurs externes et internes.
FR1662532A 2016-12-15 2016-12-15 Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes Active FR3060841B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1662532A FR3060841B1 (fr) 2016-12-15 2016-12-15 Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes
US15/837,217 US10269930B2 (en) 2016-12-15 2017-12-11 Method for producing a semiconductor device with self-aligned internal spacers

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Application Number Priority Date Filing Date Title
FR1662532 2016-12-15
FR1662532A FR3060841B1 (fr) 2016-12-15 2016-12-15 Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes

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FR3060841B1 true FR3060841B1 (fr) 2021-02-12

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KR102381197B1 (ko) * 2017-12-08 2022-04-01 삼성전자주식회사 반도체 소자
US10424651B2 (en) * 2018-01-26 2019-09-24 International Business Machines Corporation Forming nanosheet transistor using sacrificial spacer and inner spacers
US10461194B2 (en) 2018-03-23 2019-10-29 International Business Machines Corporation Threshold voltage control using channel digital etch
CN109103108A (zh) * 2018-08-29 2018-12-28 中国科学院微电子研究所 一种半导体器件的形成方法
FR3087046B1 (fr) * 2018-10-05 2020-12-25 Commissariat Energie Atomique Structure a barreaux semi-conducteurs superposes ayant une enveloppe semi-conductrice uniforme
FR3088481B1 (fr) * 2018-11-14 2024-06-07 Commissariat Energie Atomique Procede de fabrication d’un transistor a effet de champ a jonction alignee avec des espaceurs
FR3091620B1 (fr) 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture
FR3100083B1 (fr) 2019-08-20 2021-09-10 Commissariat Energie Atomique Procédé de guérison d’une couche implantée comprenant un traitement thermique préalable à une recristallisation par recuit laser
EP3840033A1 (fr) 2019-12-17 2021-06-23 Commissariat à l'énergie atomique et aux énergies alternatives Procédé de fabrication d'un substrat rf-soi à couche de piégeage issue d'une transformation cristalline d'une couche enterrée
FR3123502B1 (fr) * 2021-05-27 2024-01-05 Commissariat Energie Atomique Procédé de fabrication d'un transistor a structure de grille enrobante
CN117693820A (zh) * 2021-09-26 2024-03-12 华为技术有限公司 环栅晶体管、其制备方法、cmos晶体管及电子设备
US20230163212A1 (en) * 2021-11-19 2023-05-25 Intel Corporation Gate-all-around transistor device with compressively strained channel layers

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202117B2 (en) * 2005-01-31 2007-04-10 Freescale Semiconductor, Inc. Method of making a planar double-gated transistor
CN104126228B (zh) * 2011-12-23 2016-12-07 英特尔公司 非平面栅极全包围器件及其制造方法
US9484447B2 (en) 2012-06-29 2016-11-01 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices
US9006829B2 (en) 2012-08-24 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Aligned gate-all-around structure
US9362397B2 (en) * 2013-09-24 2016-06-07 Samsung Electronics Co., Ltd. Semiconductor devices

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US20180175166A1 (en) 2018-06-21
US10269930B2 (en) 2019-04-23
FR3060841A1 (fr) 2018-06-22

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