FR3060840B1 - Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes - Google Patents

Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes Download PDF

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FR3060840B1
FR3060840B1 FR1662531A FR1662531A FR3060840B1 FR 3060840 B1 FR3060840 B1 FR 3060840B1 FR 1662531 A FR1662531 A FR 1662531A FR 1662531 A FR1662531 A FR 1662531A FR 3060840 B1 FR3060840 B1 FR 3060840B1
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spacers
portions
semiconductor device
self
making
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FR3060840A1 (fr
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Shay REBOH
Emmanuel Augendre
Remi COQUAND
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to US15/837,405 priority patent/US10217842B2/en
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    • H01L29/66553Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • BPERFORMING OPERATIONS; TRANSPORTING
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Procédé de réalisation d'un dispositif semi-conducteur (100), comportant les étapes suivantes : a) réalisation, sur un substrat (104), d'un empilement comprenant une première portion de semi-conducteur apte à former une zone active et disposée entre deux deuxièmes portions d'un matériau apte à être gravé sélectivement vis-à-vis du semi-conducteur de la première portion, b) réalisation, sur une partie de l'empilement, d'espaceurs externes (112) et d'une grille factice, c) gravure des deuxièmes portions telle que des parties restantes soient disposées sous la grille factice, d) oxydation partielle des parties restantes depuis des faces externes, formant des espaceurs internes (118), e) suppression de la grille factice et de parties non oxydées des parties restantes disposées sous la grille factice, f) réalisation d'une grille (128) entre les espaceurs externes et entre les espaceurs internes et recouvrant le canal.
FR1662531A 2016-12-15 2016-12-15 Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes Active FR3060840B1 (fr)

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US15/837,405 US10217842B2 (en) 2016-12-15 2017-12-11 Method for making a semiconductor device with self-aligned inner spacers

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