FR3060840B1 - Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes - Google Patents
Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes Download PDFInfo
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- FR3060840B1 FR3060840B1 FR1662531A FR1662531A FR3060840B1 FR 3060840 B1 FR3060840 B1 FR 3060840B1 FR 1662531 A FR1662531 A FR 1662531A FR 1662531 A FR1662531 A FR 1662531A FR 3060840 B1 FR3060840 B1 FR 3060840B1
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- 239000004065 semiconductor Substances 0.000 title abstract 4
- 238000000034 method Methods 0.000 title abstract 2
- 125000006850 spacer group Chemical group 0.000 abstract 4
- 238000005530 etching Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
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- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Procédé de réalisation d'un dispositif semi-conducteur (100), comportant les étapes suivantes : a) réalisation, sur un substrat (104), d'un empilement comprenant une première portion de semi-conducteur apte à former une zone active et disposée entre deux deuxièmes portions d'un matériau apte à être gravé sélectivement vis-à-vis du semi-conducteur de la première portion, b) réalisation, sur une partie de l'empilement, d'espaceurs externes (112) et d'une grille factice, c) gravure des deuxièmes portions telle que des parties restantes soient disposées sous la grille factice, d) oxydation partielle des parties restantes depuis des faces externes, formant des espaceurs internes (118), e) suppression de la grille factice et de parties non oxydées des parties restantes disposées sous la grille factice, f) réalisation d'une grille (128) entre les espaceurs externes et entre les espaceurs internes et recouvrant le canal.
Priority Applications (2)
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FR1662531A FR3060840B1 (fr) | 2016-12-15 | 2016-12-15 | Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes |
US15/837,405 US10217842B2 (en) | 2016-12-15 | 2017-12-11 | Method for making a semiconductor device with self-aligned inner spacers |
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FR1662531 | 2016-12-15 | ||
FR1662531A FR3060840B1 (fr) | 2016-12-15 | 2016-12-15 | Procede de realisation d'un dispositif semi-conducteur a espaceurs internes auto-alignes |
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FR3060840A1 FR3060840A1 (fr) | 2018-06-22 |
FR3060840B1 true FR3060840B1 (fr) | 2019-05-31 |
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2016
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US10217842B2 (en) | 2019-02-26 |
US20180175167A1 (en) | 2018-06-21 |
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