WO2017096781A1 - 具有高质量外延层的纳米线半导体器件及其制造方法 - Google Patents

具有高质量外延层的纳米线半导体器件及其制造方法 Download PDF

Info

Publication number
WO2017096781A1
WO2017096781A1 PCT/CN2016/087251 CN2016087251W WO2017096781A1 WO 2017096781 A1 WO2017096781 A1 WO 2017096781A1 CN 2016087251 W CN2016087251 W CN 2016087251W WO 2017096781 A1 WO2017096781 A1 WO 2017096781A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
nanowire
substrate
semiconductor
semiconductor device
Prior art date
Application number
PCT/CN2016/087251
Other languages
English (en)
French (fr)
Inventor
朱慧珑
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201510888321.4A external-priority patent/CN105633166B/zh
Priority claimed from CN201610440133.XA external-priority patent/CN106098776B/zh
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US16/060,399 priority Critical patent/US10978591B2/en
Publication of WO2017096781A1 publication Critical patent/WO2017096781A1/zh
Priority to US17/197,930 priority patent/US11532753B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a nanowire semiconductor device having a high quality epitaxial layer and a method of fabricating the same.
  • MOSFETs metal oxide semiconductor field effect transistors
  • a semiconductor device comprising: a substrate; at least one nanowire spaced apart from the substrate, wherein the nanowire extends in a longitudinal direction of the bend; at least one semiconductor layer, respectively wound The outer circumference of each nanowire is formed to at least partially surround the respective nanowires, and the respective semiconductor layers formed around the respective nanowires are separated from each other.
  • a semiconductor device comprising: a substrate; at least two nanowires spaced apart from the substrate, wherein the nanowires are arranged in a direction substantially perpendicular to the surface of the substrate, and Each of the nanowires extends substantially parallel to each other along a longitudinal extension of the bend, wherein at least one pair of adjacent nanowires are mirror symmetrical with respect to the crystal line between them.
  • a method of fabricating a semiconductor device comprising: forming a fin structure extending in a longitudinal extension direction of a bend on a substrate; on a substrate on which a fin structure is formed Forming a support portion; removing a portion of the fin structure to form at least one nanowire spaced apart from the substrate, the at least one nanowire being supported by the support portion; and each of the nanowires as a seed layer, respectively growing the semiconductor layer.
  • a method of fabricating a semiconductor device comprising: forming a fin structure extending in a longitudinal extension direction of a bend on a substrate; forming a support portion on a substrate on which the fin structure is formed Removing a portion of the fin structure to form at least one nanowire spaced apart from the substrate, the at least one nanowire being supported by the support portion; each nanowire as a seed layer, respectively growing a semiconductor layer; at the closest to the substrate Forming a mask layer between the semiconductor layer and the substrate and between the semiconductor layers; selectively etching each semiconductor layer with the nanowire and the mask layer as a mask, so that the semiconductor layer remains on the nanowire and the mask layer And; selectively removing the nanowires and the mask layer.
  • a semiconductor layer may be grown using a curved nanowire suspended relative to a substrate as a seed layer, which may have high mobility.
  • a suspended seed layer can relax the stress in the nanowires and the semiconductor layer, thereby helping to suppress defects in the nanowire or semiconductor layer.
  • FIGS. 1(a)-15 are schematic views schematically showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure
  • 16-17 are schematic diagrams schematically showing stages in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • 18-22 are schematic diagrams schematically showing a partial stage in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a semiconductor device having a suspended fin structure refers to a structure protruding from the surface of the substrate, including but not limited to fins in a fin field effect transistor (FinFET); the so-called “suspension” means that the fin is separated from the substrate. . Note that the spacing between the fins and the substrate can be filled with other materials (eg, an isolation layer).
  • the fins may include high mobility semiconductor materials to improve device performance.
  • the "high mobility” means that the mobility with respect to silicon (Si) is high.
  • High mobility semiconductor materials such as Ge, SiGe or III-V compound semiconductors, and the like.
  • the fin may be a semiconductor layer formed on a nanowire (eg, epitaxial) spaced apart from the substrate on the substrate.
  • nanowire means a structure in which the longitudinal extension length is much larger than the cross-sectional dimension thereof and the cross-sectional dimension is on the nanometer scale.
  • the nanowires may be fin-shaped extending in a longitudinal direction of curvature (eg, substantially "C” or "S") and suspended relative to the substrate, such as generally parallel to the surface of the substrate.
  • the semiconductor layer can be formed at least partially around the periphery of the nanowires to extend in substantially the same direction as the nanowires (and thus fins) and can then serve as fins for the device.
  • partially surrounding means that there may be a range along the longitudinal extension direction of the nanowire, within which the semiconductor layer may completely enclose the outer surface of the nanowire. That is, within this range, the semiconductor layer may form a closed pattern (for example, a rectangle, a polygon, or the like corresponding to the sectional shape of the nanowire) in a cross section perpendicular to the longitudinal extension direction of the nanowire.
  • the nanowires may be covered by the semiconductor layer in addition to the surface covered by the support portion.
  • the nanowires are relatively thin (eg, having a width/height of about 3-20 nm) and are suspended relative to the substrate. In this way, the stress in the nanowires and the semiconductor layer can be relaxed during the growth process, and thus the occurrence of defects in the nanowire or the semiconductor layer can be suppressed or avoided. trap.
  • the fin may be a portion of the semiconductor layer formed as described above on the side and/or the lower side of the nanowire.
  • the remainder of the semiconductor layer, such as portions on the left and right sides of the nanowire, and the nanowires can be removed.
  • the fin itself appears in the form of nanowires and extends in substantially the same shape as the nanowires as seed layers.
  • a portion on the side of the nanowire and a portion on the lower side of the nanowire respectively grow from the upper and lower side surfaces of the nanowire, and thus their crystal structures are relative to The center between them can be roughly mirror symmetrical.
  • the nanowires can be physically connected to the substrate via the support and thus supported by the substrate.
  • the portion of the nanowire connected to the support may extend less than the longitudinal extent of the nanowire.
  • the support portion may include a laterally extending portion extending along a surface of the substrate and a vertically extending portion extending in a direction substantially perpendicular to the surface of the substrate, wherein the vertically extending portion extends to a vertical side of the nanowire along a direction substantially perpendicular to the surface of the substrate On the wall.
  • the nanowires are physically connected to the substrate and thus supported by the substrate.
  • the vertically extending portions of the support portion may extend over the vertical sidewalls on opposite sides of the nanowire to clamp the nanowires.
  • the support portions may be provided at both ends of the nanowires.
  • an isolation layer may be formed on the substrate to electrically isolate the gate stack of the field effect transistor and the substrate.
  • the top surface of the isolation layer may be closer to the substrate than the bottom surface of the lowest semiconductor layer/nanowire facing the substrate, thereby exposing the respective semiconductor layers/nanowires.
  • the gate stack can surround the semiconductor layer/nanowire (ie, the fin of the device).
  • a plurality of devices may be formed based on the same fin (semiconductor layer/nanowire).
  • respective devices may be formed based on different portions of the fin along its longitudinal extension.
  • there may be more than one, for example two or more, gate stacks intersecting the same fin to form respective devices, respectively.
  • the gate stack may include a first gate stack and a second gate stack separated along a longitudinal extension direction of the fin.
  • the first gate stack may intersect a first portion of the fin in the longitudinal extension direction (ie, a portion of the semiconductor layer formed around the outer circumference of the first portion of the nanowire in the longitudinal extension direction or a nanowire formed thereby), and the second gate stack may be combined with the fin a second portion extending in the longitudinal direction (ie, bypassing The portion of the semiconductor layer formed by the outer circumference of the second portion of the rice noodle extending in the longitudinal direction or the nanowires formed thereby intersect.
  • the respective devices of the first gate stack and the second gate stack may be isolated from each other.
  • a dielectric layer can be formed to separate the first portion and the second portion of the nanowire as a seed layer.
  • the dielectric layer may extend in a direction intersecting the longitudinal extension of the nanowires and may further separate different portions of the semiconductor layer/nanowire grown based on the seed layer.
  • Such a semiconductor device can be produced, for example, as follows. Specifically, a fin structure having a curved (eg, substantially "C” shape or "S" shape) longitudinal extension direction may be formed on the substrate. Subsequently, a portion of the fin structure will be removed to obtain at least one nanowire separated from the substrate, which nanowires can be suspended relative to the substrate.
  • a fin structure having a curved (eg, substantially "C” shape or "S" shape) longitudinal extension direction may be formed on the substrate. Subsequently, a portion of the fin structure will be removed to obtain at least one nanowire separated from the substrate, which nanowires can be suspended relative to the substrate.
  • a support portion may be formed.
  • a support portion can be formed as follows. Specifically, a layered material (hereinafter referred to as a support layer) may be formed on the substrate on which the fin structure is formed, and the support layer is patterned to extend from the surface of the substrate to the surface of the fin structure and thus the fin structure A support that is physically connected to the substrate. The patterning of the support layer can be performed using a mask.
  • the mask extends over the fin structure beyond the fin structure in a direction perpendicular to the longitudinal extension direction of the fin structure (so that the mask can shield the portion of the support layer extending over the substrate surface on both sides of the fin structure) So that the portion can then be retained); and in the longitudinal extension of the fin structure, the mask covers only a portion of the longitudinal extent of the fin structure over the fin structure (so that the mask masks the longitudinal direction of the fin structure) Only a portion of the extent is extended so that the portion can then be connected to the support).
  • the mask may cover both end ends of the fin structure, and the resulting support portions may be correspondingly located at both end ends of the fin structure.
  • the fin structure may be divided into portions along a direction substantially perpendicular to the surface of the substrate, the portions extending along the longitudinal extension of the fin structure, respectively.
  • the nanowires can be aligned in a direction generally perpendicular to the surface of the substrate, and the nanowires extend substantially parallel to each other.
  • the nanowires are similar to a cantilever configuration with respect to the substrate, the support being similar to the anchor of the cantilever, anchoring the nanowires as cantilever to the substrate.
  • the fin structure may include a stack of sacrificial layers and nanowire material layers alternately stacked on the substrate.
  • a sacrificial layer and a layer of nanowire material may be alternately formed on a substrate, which may then be patterned into a fin structure.
  • the patterning step can be performed into the substrate so as to have protrusions at a position on the substrate corresponding to the fin structure. Then you can choose The sacrificial layer is removed.
  • the nanowire Since the nanowire is suspended so that its surface is exposed, a semiconductor layer can be grown on the surface thereof. Thus, in the case of sufficient growth, the semiconductor layer can cover all surfaces exposed by the nanowires (supported portions). The semiconductor layer can then act as a fin for the device.
  • a mask layer may be formed between the semiconductor layer closest to the substrate and the substrate and between the respective semiconductor layers.
  • the semiconductor layers can be selectively etched by using the nanowires and the mask layer as a mask such that the semiconductor layer remains between the nanowires and the mask layer.
  • the nanowires and mask layers can then be selectively removed.
  • the remaining portion of the semiconductor layer can assume the shape of a substantially nanowire and can then act as a fin for the device.
  • an isolation layer can be formed on the substrate and a gate stack intersecting the semiconductor layer can be formed on the isolation layer.
  • the top surface of the isolation layer may be lower than the lowest bottom surface of the semiconductor layer and thus expose the respective semiconductor layers.
  • the spacer layer can be obtained by depositing a dielectric such as an oxide and etching back.
  • the material of the support portion may be different from the material of the isolation layer so that the support portion is not damaged during etch back.
  • two or more gate stacks may be formed to form respective devices. Isolation can be formed between the devices as designed.
  • a dielectric layer extending in a direction intersecting the longitudinal extension direction of the nanowires may be formed on the isolation layer, the dielectric layer may divide the nanowire into the first portion and the second portion, and the semiconductor grown on the nanowire
  • the layer or nanowire is divided into a first part and a second part.
  • the gate stack can be formed to include a first gate stack that intersects the first portion of the grown semiconductor layer/nanowire and a second gate stack that intersects the second portion thereof.
  • a substrate 1001 is provided.
  • the substrate 1001 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate or the like. In the following description, a bulk Si substrate will be described as an example for convenience of explanation.
  • a sacrificial layer 1003-1, a nanowire material layer 1005-1, a sacrificial layer 1003-2, and a nanowire material layer 1005-2 are sequentially formed, for example, by epitaxial growth.
  • the sacrificial layers 1003-1, 1003-2 may comprise a different semiconductor material than the substrate 1001 and the nanowire material layers 1005-1, 1005-2, such as SiGe (the atomic percentage of Ge is, for example, about 5 to 20%).
  • the thickness of the sacrificial layer 1003-1 may be about 10 to 100 nm, and the thickness of the sacrificial layer 1003-2 may be about 10 to 50 nm (the thickness of these sacrificial layers may be according to the desired spacing between the nanowires and the substrate and adjacent The spacing between the nanowires is determined).
  • the nanowire material layers 1005-1, 1005-2 may comprise a suitable semiconductor material, such as Si, having a thickness of about 3-10 nm (the thickness of the nanowire material layer may be determined according to the height of the nanowires desired to be obtained).
  • the present disclosure is not limited to a specific number of sacrificial layers and nanowire material layers, but may include more or less sacrificial layers or nanowire material layers as long as they are alternately stacked on a substrate.
  • the nanowire material layer and the sacrificial layer (and optionally the substrate) thus formed may be patterned to form a fin structure.
  • this can be done as follows.
  • a hard mask layer can be formed on the nanowire material layer 1005-2.
  • the hard mask layer can include an oxide (eg, silicon oxide) layer 1007 and a polycrystalline Si layer 1009.
  • the oxide layer 1007 has a thickness of about 2 to 10 nm
  • the polycrystalline Si layer 1009 has a thickness of about 50 to 120 nm.
  • the hard mask is patterned into fins using a pattern transfer technique.
  • a photoresist PR patterned may be formed on the hard mask layer.
  • the photoresist PR is patterned in a strip shape extending in the bending direction, and its width (dimension in the horizontal direction in the drawing) may substantially correspond to the interval between the two fin structures.
  • Such curved shapes may be curved, arcuate, polynomial curves, combinations thereof, and the like.
  • the photoresist PR is patterned into a substantially "C" shape.
  • the polycrystalline Si layer 1009 (relative to the oxide layer 1007) is selectively etched, such as reactive ion etching (RIE), using the photoresist PR as a mask.
  • RIE reactive ion etching
  • the polycrystalline Si layer 1009 can be patterned into strips corresponding to the photoresist PR.
  • FIGS. 3(a) and 3(b) Fig. 3(a) is a plan view
  • Fig. 3(b) is a cross-sectional view taken along line AA' in Fig. 3(a)
  • the photoresist PR is removed.
  • a spacer 1011 is formed on the sidewall of the polycrystalline Si layer 1009. There are various means in the art to form side walls.
  • a layer of nitride (e.g., silicon nitride) may be substantially conformally deposited by, for example, atomic layer deposition (ALD), having a thickness of, for example, about 3 to 10 nm, and then selectively etching the deposited nitride.
  • ALD atomic layer deposition
  • the RIE is removed from its laterally extending portion such that the vertically extending portion remains to form the side wall 1011.
  • the sidewall 1011 covers the sidewall of the Si layer 1009.
  • the polycrystalline Si layer 1009 can be selectively removed (eg, by a TMAH solution).
  • the sidewalls 1011 may be present on the sidewalls of the upper and lower ends of the strip-shaped polycrystalline Si layer 1009, so that the sidewall 1011 is wound around the strip-shaped polycrystalline Si layer 1009.
  • Peripheral shape In a closed pattern.
  • the upper and lower sides of the side wall 1011 can be removed by photolithography, so that the side wall 1011 which is originally a closed pattern can be separated into two parts. Each portion corresponds to a fin structure to be formed, which in this example is two "C" strips as shown in Fig. 3(a).
  • the oxide layer 1007, the nanowire material layer 1005-2, the sacrificial layer 1003-2, the nanowire material layer 1005-1, and the sacrificial layer 1003- can be sequentially disposed.
  • 1 Perform selective etching such as RIE.
  • the pattern of the side wall 1011 is transferred to the lower layer to obtain a fin structure. Therefore, the width of the nanowire material layers 1005-1 and 1005-2 after etching (the dimension in the horizontal direction in the drawing) is substantially the same as the width of the spacer 1011 (for example, about 3 to 10 nm).
  • the substrate 1001 can be further selectively etched.
  • the substrate 1001 may have protrusions thereon.
  • the projection of the fin structure on the substrate is located substantially in the middle of the protrusion. Due to the etching characteristics, the etched sacrificial layer 1003 and the protrusions of the substrate 1001 may have a shape that gradually becomes larger from top to bottom. Thereafter, the sidewall spacers 1011 can be selectively removed (the oxide layer 1007 can be further selectively removed) as shown in FIG.
  • a fin-shaped photoresist may be directly formed on the nanowire material layer 1005-2, and the nanowire material layer, the sacrificial layer, and the substrate 1001 may be selectively etched using the photoresist as a mask to form a fin shape. structure.
  • a fin-shaped photoresist may be directly formed on the hard mask layer, the hard mask may be patterned into a fin by a photoresist, and the nanowire material layer may be selectively etched sequentially by using a fin-shaped hard mask.
  • the sacrificial layer and the substrate 1001 are formed to form a fin structure.
  • fin structures are shown. However, the present disclosure is not limited thereto, and for example, more or less fin structures may be formed. In addition, the layout of the fin structure can be designed differently depending on the device requirements.
  • a support portion may be formed.
  • oxide layer 1015 and nitride layer 1017 may be deposited in a substantially conformal manner on a substrate having a fin structure formed thereon, such as by ALD.
  • the oxide layer 1015 may have a thickness of about 1 to 10 nm
  • the nitride layer 1017 may have a thickness of about 2 to 15 nm.
  • a patterned photoresist 1019 can be formed on the structure shown in FIG.
  • the photoresist 1019 is patterned to cover the ends of the fin structures on both sides (upper and lower sides in the drawing) and extends in the horizontal direction in the drawing. It should be noted here that in the top view of FIG. 8, the appearance of the nitride layer 1017 with the fin structure on the substrate is not shown for convenience, and the same is true in the following plan view.
  • FIG. 9(a) is a plan view
  • Fig. 9(b) is a cross-sectional view taken along line AA' in Fig. 9(a)
  • Fig. 9 ( c) is a cross-sectional view taken along line A1A1' in Fig. 9(a)
  • the nitride layer 1017 is selectively removed by, for example, RIE (relative to the oxide layer 1015) using the photoresist 1019 as a mask.
  • RIE reactive vapor deposition
  • the nitride layer 1017 is left at the ends of both sides of the fin structure (upper and lower sides in FIG.
  • the nitride layer 1017 physically connects the fin structure to the substrate 1001 and thus can support the fin structure (particularly after removing the sacrificial layers 1003-1 and 1003-2 as described below). Thereafter, the photoresist 1019 can be removed.
  • a support layer of a laminate structure of an oxide layer and a nitride layer is formed, and the support layer is patterned into a support portion.
  • the support layer can include a variety of suitable dielectric materials.
  • the support layer may even comprise a semiconductor material or a conductive material.
  • FIGS. 10(a) and 10(b) correspond to the cross-sectional view in FIG. 9(b), and FIG. 10(b) corresponds to the cross-sectional view in FIG. 9(c)).
  • the oxide layer 1015 can be selectively removed by, for example, RIE, (relative to the substrate 1001 of the Si material and the nanowire material layer and the sacrificial layer of the SiGe material).
  • RIE reactive ion etching
  • the nanowires 1005-1 and 1005-2 are spaced apart from each other by the spacer 1021 and spaced apart from each other, extending substantially parallel to the substrate, and passing through the support portion 1015/ 1017 is supported by the substrate 1001.
  • the nanowires 1005-1 and 1005-2 may be arranged in a direction substantially perpendicular to the surface of the substrate (in this example, in a substantially vertical direction) and may be aligned with each other. In this example, the nanowires 1005-1 and 1005-2 extend substantially parallel to each other along substantially the same curved longitudinal direction.
  • the support portion 1015/1017 includes a laterally extending portion extending over the surface of the substrate 1001 and a vertically extending portion extending in a direction substantially perpendicular to the surface of the substrate.
  • the vertically extending portion may include a portion extending along a surface of the protrusion of the substrate 1011, a portion extending along a surface of the sacrificial layer (which has been removed), and a vertical side along the nanowires 1005-1 and 1005-2 The part of the wall that extends.
  • the support portions 1015/1017 physically connect the nanowires 1005-1 and 1005-2 to the substrate 1001 so that the nanowires 1005-1 and 1005-2 can be supported.
  • the support portion 1015/1017 may extend on vertical sidewalls on opposite sides (left and right sides of the figure) of the nanowires 1005-1, 1005-2, thereby clamping the nanowires to support the nanowires more stably .
  • the extension of the portion where the nanowires 1005-1 or 1005-2 are connected to the support portion 1015/1017 is smaller than the longitudinal extension of the nanowire.
  • the "longitudinal extension direction” means the length direction of the nanowire (the direction perpendicular to the paper surface in FIG. 11), which substantially coincides with the length direction of the channel region formed thereafter, that is, from the source region to the drain region. The direction of the zone or vice versa.
  • nanowires 1005-1 and 1005-2, relative to substrate 1001 form a configuration similar to a cantilever that is anchored to substrate 1001 by support 1015/1017.
  • the support portion includes the oxide layer 1015 in addition to the nitride layer 1017, but the present disclosure is not limited thereto.
  • the nitride layer 1017 may be formed without forming the oxide layer 1015.
  • subsequent operations can also be performed in the manner described above in connection with Figures 8-11(b).
  • the support portion may also be other dielectric materials or laminated structures.
  • the support portions are formed at the ends of the upper and lower sides of the fin structure.
  • the present disclosure is not limited thereto.
  • the support portion may be formed in the middle of the fin structure.
  • the mask 1019 (see FIG. 8) for patterning the support portion is not limited to the above shape.
  • the mask may extend beyond the fin structure over the fin structure in a direction perpendicular to the longitudinal extension of the fin structure. In this way, the mask can cover a portion of the nitride layer 1017 that extends over the surface of the substrate 1001 (outside the protrusion), which portion can then remain (acting as a base for the support).
  • the mask in the longitudinal extension direction of the fin structure, the mask may cover only a portion of the longitudinal extension of the fin structure above the fin structure. In this way, a configuration similar to a cantilever-anchoring structure can be formed.
  • FIG. 12(a) is a plan view
  • Fig. 12(b) is a cross-sectional view taken along line AA' in Fig. 12(a)
  • Fig. 12 ( c) is a cross-sectional view taken along line A1A1' in Fig. 12(a)
  • the semiconductor layer 1023 can be grown on the nanowires 1005-1 and 1005-2.
  • the semiconductor layer 1023 can be packaged High mobility materials, such as Ge, SiGe or III-V compound semiconductors such as InSb, InGaSb, InAs, GaAs, InGaAs, AlSb, InP, Group III nitride, etc., may have a thickness of about 5-15 nm.
  • a compound semiconductor such as SiGe
  • its composition for example, the atomic percentage of Ge
  • Si the lattice constants of the nanowires 1005-1 and 1005-2 (here, Si) becomes less
  • the lattice constants of the nanowires 1005-1 and 1005-2 differ greatly in order to suppress the generation of dislocations or defects.
  • This growth may be selective growth such that the semiconductor layer 1023 grows only on the surface of the nanowires 1005-1 and 1005-2 (and the substrate 1001) of the semiconductor material.
  • the growth of the semiconductor layer 1023 can be controlled such that it does not completely fill the gap 1021 between the nanowires 1005-1 and 1001 and between the nanowires 1005-1 and 1005-2. Additionally, as described below, the remaining spacing 1021 is sufficient to form a gate dielectric layer (and optionally a work function adjustment layer). Due to the suspended configuration of the nanowires 1005-1 and 1005-2, the stress in the nanowires 1005-1, 1005-2 and the semiconductor layer 1023 can be relaxed during growth.
  • the lattice constant of the semiconductor layer 1023 such as a Ge, SiGe or III-V compound semiconductor layer is generally larger than the lattice constant of silicon, and thus the nanowires 1005-1 and 1005 of silicon-
  • the length of the semiconductor layer 1023 which is 2 seed grown, will increase relative to the nanowires 1005-1 and 1005-2.
  • the center of the semiconductor layer 1023 will be shifted to the left with respect to the original center of the nanowires 1005-1 and 1005-2. This helps release stress during growth.
  • defects can be suppressed or avoided in the nanowires 1005-1, 1005-2 or the semiconductor layer 1023, which contributes to improving device performance (for example, reducing off-state leakage current and increasing on-state current).
  • the remaining surfaces of the nanowires 1005-1 and 1005-2 are covered by the semiconductor layer except for the surface covered by the support portion 1015/1017.
  • the semiconductor layer 1023 may also be grown on the surface of the substrate 1001.
  • the semiconductor layer 1023 completely encapsulates the periphery of the nanowires at the remaining longitudinal extent.
  • the semiconductor layer 1023 forms a closed pattern (rectangular in this example).
  • the closed pattern is defined by the pattern of nanowires at the cross section, and may be other shapes such as polygons.
  • the semiconductor layer 1023 thus shaped can then serve as the fin of the device.
  • a gate stack intersecting the fins may be formed and formed
  • the final semiconductor device for example, FinFET
  • An isolation layer 1025 is first formed on the semiconductor layer 1023 formed on the bottom 1001.
  • Such an isolation layer can be formed, for example, by depositing a dielectric material such as an oxide on the substrate and then performing etch back. During the etch back process, the etch back depth is controlled such that the resulting isolation layer 1025 is capable of exposing the semiconductor layer 1023 formed around each nanowire.
  • a gate stack intersecting the fins may be formed on the isolation layer 1025.
  • this can be done as follows.
  • the gate dielectric layer 1027 and the gate conductor layer 1029 may be sequentially formed.
  • the gate dielectric layer 1027 may include an oxide (eg, SiO 2 or GeO 2 ) having a thickness of about 0.3 to 2 nm, and the gate conductor layer 1029 may include polysilicon; or the gate dielectric layer 1027 may include a thickness of about 1 to 4 nm.
  • the high K gate dielectric such as HfO 2 or Al 2 O 3 , the gate conductor layer 1029 may include a metal gate conductor.
  • a function adjustment layer (not shown), such as TiN, Al, Ti, TiAlC, may be formed between the gate dielectric layer 1027 and the gate conductor layer 1029, and has a thickness of about 1 to 3 nm.
  • the gate dielectric layer 1027 may be formed to at least partially surround the outer circumference of each nanowire. Further, a material of the gate dielectric layer may be formed on the surface of the isolation layer 1025. Further, in the case of the shape success function adjustment layer, the work function adjustment layer may similarly be formed to at least partially surround the outer circumference of each gate dielectric layer. Further, a material having a work function adjusting layer may be formed on the gate dielectric layer material formed on the spacer layer 1025. In the portion covered by the support portion (see Fig. 13 (b)), the void 1021 therein is also filled with the material of the gate dielectric layer, the work function adjusting layer, and the gate conductor layer.
  • the gate dielectric layer 1027 and the gate conductor layer 1029 may be patterned by, for example, photolithography to form the gate stack G.
  • the gate stack G there are two gate stacks G that intersect the same fin structure.
  • the present disclosure is not limited thereto.
  • the layout of the gate stack G can be based on the device design.
  • a gate stack can be used as a mask for halo implantation and extension implantation.
  • a gate spacer can be formed on the sidewalls of the gate stack.
  • Source/drain (S/D) implantation can then be performed using the gate stack and the gate spacer as a mask.
  • the implanted ions may be activated by annealing to form in the semiconductor layer 1023 on both sides of the gate stack G (upper and lower sides in the drawing). Source/drain area.
  • each of the gate stack G and the fins 1023 constitute respective devices such as FinFETs. Depending on the device design, these devices can be connected or isolated.
  • An example of isolation of devices from each other is shown in FIG. Specifically, as shown in FIG. 15, a dielectric layer 1031 extending in a direction intersecting the longitudinal extension direction of the fin structure may be formed on the isolation layer 1025 to divide the nanowires 1005-1 and 1005-2 into two isolated from each other. Portion, and the semiconductor layer 1023 is divided into two parts that are isolated from each other.
  • the semiconductor layer 1023 and the nanowires 1005-1 and 1005-2 may be selectively etched by photolithography to form a gap therein. Then, a dielectric material such as an oxide is filled in the gap to form the dielectric layer 1031.
  • the semiconductor device of this embodiment is obtained.
  • the semiconductor device may include at least one nanowire (1005-1, 1005-2) spaced apart from the substrate 1001, and the nanowire is physically connected to the substrate 1001 via the support portion 1015/1017. (See Figure 11(b)).
  • a semiconductor layer 1023 is formed to serve as a fin of the device.
  • the device further includes an isolation layer 1025 and a gate stack (1027, 1029) formed on the isolation layer 1025 that intersects the fins 1023. The gate stack can at least partially surround each of the fins 1023.
  • the support portion is retained in the final device structure.
  • the support may also be selectively (at least partially) removed (eg, after forming the gate stack), the space resulting from its removal being subsequently filled, for example, by other dielectric layers.
  • the support portions are formed at both end portions of the nanowires, and both ends of the curved fin structure can be fixed, which is particularly advantageous for the curved fin structure.
  • the present disclosure is not limited thereto, and a support portion may be formed at other portions of the first semiconductor layer in addition to or instead of the both end portions.
  • a substantially "C” shaped curved fin structure is formed, but the present disclosure is not limited thereto, and various curved shapes such as an arc shape, an arc shape, a polynomial curve, and the like, or a combination thereof may be formed.
  • the photoresist PR may be patterned into a substantially "S" shape instead of a substantially "C” shape.
  • Other operations can be performed as described above.
  • Layer 1023 is shown in FIG.
  • the length of the semiconductor layer 1023 can likewise be made larger relative to the first semiconductor layer 1005, as described above.
  • the center of the semiconductor layer 1023 will be offset with respect to the original center of the nanowires 1005-1 and 1005-2. This helps release stress during growth. More specifically, the center may be offset toward the convex side of the curved shape (the upper half of the "S" shape is shifted to the left side, and the lower half of the "S” shape is shifted to the right side).
  • a gate stack intersecting the "S" shaped fins 1023 can be formed in the manner described above.
  • FIGS. 18-22 are schematic diagrams schematically showing a partial stage in a process of fabricating a semiconductor device in accordance with another embodiment of the present disclosure.
  • this embodiment differs between this embodiment and the above embodiment will be mainly described.
  • the nanowires 1005-1 and 1005-2 may be formed on the substrate 1001, and the semiconductor layer 1023 may be grown with the nanowire as a seed, as described above in connection with Figs. 1-12(c).
  • the surface of the substrate 1001 may be a (111) crystal plane or a (110) crystal plane.
  • the uppermost nanowire material layer 1005-2 can be relatively thick, for example about 3-20 nm, as this layer can then be used as a mask.
  • the surface of the substrate 1001 may be a (111) crystal plane or a (110) crystal plane
  • the upper and lower surfaces of the nanowires 1005-1 and 1005-2 may also be (111) crystals.
  • the semiconductor layer having the lowermost isolation layer is not completely removed.
  • These remaining portions of the isolation layer 1025 can be realized, for example, by undercut in etching, and can then be used as a mask layer. The amount of etching can be controlled such that the width of the mask layer can be substantially the same as the width of the nanowires 1005-1, 1005-2.
  • an isolation layer may be formed as described in FIGS. 13(a) and 13(b), and then a dielectric layer (eg, a nitride layer) may be additionally formed on the isolation layer.
  • a dielectric layer eg, a nitride layer
  • the RIE semiconductor layer 1023 may be selectively etched using the nanowires and the mask layer as a mask.
  • the semiconductor layer 1023 can remain between the nanowires and the mask layer.
  • these remaining portions 1023-1, 1023-2, and 2013-3 of the semiconductor layer 1023 can also assume the shape of the nanowires.
  • the nanowires 1023-1 and 1023-2 obtained from the same semiconductor layer 1023 they can The mirror line is symmetric with respect to the center line between them.
  • the nanowires 1005-1, 1005-2 can be selectively removed by selective etching such as RIE, and as shown in FIG. 21, the mask layer can be selectively removed by selective etching such as RIE. 1025 (eg, wet etching) to obtain suspended nanowires 1023-1, 1023-2, and 2013-3. These nanowires are supported by the support at the ends or the rest, as described above.
  • selective etching such as RIE
  • the mask layer can be selectively removed by selective etching such as RIE.
  • 1025 eg, wet etching
  • nanowires 1023-1, 1023-2, and 2013-3 can act as fins for the device. Fin-based device fabrication can be performed as described above and will not be described herein.
  • the semiconductor device of this embodiment may include a plurality of nanowires (1023-1, 1023-2, 2013-3) spaced apart from the substrate 1001. These nanowires can include high mobility materials to act as fins for the device.
  • the device further includes an isolation layer 1025 and a gate stack (1027, 1029) formed on the isolation layer 1025 that intersects the fins 1023. The gate stack can at least partially surround each of the fins 1023.
  • the FinFET is taken as an example, but the present disclosure is not limited thereto.
  • the technology of the present disclosure can be applied to various semiconductor devices, particularly semiconductor devices that require high mobility materials such as Ge, SiGe, III-V compound semiconductor materials, such as various optoelectronic devices such as photodiodes, laser diodes (LD). )Wait.
  • a pn junction can be formed by doping the epitaxially grown semiconductor layer/nanowire on the seed layer to form a diode.
  • a pn junction can be formed by doping the epitaxially grown semiconductor layer/nanowire on the seed layer to form a diode.
  • a semiconductor device can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (eg, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and thereby an electronic device can be constructed. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
  • Such electronic devices are, for example, smart phones, tablet computers (PCs), personal digital assistants (PDAs), and the like.
  • a method of fabricating a chip system is also provided.
  • the method can include the above method of fabricating a semiconductor device.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated in accordance with the methods of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种具有高质量外延层的纳米线半导体器件及其制造方法。半导体器件可以包括：衬底（1001）；与衬底（1001）相隔开的至少一条纳米线（1005-1、1005-2），其中该纳米线（1005-1、1005-2）沿弯曲的纵向延伸方向延伸；至少一个半导体层（1023），分别绕各纳米线（1005-1、1005-2）外周形成以至少部分环绕相应纳米线（1005-1、1005-2），且绕各纳米线（1005-1、1005-2）形成的各半导体层（1023）彼此分离。

Description

具有高质量外延层的纳米线半导体器件及其制造方法
相关申请的引用
本申请要求于2016年6月17日递交的题为“具有高质量外延层的纳米线半导体器件及其制造方法”的中国专利申请201610440133.X的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及一种具有高质量外延层的纳米线半导体器件及其制造方法。
背景技术
随着半导体器件的发展，期望以迁移率高于硅(Si)的半导体材料来制作高性能半导体器件如金属氧化物半导体场效应晶体管(MOSFET)。但是，难以形成高质量的高迁移率半导体材料。
发明内容
本公开的目的至少部分地在于提供一种具有高质量外延层的半导体器件及其制造方法。
根据本公开的一个方面，提供了一种半导体器件，包括：衬底；与衬底相隔开的至少一条纳米线，其中该纳米线沿弯曲的纵向延伸方向延伸；至少一个半导体层，分别绕各纳米线外周形成以至少部分环绕相应纳米线，且绕各纳米线形成的各半导体层彼此分离。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；与衬底相隔开的至少两条纳米线，其中，各纳米线沿大致垂直于衬底表面的方向排列，且各纳米线彼此间隔开沿弯曲的纵向延伸方向大致平行延伸，其中至少一对相邻的纳米线相对于它们之间的中线在晶体结构上是镜像对称的。
根据本公开的再一方面，提供了一种制造半导体器件的方法，包括：在衬底上形成沿弯曲的纵向延伸方向延伸的鳍状结构；在形成有鳍状结构的衬底上 形成支撑部；去除鳍状结构的一部分，以形成与衬底隔开的至少一条纳米线，该至少一条纳米线由支撑部支撑；以及以各纳米线为种子层，分别生长半导体层。
根据本公开的又一方面，提供了一种制造半导体器件的方法，包括：在衬底上形成沿弯曲的纵向延伸方向延伸的鳍状结构；在形成有鳍状结构的衬底上形成支撑部；去除鳍状结构的一部分，以形成与衬底隔开的至少一条纳米线，该至少一条纳米线由支撑部支撑；以各纳米线为种子层，分别生长半导体层；在最靠近衬底的半导体层与衬底之间以及在各半导体层之间，形成掩模层；以纳米线和掩模层为掩模，选择性刻蚀各半导体层，使得半导体层留于纳米线与掩模层之间；以及选择性去除纳米线和掩模层。
根据本公开的实施例，可以利用相对于衬底悬置的弯曲纳米线作为种子层，来生长半导体层，半导体层可以具有高迁移率。这种悬置种子层可以使纳米线和半导体层中的应力弛豫，从而有助于抑制纳米线或半导体层中的缺陷。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1(a)-15是示意性示出了根据本公开实施例的制造半导体器件流程的示意图；
图16-17是示意性示出了根据本公开另一实施例的制造半导体器件流程中部分阶段的示意图；
图18-22是示意性示出了根据本公开另一实施例的制造半导体器件流程中部分阶段的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比 例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种具有悬置鳍结构的半导体器件。在此，所谓“鳍结构”，是指相对于衬底表面突出的构造，包括但不限于鳍式场效应晶体管(FinFET)中的鳍；所谓“悬置”，是指鳍与衬底相分离。注意，鳍与衬底之间的间隔可以被其他材料(例如，隔离层)填充。鳍可以包括高迁移率半导体材料，以改善器件性能。在此，所谓的“高迁移率”是指相对于硅(Si)的迁移率要高。高迁移率半导体材料例如Ge、SiGe或III-V族化合物半导体等。
鳍可以是在衬底上与衬底隔开的纳米线上(例如，外延)形成的半导体层。在此，所谓“纳米线”是指呈线状，即其纵向延伸长度远大于其截面尺度，且截面尺度在纳米级别的结构。纳米线可以呈沿弯曲(例如，大致“C”形或“S”形)纵向延伸方向延伸的鳍状，且相对于衬底悬置，例如大致平行于衬底的表面延伸。于是，半导体层可以至少部分地环绕纳米线的外周形成，从而与纳米线沿大致相同的方向延伸(因此呈鳍状)且随后可以用作器件的鳍。在此，所谓“部分地环绕”，是指沿纳米线的纵向延伸方向可以存在一范围，在该范围内，半导体层可以完全包封纳米线的外表面。也即，在该范围内，在与纳米线的纵向延伸方向垂直的截面上，半导体层可以形成闭合图案(例如，与纳米线的截面形状相对应的矩形、多边形等)。当然，纳米线除了被支撑部覆盖的表面之外，其余表面也可以被半导体层覆盖。纳米线相对较细(例如，宽度/高度为约3～20nm)，且相对于衬底悬置。这样，在生长过程中纳米线和半导体层中的应力可以得以弛豫，且因此可以抑制或避免在纳米线或半导体层中产生缺 陷。
或者，鳍可以是如上形成的半导体层位于纳米线上侧和/或下侧的部分。半导体层的其余部分例如位于纳米线左侧和右侧的部分以及纳米线可以去除。这样，鳍本身呈现纳米线的形式，且与作为种子层的纳米线大致呈相同形状延伸。对于以同一纳米线为种子生长的半导体层，其位于该纳米线上侧的部分和位于该纳米线下侧的部分分别从纳米线的上、下侧表面开始生长，因此它们的晶体结构相对于它们之间的中心可以大致镜像对称。
纳米线可以经支撑部物理连接到衬底并因此由衬底支撑。在纳米线的纵向延伸方向上，纳米线与支撑部相连接的部分的延伸范围可以小于纳米线的纵向延伸长度。这样，当仅观察纳米线、衬底和支撑部之间的位置关系(不考虑其他层结构)时，纳米线类似于一种悬梁构造，支撑部类似于悬梁的锚定结构(anchor)。
支撑部可以包括沿衬底表面延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分，其中竖直延伸部分延伸至纳米线沿大致垂直于衬底表面的竖直侧壁上。这样，通过该支撑部，将纳米线物理连接到衬底上，并因此由衬底支撑。支撑部的竖直延伸部分可以在纳米线的相对两侧的竖直侧壁上延伸，从而夹持纳米线。
支撑部可以设于纳米线的两侧端部。
对于形成场效应晶体管的情形，衬底上可以形成有隔离层，用以电隔离场效应晶体管的栅堆叠和衬底。隔离层的顶面可以比最低的半导体层/纳米线面向衬底的底面要靠近衬底，从而露出各半导体层/纳米线。这样，栅堆叠可以环绕半导体层/纳米线(即器件的鳍)。
根据实施例，基于同一鳍(半导体层/纳米线)可以形成多个器件。例如，可以基于该鳍沿其纵向延伸方向的不同部分，分别形成相应的器件。在场效应晶体管的情况下，与同一鳍相交的栅堆叠可以多于一个，例如两个或更多，以分别形成相应的器件。例如，栅堆叠可以包括沿鳍的纵向延伸方向分开的第一栅堆叠和第二栅堆叠。第一栅堆叠可以与鳍沿纵向延伸方向的第一部分(即，绕纳米线沿纵向延伸方向的第一部分外周形成的半导体层部分或者由此形成的纳米线)相交，第二栅堆叠可以与鳍沿纵向延伸方向的第二部分(即，绕纳 米线沿纵向延伸方向的第二部分外周形成的半导体层部分或由此形成的纳米线)相交。第一栅堆叠和第二栅堆叠各自对应的器件可以彼此隔离。例如，可以形成有电介质层，以将作为种子层的纳米线的第一部分和第二部分隔开。该电介质层可以沿与纳米线的纵向延伸方向相交的方向延伸，并可以进一步将基于种子层生长的半导体层/纳米线的不同部分隔开。
这种半导体器件例如可以如下制作。具体地，可以在衬底上形成具有弯曲(例如，大致“C”形或“S”形)纵向延伸方向的鳍状结构。随后，将去除该鳍状结构的一部分以得到与衬底分离的至少一条纳米线，这些纳米线可以相对于衬底悬置。
为了支撑随后将悬置的纳米线，可以形成支撑部。这种支撑部可以如下形成。具体地，可以在形成有鳍状结构的衬底上形成层状材料(以下称作支撑层)，并将该支撑层构图为从衬底表面延伸至鳍状结构的表面并因此将鳍状结构与衬底在物理上连接的支撑部。支撑层的构图可以利用掩模进行。在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方延伸超出鳍状结构的范围(这样，掩模可以遮蔽支撑层在鳍状结构两侧的衬底表面上延伸的部分，从而该部分随后可以得以保留)；而在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方覆盖鳍状结构的纵向延伸长度的仅一部分(这样，掩模遮蔽鳍状结构的纵向延伸范围的仅一部分，从而该部分随后可以与支撑部相连)。掩模可以覆盖鳍状结构的两侧端部，得到的支撑部可以相应地位于鳍状结构的两侧端部。
之后，可以去除鳍状结构的一部分，以得到纳米线。例如，鳍状结构可以沿大致垂直于衬底表面的方向分为若干部分，这些部分分别沿着鳍状结构的纵向延伸方向延伸。去除其中一些部分并保留另外的部分，可以得到一条或多条纳米线。因而，这些纳米线可以沿大致垂直于衬底表面的方向排列，且各纳米线彼此间隔开大致平行延伸。这样，纳米线相对于衬底类似于悬梁构造，支撑部类似于悬梁的锚定结构(anchor)，将作为悬梁的纳米线锚定至衬底。
为了便于去除鳍状结构的一部分，鳍状结构可以包括在衬底上形成的牺牲层和纳米线材料层交替叠置的叠层。例如，可以在衬底上交替形成牺牲层和纳米线材料层，然后可以将它们构图为鳍状结构。在该构图步骤可以进行到衬底中，从而在衬底上与鳍状结构相对应的位置处可以具有突起。随后，可以选择 性去除牺牲层。
由于纳米线悬置从而其表面露出，可以在其表面上生长半导体层。于是，在充分生长的情况下，半导体层可以覆盖纳米线(被支撑部)露出的所有表面。半导体层随后可以充当器件的鳍。
或者，还可以在最靠近衬底的半导体层与衬底之间以及在各半导体层之间，形成掩模层。于是，可以纳米线和掩模层为掩模，选择性刻蚀各半导体层，使得半导体层留于纳米线与掩模层之间。然后，可以选择性去除纳米线和掩模层。留下的半导体层部分可以呈现大致纳米线的形状，且随后可以充当器件的鳍。
以鳍为基础，可以有多种方式来完成器件的制造。例如，可以在衬底上形成隔离层，并在隔离层上形成与半导体层相交的栅堆叠。隔离层的顶面可以低于半导体层最低的底面，并因此露出各半导体层。隔离层可以通过淀积电介质如氧化物并回蚀来得到。支撑部的材料可以不同于隔离层的材料，这样在回蚀时不会破坏支撑部。
此外，在形成栅堆叠时，如上所述，针对同一鳍，可以形成与之相交的两个或更多栅堆叠，以分别形成相应的器件。可以在各器件之间按设计需要形成隔离。例如，可以在隔离层上形成沿与纳米线的纵向延伸方向相交的方向延伸的电介质层，该电介质层可以将纳米线分为第一部分和第二部分，并可以将该纳米线上生长的半导体层或纳米线分为第一部分和第二部分。栅堆叠可以形成为包括与生长的半导体层/纳米线的第一部分相交的第一栅堆叠以及与其第二部分相交的第二栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1(a)和1(b)(图1(a)是俯视图，图1(b)是沿图1(a)中AA′线的截面图)所示，提供衬底1001。该衬底1001可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001上，例如通过外延生长，依次形成牺牲层1003-1、纳米线材料层1005-1、牺牲层1003-2和纳米线材料层1005-2。牺牲层1003-1、1003-2可以包括与衬底1001和纳米线材料层1005-1、1005-2不同的半导体材料，如 SiGe(Ge的原子百分比例如为约5～20％)。牺牲层1003-1的厚度可以为约10～100nm，牺牲层1003-2的厚度可以为约10～50nm(这些牺牲层的厚度可以根据希望获得的纳米线与衬底之间的间距以及相邻纳米线之间的间距来确定)。纳米线材料层1005-1、1005-2可以包括合适的半导体材料，例如Si，厚度为约3～10nm(纳米线材料层的厚度可以根据希望获得的纳米线的高度来确定)。当然，本公开不限于牺牲层和纳米线材料层的具体数目，而是可以包括更多或更少的牺牲层或纳米线材料层，只要它们交替叠置在衬底上。
随后，可以对如此形成的纳米线材料层和牺牲层(可选地，还有衬底)进行构图，以形成鳍状结构。例如，这可以如下进行。
具体地，可以在纳米线材料层1005-2上形成硬掩模层。在该示例中，硬掩膜层可以包括氧化物(例如，氧化硅)层1007和多晶Si层1009。例如，氧化物层1007的厚度为约2～10nm，多晶Si层1009的厚度为约50～120nm。在该示例中，利用图形转移技术，来将硬掩膜构图为鳍状。为此，可以在硬掩膜层上形成构图(例如，通过曝光、显影)的光刻胶PR。在此，光刻胶PR被构图沿弯曲方向延伸的条状，且其宽度(图中水平方向上的维度)可以大致对应于两个鳍状结构之间的间距。这种弯曲形状可以是弧形、弓形、多项式曲线或其组合等。在该示例中，光刻胶PR被构图为大致呈“C”形。
接着，如图2所示，以该光刻胶PR为掩模，对多晶Si层1009(相对于氧化层1007)进行选择性刻蚀如反应离子刻蚀(RIE)。这样，可以将多晶Si层1009构图为与光刻胶PR相对应的条状。接着，如图3(a)和3(b)(图3(a)是俯视图，图3(b)是沿图3(a)中AA′线的截面图)所示，去除光刻胶PR，并在多晶Si层1009的侧壁上形成侧墙(spacer)1011。本领域存在多种手段来形成侧墙。例如，可以通过如原子层淀积(ALD)大致共形淀积一层氮化物(例如，氮化硅)，厚度例如为约3～10nm，然后对淀积的氮化物进行选择性刻蚀如RIE，去除其横向延伸部分，使得竖直延伸部分保留，以形成侧墙1011。侧墙1011覆盖Si层1009的侧壁。之后，如图4(对应于图3(b)中的截面图)所示，可以选择性去除多晶Si层1009(例如，通过TMAH溶液)。
注意，尽管图3(a)中未示出，但是在条状多晶Si层1009的上下两端的侧壁上，也可以存在侧墙1011，从而侧墙1011绕条状多晶Si层1009的外周形 成封闭图案。例如可以通过光刻，将侧墙1011上下两侧的部分去除，从而可以将原本为封闭图案的侧墙1011分离为两部分。每一部分对应于将要形成的鳍状结构，在该示例中为如图3(a)所示的两个“C”形条状。
然后，如图5所示，以侧墙1011为掩模，可以依次对氧化物层1007、纳米线材料层1005-2、牺牲层1003-2、纳米线材料层1005-1和牺牲层1003-1进行选择性刻蚀如RIE。这样，将侧墙1011的图案转移到下方的层中，得到鳍状结构。因此，刻蚀后纳米线材料层1005-1和1005-2的宽度(图中水平方向的维度)与侧墙1011的宽度大致相同(例如，约3～10nm)。在此，还可以进一步选择性刻蚀衬底1001。因此，在与鳍状结构相对应的位置处，衬底1001上可以具有突起。鳍状结构在衬底上的投影大致位于该突起的中部。由于刻蚀的特性，刻蚀后的牺牲层1003以及衬底1001的突起可以呈从上至下逐渐变大的形状。之后，可以选择性去除侧墙1011(还可以进一步选择性去除氧化物层1007)，如图6所示。
尽管在以上利用图形转移技术来形成鳍状结构，但是本公开不限于此。例如，可以直接在纳米线材料层1005-2上形成鳍状的光刻胶，并以光刻胶为掩模，选择性刻蚀纳米线材料层、牺牲层和衬底1001，以形成鳍状结构。或者，也可以在硬掩膜层上直接形成鳍状的光刻胶，利用光刻胶将硬掩膜构图为鳍状，并利用鳍状的硬掩膜依次选择性刻蚀纳米线材料层、牺牲层和衬底1001，以形成鳍状结构。
在此，示出了两个鳍状结构。但是，本公开不限于此，例如可以形成更多或更少的鳍状结构。另外，鳍状结构的布局可以根据器件需要不同地设计。
在形成鳍状结构之后，可以形成支撑部。例如，如图7所示，可以在形成有鳍状结构的衬底上，例如通过ALD，以大致共形的方式，淀积氧化物层1015和氮化物层1017。氧化物层1015的厚度可以为约1～10nm，氮化物层1017的厚度可以为约2～15nm。之后，如图8中的俯视图所示，可以在图7所示的结构上形成构图的光刻胶1019。该光刻胶1019被构图为覆盖鳍状结构两侧(图中上下两侧)的端部，并沿图中的水平方向延伸。这里需要指出的是，在图8的俯视图中，仅为方便起见，并未示出氮化物层1017随衬底上鳍状结构而起伏的形貌，以下俯视图中同样如此。
随后，如图9(a)、9(b)和9(c)(图9(a)是俯视图，图9(b)是沿图9(a)中AA′线的截面图，图9(c)是沿图9(a)中A1A1′线的截面图)所示，以光刻胶1019为掩模，例如通过RIE(相对于氧化物层1015)选择性去除氮化物层1017。这样，如图9(c)所示，氮化物层1017留在鳍状结构两侧(图9(a)中上下两侧)的端部，并延伸到衬底1001的表面上。这样，氮化物层1017将鳍状结构与衬底1001在物理上连接，并因此可以支撑鳍状结构(特别是在如下所述去除牺牲层1003-1和1003-2之后)。之后，可以去除光刻胶1019。
在该实施例中，形成了氧化物层和氮化物层的叠层结构的支撑层，并将该支撑层构图为支撑部。但是，本公开不限于此。支撑层可以包括各种合适的电介质材料。在随后去除支撑部的实施例中，支撑层甚至还可以包括半导体材料或导电材料。
在此需要指出的是，仅为了图示方便起见，图9(c)所示的截面图与图9(a)所示的俯视图在位置上有偏移(特别是图9(c)中两个鳍状结构的位置)。以下相应截面图中同样如此。
之后，如图10(a)和10(b)(图10(a)对应于图9(b)中的截面图，图10(b)对应于图9(c)中的截面图)所示，可以通过例如RIE，(相对于Si材料的衬底1001和纳米线材料层以及SiGe材料的牺牲层)，选择性去除氧化物层1015。如图10(a)所示，鳍状结构的中部被完全露出；此外，如图10(b)所示，在鳍状结构的两侧端部处，氧化物层1015被氮化物层1017覆盖，并可以得以保留。然后，如图11(a)和11(b)(分别对应于图10(a)和10(b)的截面图)所示，可以通过例如湿法腐蚀，(相对于Si材料的衬底1001和纳米线材料层1005-1、1005-2)选择性去除牺牲层1003-1和1003-2。这样，在纳米线材料层1005-1和衬底1001之间以及在纳米线材料层1005-1和1005-2之间形成间隔1021。由此，纳米线材料层1005-1和1005-2分别形成了纳米线结构。
如图11(a)和11(b)所示，纳米线1005-1和1005-2通过间隔1021与衬底1001隔开且彼此间隔开，大致平行于衬底延伸，并经支撑部1015/1017而被衬底1001支撑。纳米线1005-1和1005-2可以沿大致垂直于衬底表面的方向(在该示例中，沿大致竖直的方向)排列，且可以彼此对准。在该示例中，纳米线1005-1和1005-2彼此大致平行沿着大致相同的弯曲纵向方向延伸。
支撑部1015/1017包括在衬底1001的表面上延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分。在该示例中，竖直延伸部分可以包括沿衬底1011的突起的表面延伸的部分、沿牺牲层(已经去除)的表面延伸的部分以及沿纳米线1005-1和1005-2的竖直侧壁延伸的部分。这样，支撑部1015/1017将纳米线1005-1和1005-2物理连接到衬底1001，从而可以支撑纳米线1005-1和1005-2。支撑部1015/1017可以在纳米线1005-1、1005-2的相对两侧(图中左右两侧)的竖直侧壁上延伸，从而夹持各纳米线，以便更为稳定地支撑纳米线。在纳米线1005-1或1005-2的纵向延伸方向上，纳米线1005-1或1005-2与支撑部1015/1017相连接部分的延伸范围小于该纳米线的纵向延伸长度。在此，所谓“纵向延伸方向”是指纳米线的长度方向(图11中垂直于纸面的方向)，与之后形成的沟道区的长度方向基本上一致，也即，从源区到漏区的方向或者反之亦然。这样，纳米线1005-1和1005-2相对于衬底1001，形成类似于悬梁的构造，该悬梁通过支撑部1015/1017锚定到衬底1001。
在以上示例中，支撑部除了氮化物层1017之外，还包括氧化物层1015，但是本公开不限于此。例如，在以上结合图7描述的操作中，可以不形成氧化物层1015，而直接形成氮化物层1017。这样，同样可以按以上结合图8-11(b)描述的方式进行后继操作。当然，支撑部也可以是其他电介质材料或叠层结构。
此外，在以上示例中，支撑部形成于鳍状结构上下两侧的端部。但是本公开不限于此。例如，支撑部可以形成于鳍状结构的中部。
另外，用来构图支撑部的掩模1019(参见图8)不限于上述形状。一般地，在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方可以延伸超出鳍状结构的范围。这样，掩模可以覆盖氮化物层1017在衬底1001(突起之外的)表面上延伸的部分，这部分随后可以保留(充当支撑部的底座)。另一方面，在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方可以覆盖鳍状结构的纵向延伸长度的仅一部分。这样，可以形成类似悬梁-锚定结构的配置。
然后，如图12(a)、12(b)和12(c)(图12(a)是俯视图，图12(b)是沿图12(a)中AA′线的截面图，图12(c)是沿图12(a)中A1A1′线的截面图)所示，可以在纳米线1005-1和1005-2上生长半导体层1023。在此，半导体层1023可以包 括高迁移率材料，例如Ge、SiGe或III-V族化合物半导体如InSb、InGaSb、InAs、GaAs、InGaAs、AlSb、InP、三族氮化物等，厚度可以为约5～15nm。在化合物半导体如SiGe的情况下，其成分(例如，Ge原子百分比)可以渐变，使得例如从与纳米线1005-1和1005-2(在此，Si)的晶格常数相差较少变为与纳米线1005-1和1005-2的晶格常数相差较大，以便抑制位错或缺陷的生成。
这种生长可以是选择性生长，从而半导体层1023只在半导体材料的纳米线1005-1和1005-2(以及衬底1001)的表面上生长。可以控制半导体层1023的生长，使得其没有完全填满纳米线1005-1与衬底1001之间以及纳米线1005-1与1005-2之间的间隔1021。另外，如下所述，剩下的间隔1021中足以形成栅介质层(以及可选地功函数调节层)。由于纳米线1005-1和1005-2的悬置构造，在生长过程中纳米线1005-1、1005-2和半导体层1023中的应力可以得以弛豫。
此外，如图12(a)所示，半导体层1023如Ge、SiGe或III-V族化合物半导体层的晶格常数通常大于硅的晶格常数，因此以硅的纳米线1005-1和1005-2为种子生长的半导体层1023的长度相对于纳米线1005-1和1005-2将增大。于是，如图中箭头所示，半导体层1023的中心相对于纳米线1005-1和1005-2原本的中心将向左侧偏移。这有助于在生长过程中释放应力。
这样，可以抑制或避免纳米线1005-1、1005-2或半导体层1023中产生缺陷，这有助于改善器件性能(例如，降低关态漏电流以及提升开态电流)。
在该示例中，除了被支撑部1015/1017覆盖的表面之外，纳米线1005-1和1005-2的其余表面均被半导体层覆盖。当然，衬底1001的表面上也可以生长有半导体层1023。
在该示例中，沿纳米线的纵向延伸方向，除了支撑部所占据的纵向延伸范围之外，在其余纵向延伸范围处，半导体层1023完全包封纳米线的外周。这样，在与纳米线的纵向延伸方向垂直的截面(即，图12(b)所示的截面)上，半导体层1023形成闭合图案(该示例中为矩形)。当然，该闭合图案由纳米线在该截面处的图案所定，可以为其他形状例如多边形。
如此形状的半导体层1023随后可以充当器件的鳍。
在通过上述处理形成鳍1023之后，可以形成与鳍相交的栅堆叠，并形成 最终的半导体器件(例如，FinFET)。
为了隔离栅堆叠和衬底，如图13(a)和13(b)(分别对应于图12(b)和12(c)的截面图)在衬底1001上(在该示例中，在衬底1001上形成的半导体层1023上)首先形成隔离层1025。这种隔离层例如可以通过在衬底上淀积电介质材料如氧化物，且然后进行回蚀来形成。在回蚀过程中，控制回蚀深度，使得得到的隔离层1025能够露出绕各纳米线形成的半导体层1023。
随后，可以在隔离层1025上形成与鳍相交的栅堆叠。例如，这可以如下进行。具体地，如图14(对应于图13(a)所示的截面图)所示，可以依次形成栅介质层1027和栅导体层1029。例如，栅介质层1027可以包括厚度为约0.3～2nm的氧化物(例如，SiO2或GeO2)，栅导体层1029可以包括多晶硅；或者，栅介质层1027可以包括厚度为约1～4nm的高K栅介质如HfO2或Al2O3，栅导体层1029可以包括金属栅导体。在高K栅介质/金属栅导体的情况下，在栅介质层1027和栅导体层1029之间还可以形成功函数调节层(未示出)，例如TiN、Al、Ti、TiAlC，厚度为约1～3nm。
由于纳米线1005-1和1005-2的悬置状态，栅介质层1027可以形成为至少部分环绕各纳米线的外周。而且，在隔离层1025的表面上，也可以形成有栅介质层的材料。此外，在形成功函数调节层的情况下，功函数调节层类似地可以形成为至少部分环绕各栅介质层的外周。而且，在隔离层1025上形成的栅介质层材料上，也可以形成有功函数调节层的材料。在被支撑部覆盖的部分(参见图13(b))，其中的空隙1021也会被栅介质层、功函数调节层和栅导体层的材料填充。
之后，如图15中的俯视图所示，可以通过例如光刻，对栅介质层1027和栅导体层1029进行构图，以形成栅堆叠G。在此，有两个栅堆叠G与同一鳍状结构相交。但是，本公开不限于此。例如，可以仅有一个或者有三个或更多栅堆叠与同一鳍状结构相交。栅堆叠G的布局可以根据器件设计而定。
在形成栅堆叠之后，例如可以栅堆叠为掩模，进行晕图(halo)注入和延伸区(extension)注入。接下来，可以在栅堆叠的侧壁上形成栅侧墙。然后，可以栅堆叠及栅侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以栅堆叠G两侧(图中上下两侧)在半导体层1023中形成 源/漏区。
本领域技术人员知道多种方式来以鳍为基础制作器件，在此对于形成鳍之后的工艺不再赘述。
各栅堆叠G与鳍1023的相应部分构成相应的器件如FinFET。根据器件设计，这些器件可以相连接或者相隔离。图15中示出了器件之间彼此隔离的示例。具体地，如图15所示，可以在隔离层1025上形成沿与鳍状结构的纵向延伸方向相交的方向延伸的电介质层1031，以便将纳米线1005-1和1005-2分成彼此隔离的两部分，并将半导体层1023分成彼此隔离的两部分。具体地，可以通过光刻，对半导体层1023及纳米线1005-1和1005-2进行选择性刻蚀，从而在其中形成间隙。然后，向间隙中填充电介质材料如氧化物，来形成电介质层1031。
这样，就得到了该实施例的半导体器件。如图14和15所示，该半导体器件可以包括与衬底1001相隔开的至少一条纳米线(1005-1，1005-2)，纳米线经支撑部1015/1017而物理连接到衬底1001(参见图11(b))。绕各纳米线的外周，形成有半导体层1023，充当该器件的鳍。此外，该器件还包括隔离层1025以及在隔离层1025上形成的与鳍1023相交的栅堆叠(1027、1029)。栅堆叠可以至少部分环绕各鳍1023。
在该实施例中，在最终的器件结构中，保留了支撑部。但是，本公开不限于此。支撑部也可以被选择性(至少部分)去除(例如，在形成栅堆叠之后)，其去除而导致的空间随后例如可以被其他电介质层填充。
在以上实施例中，在纳米线的两侧端部形成了支撑部，并可以将弯曲鳍状结构的两端固定，这对于弯曲的鳍状结构特别有利。但是本公开不限于此，在两侧端部之外或者代替两侧端部，也可以在第一半导体层的其他部位处形成支撑部。
在以上示例中，形成了大致“C”形的弯曲鳍状结构，但是本公开不限于此，可以形成各种弯曲形状，例如弧形、弓形、多项式曲线等或其组合。例如，如图16所示，在以上结合图1(a)描述的操作中，可以将光刻胶PR构图为大致“S”形，而不是大致“C”形。其他操作可以如上所述进行。这样，在以上结合图12(a)-12(c)描述的操作中，可以生长同样大致呈“S”形延伸的半导体 层1023，如图17所示。半导体层1023的长度同样可以相对于第一半导体层1005变大，如上所述。这样，如图28中箭头所示，半导体层1023的中心相对于纳米线1005-1和1005-2原本的中心将偏移。这有助于在生长过程中释放应力。更具体地，中心可以向弯曲形状的凸出一侧偏移(“S”形上半部向左侧偏移，而“S”形下半部向右侧偏移)。之后，可以按上述方式，形成与“S”形鳍1023相交的栅堆叠。
图18-22是示意性示出了根据本公开另一实施例的制造半导体器件流程中部分阶段的示意图。以下，将着重描述该实施例与上述实施例的不同之处。
首先，同上述实施例中一样，可以在衬底1001上形成纳米线1005-1和1005-2，并以纳米线为种子生长半导体层1023，如以上结合图1-12(c)所述。在该实施例中，衬底1001的表面可以是(111)晶面或(110)晶面。另外，最上方的纳米线材料层1005-2可以相对较厚，例如为约3～20nm，因为该层随后会用作掩模。
由于衬底1001的表面可以是(111)晶面或(110)晶面，因此纳米线1005-1和1005-2的上下两侧表面(参见图11(a))也可以是(111)晶面或(110)晶面，从而这两个表面可以更易于生长半导体层1023。
与上述实施例中结合图13(a)和13(b)描述的形成隔离层的操作不同，如图18所示，在回蚀隔离层时，并没有完全去除隔离层位于最下方的半导体层1023与衬底1001之间以及各半导体层1023之间的部分。隔离层1025的这些保留部分例如可以通过刻蚀中的底切来实现，并在随后可以用作掩模层。可以控制刻蚀的量，使得掩模层的宽度可以与纳米线1005-1、1005-2的宽度大致相同。
在此需要指出的是，尽管与隔离层的回蚀一起形成了这些掩模层，但是本公开不限于此。例如，可以如图13(a)和13(b)所述形成隔离层，然后在该隔离层上另外形成一电介质层(例如，氮化物层)。对这些氮化物层进行选择性刻蚀(并形成底切)，同样可以得到如图18所示的掩模层。
随后，如图19所示，可以纳米线以及掩模层为掩模，来选择性刻蚀如RIE半导体层1023。于是，半导体层1023可以留于纳米线与掩模层之间。于是，半导体层1023的这些剩余部分1023-1、1023-2和2013-3同样可以呈现纳米线的形状。对于由同一半导体层1023得到的纳米线1023-1和1023-2，它们可以 相对于它们之间的中线在晶体结构上成镜像对称。
然后，如图20所示，可以通过选择性刻蚀如RIE选择性去除纳米线1005-1、1005-2，且如图21所示，可以通过选择性刻蚀如RIE选择性去除掩模层1025(例如，湿法腐蚀)，来得到悬置的纳米线1023-1、1023-2和2013-3。这些纳米线在端部或其余部位处被支撑部支撑，如以上所述。
这些纳米线1023-1、1023-2和2013-3可以充当器件的鳍。基于鳍的器件制造可以如上所述进行，在此不再赘述。
这样，就得到了该实施例的半导体器件。如图22所示，该半导体器件可以包括与衬底1001相隔开的多条纳米线(1023-1、1023-2，2013-3)。这些纳米线可以包括高迁移率材料，以充当器件的鳍。此外，该器件还包括隔离层1025以及在隔离层1025上形成的与鳍1023相交的栅堆叠(1027、1029)。栅堆叠可以至少部分环绕各鳍1023。
在以上实施例中，以FinFET为例进行描述，但是本公开不限于此。本公开的技术可以适用于各种半导体器件，特别是需要利用高迁移率材料如Ge、SiGe、III-V族化合物半导体材料等的半导体器件，例如各种光电器件如光电二极管、激光二极管(LD)等。例如，可以通过对种子层上外延生长的半导体层/纳米线进行相应掺杂来形成pn结，以形成二极管。本领域技术人员知道各种方式来以半导体层/纳米线为基础制造各种半导体器件。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、平板电脑(PC)、个人数字助手(PDA)等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述制造半导体器件的方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状 的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (39)

  1. 一种半导体器件，包括：
    衬底；
    与衬底相隔开的至少一条纳米线，其中该纳米线沿弯曲的纵向延伸方向延伸；
    至少一个半导体层，分别绕各纳米线外周形成以至少部分环绕相应纳米线，且绕各纳米线形成的各半导体层彼此分离。
  2. 根据权利要求1所述的半导体器件，还包括：
    在衬底上形成的隔离层，隔离层露出各半导体层；以及
    在隔离层上形成的与半导体层相交的栅堆叠，其中栅堆叠包括至少部分环绕各半导体层外周的栅介质层以及栅导体层。
  3. 根据权利要求2所述的半导体器件，其中，至少部分环绕各纳米线外周的半导体层位于该纳米线与栅堆叠之间。
  4. 根据权利要求1所述的半导体器件，其中，存在多条纳米线，沿大致垂直于衬底表面的方向排列，且各纳米线彼此间隔开大致平行延伸。
  5. 根据权利要求1所述的半导体器件，其中，至少一条纳米线沿其纵向延伸方向包括第一部分和第二部分，绕该纳米线外周形成的半导体层包括至少部分环该绕纳米线的第一部分外周形成的第一部分以及至少部分环绕该纳米线的第二部分外周形成的第二部分。
  6. 根据权利要求2所述的半导体器件，其中，至少一条纳米线沿其纵向延伸方向包括第一部分和第二部分，绕该纳米线外周形成的半导体层包括至少部分环绕该纳米线的第一部分外周形成的第一部分以及至少部分环绕该纳米线的第二部分外周形成的第二部分，且栅堆叠包括与半导体层的第一部分相交的第一栅堆叠以及与半导体层的第一部分相交的第二栅堆叠。
  7. 根据权利要求5或6所述的半导体器件，还包括：沿与该纳米线的纵向延伸方向相交的方向延伸的电介质层，其中该电介质层将该纳米线的第一部分与第二部分相隔离，且将半导体层的第一部分与第二部分相隔离。
  8. 根据权利要求2所述的半导体器件，还包括：在衬底的表面上形成的 与半导体层相同材料的另一半导体层，其中隔离层形成于该另一半导体层上。
  9. 根据权利要求1所述的半导体器件，其中，纳米线包括Si，半导体层包括Ge、SiGe或III-V族化合物半导体。
  10. 一种半导体器件，包括：
    衬底；
    与衬底相隔开的至少两条纳米线，其中，各纳米线沿大致垂直于衬底表面的方向排列，且各纳米线彼此间隔开沿弯曲的纵向延伸方向大致平行延伸，其中至少一对相邻的纳米线相对于它们之间的中线在晶体结构上是镜像对称的。
  11. 根据权利要求10所述的半导体器件，还包括：
    在衬底上形成的隔离层，隔离层露出各纳米线；以及
    在隔离层上形成的与纳米线相交的栅堆叠，其中栅堆叠包括至少部分环绕各纳米线外周的栅介质层以及栅导体层。
  12. 根据权利要求10所述的半导体器件，其中，至少一条纳米线沿其纵向延伸方向包括第一部分和第二部分。
  13. 根据权利要求11所述的半导体器件，其中，至少一条纳米线沿其纵向延伸方向包括第一部分和第二部分，且栅堆叠包括与纳米线的第一部分相交的第一栅堆叠以及与纳米线的第一部分相交的第二栅堆叠。
  14. 根据权利要求12或13所述的半导体器件，还包括：沿与该纳米线的纵向延伸方向相交的方向延伸的电介质层，其中该电介质层将该纳米线的第一部分与第二部分相隔离。
  15. 根据权利要求11所述的半导体器件，还包括：在衬底的表面上形成的与纳米线相同材料的半导体层，其中隔离层形成于该半导体层上。
  16. 根据权利要求11所述的半导体器件，其中，衬底包括Si，纳米线包括Ge、SiGe或III-V族化合物半导体。
  17. 根据权利要求11所述的半导体器件，衬底的表面是(111)或(110)晶面。
  18. 根据权利要求1或10所述的半导体器件，其中，各纳米线大致呈“C”形或“S”形。
  19. 根据权利要求2或11所述的半导体器件，还包括：
    至少部分环绕各栅介质层外周的功函数调节层。
  20. 根据权利要求1或10所述的半导体器件，还包括：支撑部，各纳米线经支撑部而在物理上连接到衬底。
  21. 根据权利要求20所述的半导体器件，其中，在纳米线的纵向延伸方向上，纳米线与支撑部相连接的部分的延伸范围小于纳米线的纵向延伸长度。
  22. 根据权利要求21所述的半导体器件，其中，支撑部包括沿衬底表面延伸的横向延伸部分以及沿大致垂直于衬底表面的方向延伸的竖直延伸部分，其中竖直延伸部分延伸至各纳米线沿大致垂直于衬底表面的竖直侧壁上。
  23. 根据权利要求21所述的半导体器件，其中，
    在衬底上与纳米线相对应的位置处，衬底具有突起，
    支撑部的竖直延伸部分中的一部分沿着突起的表面延伸，而另一部分沿着各纳米线的竖直侧壁延伸。
  24. 根据权利要求20所述的半导体器件，其中，支撑部设于纳米线的两侧端部。
  25. 根据权利要求2或11所述的半导体器件，还包括：在隔离层的表面上依次形成的栅介质层和功函数调节层，其中，栅导体形成于位于隔离层表面上的栅介质层和功函数调节层上。
  26. 一种制造半导体器件的方法，包括：
    在衬底上形成沿弯曲的纵向延伸方向延伸的鳍状结构；
    在形成有鳍状结构的衬底上形成支撑部；
    去除鳍状结构的一部分，以形成与衬底隔开的至少一条纳米线，该至少一条纳米线由支撑部支撑；以及
    以各纳米线为种子层，分别生长半导体层。
  27. 一种制造半导体器件的方法，包括：
    在衬底上形成沿弯曲的纵向延伸方向延伸的鳍状结构；
    在形成有鳍状结构的衬底上形成支撑部；
    去除鳍状结构的一部分，以形成与衬底隔开的至少一条纳米线，该至少一条纳米线由支撑部支撑；
    以各纳米线为种子层，分别生长半导体层；
    在最靠近衬底的半导体层与衬底之间以及在各半导体层之间，形成掩模 层；
    以纳米线和掩模层为掩模，选择性刻蚀各半导体层，使得半导体层留于纳米线与掩模层之间；以及
    选择性去除纳米线和掩模层。
  28. 根据权利要求26或27所述的方法，其中，鳍状结构包括在衬底上形成的牺牲层和纳米线材料层交替叠置的叠层。
  29. 根据权利要求28所述的方法，其中，形成鳍状结构包括：依次将纳米线材料层和牺牲层构图为鳍状结构。
  30. 根据权利要求28所述的方法，其中，去除鳍状结构的一部分包括：选择性去除牺牲层。
  31. 根据权利要求26或27所述的方法，其中，通过选择性生长，来生长半导体层。
  32. 根据权利要求26或27所述的方法，进一步包括：
    在衬底上形成隔离层，其中隔离层露出各半导体层；以及
    在隔离层上形成与半导体层相交的栅堆叠。
  33. 根据权利要求32所述的方法，其中，在形成隔离层时，保留隔离层位于最靠近衬底的半导体层与衬底之间以及各半导体层之间的部分，以用作所述掩模层。
  34. 根据权利要求32所述的方法，其中，形成栅堆叠包括：
    形成至少部分环绕各半导体层外周的栅介质层；以及
    在隔离层上形成栅导体层。
  35. 根据权利要求26或27所述的方法，其中，形成支撑部包括：
    在形成有鳍状结构的衬底上形成层状材料，并通过将该层状材料构图为在物理上连接鳍状结构的表面和衬底的表面来形成支撑部。
  36. 根据权利要求35所述的方法，其中，形成层状材料并对其构图包括：
    形成层状材料使其覆盖鳍状结构和衬底表面，并形成掩模以遮蔽一部分支撑层，其中，在垂直于鳍状结构纵向延伸方向的方向上，掩模在鳍状结构上方延伸超出鳍状结构的范围；而在鳍状结构的纵向延伸方向上，掩模在鳍状结构上方覆盖鳍状结构的纵向延伸长度的仅一部分；
    选择性去除未被遮蔽的层状材料部分；以及
    去除掩模。
  37. 根据权利要求36所述的方法，其中，形成掩模包括：
    使掩模覆盖鳍状结构的两侧端部。
  38. 一种电子设备，包括由如权利要求1～25中任一项所述的半导体器件形成的集成电路。
  39. 根据权利要求38所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
PCT/CN2016/087251 2015-12-07 2016-06-27 具有高质量外延层的纳米线半导体器件及其制造方法 WO2017096781A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/060,399 US10978591B2 (en) 2015-12-07 2016-06-27 Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same
US17/197,930 US11532753B2 (en) 2015-12-07 2021-03-10 Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201510888321.4 2015-12-07
CN201510888321.4A CN105633166B (zh) 2015-12-07 2015-12-07 具有高质量外延层的纳米线半导体器件及其制造方法
CN201610440133.X 2016-06-17
CN201610440133.XA CN106098776B (zh) 2016-06-17 2016-06-17 具有高质量外延层的纳米线半导体器件及其制造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/060,399 A-371-Of-International US10978591B2 (en) 2015-12-07 2016-06-27 Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same
US17/197,930 Division US11532753B2 (en) 2015-12-07 2021-03-10 Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2017096781A1 true WO2017096781A1 (zh) 2017-06-15

Family

ID=59013682

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/087251 WO2017096781A1 (zh) 2015-12-07 2016-06-27 具有高质量外延层的纳米线半导体器件及其制造方法

Country Status (2)

Country Link
US (2) US10978591B2 (zh)
WO (1) WO2017096781A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017096780A1 (zh) * 2015-12-07 2017-06-15 中国科学院微电子研究所 具有高质量外延层的半导体器件及其制造方法
CN105977299B (zh) * 2016-06-17 2019-12-10 中国科学院微电子研究所 半导体器件及其制造方法
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US11244871B2 (en) * 2019-06-27 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of fabricating semiconductor devices for tightening spacing between nanosheets in GAA structures and structures formed thereby
CN111415902B (zh) * 2020-03-05 2023-07-14 中国科学院微电子研究所 一种金属纳米结构及其制作方法、电子器件、电子设备
US20230178658A1 (en) * 2021-12-02 2023-06-08 Intel Corporation Recessed inner gate spacers and partial replacement channel in non-planar transistors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339947A (zh) * 2007-07-02 2009-01-07 恩益禧电子股份有限公司 半导体器件
CN103456638A (zh) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 自对准GaAs FinFET结构及其制造方法
CN105633166A (zh) * 2015-12-07 2016-06-01 中国科学院微电子研究所 具有高质量外延层的纳米线半导体器件及其制造方法
US20160172359A1 (en) * 2014-12-16 2016-06-16 Young-Soo Yoon Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7354831B2 (en) 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
US7786024B2 (en) * 2006-11-29 2010-08-31 Nanosys, Inc. Selective processing of semiconductor nanowires by polarized visible radiation
US7538391B2 (en) 2007-01-09 2009-05-26 International Business Machines Corporation Curved FINFETs
US8399879B2 (en) 2008-06-09 2013-03-19 National Institute Of Advanced Industrial Science And Technology Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor
US9240410B2 (en) * 2011-12-19 2016-01-19 Intel Corporation Group III-N nanowire transistors
WO2013095651A1 (en) 2011-12-23 2013-06-27 Intel Corporation Non-planar gate all-around device and method of fabrication thereof
US9087863B2 (en) * 2011-12-23 2015-07-21 Intel Corporation Nanowire structures having non-discrete source and drain regions
US8658518B1 (en) * 2012-08-17 2014-02-25 International Business Machines Corporation Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices
US8785909B2 (en) 2012-09-27 2014-07-22 Intel Corporation Non-planar semiconductor device having channel region with low band-gap cladding layer
US9171843B2 (en) 2013-08-02 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
CN106030810B (zh) 2013-09-27 2019-07-16 英特尔公司 经由用于硅上异质集成的模板工程的改进的包覆层外延
US9263520B2 (en) * 2013-10-10 2016-02-16 Globalfoundries Inc. Facilitating fabricating gate-all-around nanowire field-effect transistors
CN105633167B (zh) 2015-12-07 2019-10-01 中国科学院微电子研究所 具有高质量外延层的半导体器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101339947A (zh) * 2007-07-02 2009-01-07 恩益禧电子股份有限公司 半导体器件
CN103456638A (zh) * 2012-06-05 2013-12-18 中芯国际集成电路制造(上海)有限公司 自对准GaAs FinFET结构及其制造方法
US20160172359A1 (en) * 2014-12-16 2016-06-16 Young-Soo Yoon Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same
CN105633166A (zh) * 2015-12-07 2016-06-01 中国科学院微电子研究所 具有高质量外延层的纳米线半导体器件及其制造方法

Also Published As

Publication number Publication date
US20180277682A1 (en) 2018-09-27
US10978591B2 (en) 2021-04-13
US20210226058A1 (en) 2021-07-22
US11532753B2 (en) 2022-12-20

Similar Documents

Publication Publication Date Title
US11152516B2 (en) Nanometer semiconductor devices having high-quality epitaxial layer
WO2017096781A1 (zh) 具有高质量外延层的纳米线半导体器件及其制造方法
US9954063B2 (en) Stacked planar double-gate lamellar field-effect transistor
US8551833B2 (en) Double gate planar field effect transistors
TWI577018B (zh) 非平面第三族氮化物電晶體
TWI533449B (zh) 經由針對矽上之異質集成的模板工程之改良包覆層磊晶
EP2924738B1 (en) Method for manufacturing a iii-v gate all around semiconductor device
US9337340B2 (en) FinFET with active region shaped structures and channel separation
KR101624388B1 (ko) 채널 에피택셜 영역을 갖는 ｆｉｎｆｅｔ 디바이스
US10043909B2 (en) Semiconductor devices having high-quality epitaxial layer and methods of manufacturing the same
US20160079394A1 (en) Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same
CN110660799A (zh) 用于堆叠式晶体管集成的基座鳍结构
TWI692107B (zh) 具有逆行半導體源/汲極之高遷移率的場效電晶體
KR20160098187A (ko) 반도체 디바이스를 위한 듀얼 스트레인된 클래딩층
WO2024174843A1 (zh) 半导体结构及其形成方法
US11276769B2 (en) Semiconductor device and method of manufacturing the same
WO2017096780A1 (zh) 具有高质量外延层的半导体器件及其制造方法
US20220367672A1 (en) Semiconductor devices and methods of manufacturing thereof
US20240113214A1 (en) Semiconductor structure with dielectric spacer and method for manufacturing the same
CN106098623B (zh) 具有高质量外延层的半导体器件及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16871985

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 16060399

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16871985

Country of ref document: EP

Kind code of ref document: A1