CN100435327C - 具有接合焊盘的半导体器件及其制造方法 - Google Patents

具有接合焊盘的半导体器件及其制造方法 Download PDF

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Publication number
CN100435327C
CN100435327C CNB038057700A CN03805770A CN100435327C CN 100435327 C CN100435327 C CN 100435327C CN B038057700 A CNB038057700 A CN B038057700A CN 03805770 A CN03805770 A CN 03805770A CN 100435327 C CN100435327 C CN 100435327C
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China
Prior art keywords
pad
bond
layer
district
bond pads
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Expired - Lifetime
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CNB038057700A
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Chinese (zh)
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CN1643684A (zh
Inventor
罗伊斯·E.·永
彼德·R.·哈帕
涂安·特朗
杰弗利·W.·玫兹
乔治·R.·里尔
迪乌·V.·迪恩
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SK Hynix Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB038057700A 2002-03-13 2003-03-12 具有接合焊盘的半导体器件及其制造方法 Expired - Lifetime CN100435327C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/097,036 2002-03-13
US10/097,036 US6844631B2 (en) 2002-03-13 2002-03-13 Semiconductor device having a bond pad and method therefor

Publications (2)

Publication Number Publication Date
CN1643684A CN1643684A (zh) 2005-07-20
CN100435327C true CN100435327C (zh) 2008-11-19

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CNB038057700A Expired - Lifetime CN100435327C (zh) 2002-03-13 2003-03-12 具有接合焊盘的半导体器件及其制造方法

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Country Link
US (2) US6844631B2 (https=)
EP (1) EP1483787A2 (https=)
JP (2) JP5283300B2 (https=)
KR (1) KR100979081B1 (https=)
CN (1) CN100435327C (https=)
AU (1) AU2003218145A1 (https=)
TW (1) TWI266402B (https=)
WO (1) WO2003079437A2 (https=)

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KR102893028B1 (ko) 2020-08-25 2025-11-27 삼성전자 주식회사 반도체 패키지
KR102815730B1 (ko) * 2020-09-03 2025-06-02 삼성전자주식회사 반도체 패키지
TWI737498B (zh) * 2020-09-21 2021-08-21 丁肇誠 具有能態層的半導體測試晶片，及具有能態層之半導體測試晶片的製作方法
CN114284162B (zh) * 2020-09-27 2025-06-24 抱朴科技股份有限公司 半导体测试芯片及其制作方法
CN114334684B (zh) * 2020-09-29 2025-07-18 抱朴科技股份有限公司 具有可调能态的电连接垫的半导体测试芯片及其制作方法

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EP1483787A2 (en) 2004-12-08
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US20030173667A1 (en) 2003-09-18
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US6844631B2 (en) 2005-01-18

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