CN1717802B - 具有接合焊盘的半导体器件及其制造方法 - Google Patents

具有接合焊盘的半导体器件及其制造方法 Download PDF

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Publication number
CN1717802B
CN1717802B CN2003801042618A CN200380104261A CN1717802B CN 1717802 B CN1717802 B CN 1717802B CN 2003801042618 A CN2003801042618 A CN 2003801042618A CN 200380104261 A CN200380104261 A CN 200380104261A CN 1717802 B CN1717802 B CN 1717802B
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bond pad
integrated circuit
bonding region
wire
wire bonding
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CN1717802A (zh
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苏珊·H·唐尼
彼得·R·哈珀
凯文·赫斯
迈克尔·V·莱奥尼
图昂·德兰
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SK Hynix Inc
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Freescale Semiconductor Inc
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Abstract

一个接合焊盘(200)有第一引线接合区(202)和第二引线接合区(204)。在一个实施例中，第一引线接合区(202)在钝化层(18)之上延伸。在备选实施例中，接合焊盘具有探测区、第一引线接合区和第二引线接合区。在一个实施例中，探测区和引线接合区在钝化层(18)之上延伸。在不同结构中，接合焊盘可以有任何数量的引线接合和探测区。具有多个引线接和区的接合焊盘的能力允许多个引线连接到同一个接合焊盘上，例如在多芯片封装中。接合焊盘在钝化层之上延伸的能力，还能实现集成电路芯片面积的减小。

Description

具有接合焊盘的半导体器件及其制造方法
技术领域
本发明一般涉及半导体器件，更特别地是涉及具有接合焊盘的半导体器件。
背景技术
在集成电路制造业中，引线接合是一个众所周知的方法，被用来将具有电路系统的半导体芯片连接到元件封装上的管脚。另外，在集成电路制造业中，一个不断强健的共识就是封装多个半导体芯片于同一个封装中，该封装中多个半导体芯片可以放置在一个堆叠的结构里。在集成电路制造业中还存在一种很普遍的实践，就是在完成元件装配之前来测试半导体芯片的功能性。“探针测试”就是这样一种用来测试半导体的方法，其中探针触点普遍被用做与芯片上接合焊盘的机械与电的界面。
采用这种机械界面例如探测针带来的一个问题是接合焊盘可能被损伤或沾污，导致当芯片在被引线接合时无法在接合焊盘和封装管脚之间实现可靠的电连接。这个问题随着现代深亚微米半导体技术接合焊盘的几何尺寸不断减小而变的越来越严重。不断缩小的接合焊盘几何尺寸包括了在其上形成有更小引线接合的更小接合焊盘。这增大了由于探针接触而被损伤的接合焊盘的质量和可靠性方面的问题。随着接合焊盘的尺寸缩小，由于探针接触造成的损伤与接合焊盘损伤面积之间的比例也会增加。缩小接合焊盘几何尺寸带来的另一问题就是，对于使用传统方法例如悬臂式探针的粗探针测试方法而言，接合焊盘之间的间距可能太小。
因此，就需要有这样一种探针测试芯片的能力，它不会引起不可靠的引线接合连接，并且保证对具有小接合焊盘和接合焊盘上的细线宽间距的芯片进行粗探针测试。另外还需要为单一封装中的多个芯片提供电连接的能力。并且在很多场合，需要在不显著影响芯片的尺寸的情况下满足前述标准，来保持成本的降低。
附图说明
图1图示出根据本发明的引线接合焊盘的俯视图。
图2图示出根据本发明的具有图1的引线接合焊盘的半导体器件的剖面图。
图3图示出根据本发明的另一个实施例的半导体器件的剖面图。
图4图示出根据本发明的另一个实施例的半导体器件的剖面图。
图5至图14图示出根据本发明的具有多个引线接合焊盘的集成电路的备选实施例的俯视图。
图15图示出根据本发明的实施例的引线接合焊盘的俯视图。
图16图示出根据本发明的一个实施例的具有图15的接合焊盘的半导体器件的剖面图。
图17图示出根据本发明的一个实施例的具有多个引线接合焊盘的集成电路的俯视图。
图18图示出根据本发明的备选实施例的引线接合焊盘的俯视图。
图19图示出根据本发明的备选实施例的具有图18的接合焊盘的半导体器件的剖面图。
图20根据本发明的备选实施例的具有多个引线接合焊盘的集成电路的俯视图。
图21根据本发明的一个实施例的多集成电路芯片的俯视图，每个集成电路芯片均具有多个引线接合焊盘。
具体实施方式
一般而言，本发明提供了一种具有多个接合焊盘的集成电路。所述多个接合焊盘中的每一个都有探测区和引线接合区，它们基本上是不重叠的并且是相邻的。在一个实施例中，接合焊盘在集成电路的有源电路和/或电互连层之上延伸。部分或全部的接合焊盘在互连层之上延伸，而部分的焊盘可能在钝化层之上被形成并连接到最终金属层焊盘。在一个实施例中，接合焊盘是由铝形成的，而最终金属层焊盘是由铜形成的。
从引线接合区分离出探测区并在有源电路之上形成接合焊盘具有很多优点。在要求接合焊盘之间的极细线宽的应用中，探测区和引线接合区可以被错开以便有效地增加探测区之间的距离。通过从引线接合区中分离出探测区，引线接合区就不会被探针测试而损伤，从而获得更可靠的引线接合。另外，在有源电路、包括金属互连层之上形成接合焊盘，使得集成电路会更小。
在本发明的一个备选实施例中，多个接合焊盘中的每一个都有第一引线接合区和第二引线接合区，它们基本上重叠并且是相邻的。在一个实施例中，接合焊盘在集成电路的有源电路和/或电互连层之上延伸。部分或全部的接合焊盘在互连层之上延伸，以及部分的焊盘可能在钝化层之上被形成并连接到最终金属层焊盘。在一个实施例中，除了第一和第二引线接合区之外，接合焊盘可能还包括了探测区。
为每一个接合焊盘中提供多引线接合区的能力，允许将多个引线接合连接到每一个接合焊盘。这带来集成电路芯片之间更有效的引线接合连接，无论它们是采取堆叠式的结构还是彼此相邻。还有，通过从多引线接合区分离出探测区，引线接合区就不会被探针测试所损坏，这就获得了更可靠的引线接合。另外，如上所述，在有源电路、包括金属互连层之上形成接合焊盘，使得集成电路会更小。
图1图示出根据本发明的接合焊盘10的俯视图。接合焊盘10被分隔成一个引线接合区12和一个探测区14，由虚线标明。为了适应引线接合和探测工具的尺寸和精度的需要，引线接合区12和探测区14被布局和调整大小。在所示的本实施例中，引线接合区12被描画的比探测区14更小一些。在其它的实施例中，各个区可能被定义成不同的大小。
接合焊盘10可以被设计位于如图2、图3和图4剖面图所示的不同的半导体器件中。请注意，相像或类似的元素在所有图中都被给予相同的附图标记，另外注意的是所有图都不是按比例所画。图2图示出根据本发明的半导体器件20的剖面图。半导体器件20具有边缘、即外围25、钝化层18、接合焊盘10、互连区24，和有源区或衬底26。接合焊盘10有引线接合区12和探测区14(见图1)并且它相对于外围25被定位。互连区24包括用于传送电源、地电平、信号的金属层28、30和32，以及半导体器件20中各种元件之间的其它连线。如图2中所示，金属层28在下文中被称为最终金属层28，其被置于接近半导体器件20的表面，同时还包括接合焊盘10，在该接合焊盘10处应用探测和引线接合以形成与位于半导体器件20之外的器件(没有示出)的连接。互连区24的金属层可以通过连通孔在彼此之间互连起来。互连金属层32是通过触点和有源区电气连接。
对半导体器件20施用常规的制作技术以便在有源区26或衬底中形成电路。这个电路可被用于各种集成电路应用，例如通信、运输、常规计算或娱乐。在所示的实施例中，金属层28、30和32用导电材料被形成，举例来说，铝、铜、或者金。在其它的实施例里，可以有更多或更少的金属层。接合焊盘10作为最终金属层28的一部分被形成。在金属层28被形成之后，钝化层18被沉积在半导体器件表面。在钝化层18上打开一些开口，就像在接合焊盘10上方所示出的，用于例如在半导体器件20和封装上的一根管脚之间实现电连接。
接合焊盘10是由相对厚的铜层来形成的。在一个实施例中，铜可以是0.3到1.0微米厚。测试表明接合焊盘10足够强来承受引线接合设备的冲击并能够在互连层24之上被形成，而不会损坏互连层24以及如图2中所示的有源区26的下层电路。
图3图示出根据本发明的半导体器件34的剖面图。半导体器件34具有边缘、即外围25、钝化层18、互连区24、有源区26，和接合焊盘36。接合焊盘36包括最终金属层焊盘16和铝焊盘层35。铝焊盘层35包括引线接合区38和探测区37。铝焊盘层35可能在0.5至2.0微米之间厚。接合焊盘36被相对于半导体器件34的外围25来定位，并通过阻挡层22与最终金属层焊盘16分开。接合焊盘36被布局和调整大小，以便容纳探测区37和引线接合区38。
如对于图2中的半导体器件20所述的那样，对半导体器件34施用制造技术和材料。另外，在钝化层18之上形成阻挡层22，以便在最终金属层焊盘16和接合焊盘36之间、以及接合焊盘36和钝化层18之间提供扩散阻挡层和粘附层。在沉积阻挡层22之后，铝焊盘层35被沉积在阻挡层22之上。阻挡层22和铝焊盘层35接着被形成图案来得到探测和引线接合区所需要的最终形状和大小。在所示的实施例中，铝焊盘层35是由铝所形成，但是在其它的实施例中，铝焊盘层35可以由其它导电的材料所形成。此外，互连区24的金属层28、30和32，以及最终金属层焊盘16都是由铜所形成。在其它的实施例中，其它的导体材料可用于接合焊盘36、最终金属层焊盘16，和金属层28、30和32。举例说明，金属层28、30和32，以及最终金属层焊盘16可由铝或者金制成，最终金属层焊盘16可包含金。另外，在所示的实施例中，阻挡层22是由钽形成。但是在其它实施例中，阻挡层22可以是用于在不同但相邻的材料之间形成扩散阻挡层和粘附层的任何材料。扩散阻挡层材料的例子包括氮化钽、钛、氮化钛、镍、钨、钛钨合金和氮化钽硅。
接合焊盘36的铝层焊盘35和最终金属焊盘16分别由相对厚的铝层和铜层所形成。因此，接合焊盘36足够强来承受引线接合设备的冲击并能够在互连层24之上被形成，而不会损坏互连层24以及图3中所示的有源区26的任何下层电路。
图4图示出根据本发明的另一实施例的半导体器件40的剖面图。半导体器件40具有边缘、即外围25、钝化层18、互连区24、有源区26，和接合焊盘44。接合焊盘44包括铝焊盘45和最终金属焊盘42。最终金属焊盘42是作为最终金属层28的一部分被形成。接合焊盘44相对半导体器件40的外围25来定位，并被分成探测区和引线接合区，如由图4中的一条垂直虚线所示出的。铝焊盘45通过阻挡层43与最终金属层焊盘42所分开。
对半导体器件40施用如图2和图3所述的制造技术和材料。然而，在图4的器件中，接合焊盘44的一部分在钝化层18、下层有源电路26和/或连接区24的上方延伸，并且其余部分在钝化层18的开口处被连接到最终金属层焊盘42。如上所述，接合焊盘44被分成引线接合区和探测区。探测区接合焊盘10上的一部分上，该部分延伸至钝化层18之上，并在互连区24的电互连层28，30和32的上方延伸。引线接合区在接合焊盘44的一部分上被形成，该部分被连接到最终金属层焊盘42。引线接合区足够强来承受引线接合设备的冲击，而不会使下层电路损坏或变形，也可以在互连区24的金属层之上被形成。
通过在钝化层18上方延伸探测区，最终金属层焊盘42的尺寸不会受到影响，并且能够在不增加半导体器件的整体尺寸的情况下增加接合焊盘44的尺寸。另外，由于最终金属层焊盘42不是用于探针测试或引线接合，最终金属层焊盘42的大小和形状以及钝化层18中开口的大小和形状，都只是受限于给接合焊盘44提供电连接所需要的面积。在其它实施例中，可以有多个更小的最终金属层焊盘和相应的钝化层开口，它们共同给接合焊盘44提供足够的电连接。由于接合焊盘44是在钝化层18上方延伸，并且最终金属层焊盘42的大小不受影响，所以在对探测区和引线接合区进行布局时有更多的灵活性。举个例子，在其它实施例中，探测区和引线接合区不是必须相邻。
接合焊盘44可由铝形成，并且最终金属层焊盘42可由铜形成。除了为了更可靠的引线接合而将引线接合区与探测区分离之外，在钝化层18上方进行探测消除了最终金属层焊盘42不利地暴露出铜的风险。暴露出的铜很容易被氧化并对引线接合形成一个不可靠的表面。
图5图示出根据本发明的一个实施例的半导体器件60的俯视图。集成电路60包括类似图1中所示的接合焊盘的多个接合焊盘，并能够依照图2和图3所示的实施例进行结构。集成电路60包括多个接合焊盘62-65，它们沿着集成电路60的边缘61来形成。大量接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口66。每一个接合焊盘都被分成如图1中所论述过的探测区和引线结合区。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。所述多个接合焊盘被相对于外围61来排列。每一个接合焊盘的引线接合区要比探测区离外围61更近。相邻接合焊盘的引线接合区被维持在一条同边缘61等距的直线上。同样的，相邻接合焊盘的探测区也被维持在一条同边缘61等距的直线上。在其它实施例中，探测区和引线接合区可以被互换。
图6图示出根据本发明的另一个实施例的半导体器件70的俯视图。集成电路70包括与图1中所示的接合焊盘类似的接合焊盘，并且可以依照图4所示的实施例的来构造。集成电路70包括多个接合焊盘72-75，它们沿着集成电路70的边缘71来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口76。每一个接合焊盘都被分成如图1中所论述过的探测区和引线结合区。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。多个接合焊盘被相对于外围71来排列。每一个接合焊盘的引线接合区要比探测区离外围71更近。相邻接合焊盘的引线接合区被维持在一条同边缘71等距的直线上。同样的，相邻接合焊盘的探测区也被维持在一条同边缘71等距的直线上。在其它实施例中，探测区和引线接合区可以被互换。
如图4所示，接合焊盘72-75一部分在钝化层上方被形成，而接合焊盘的的另一部分在最终金属层焊盘之上被形成。
图7所示的是依照该技术另一个实施例的半导体器件80的俯视图。集成电路80包括与图1中所示的接合焊盘相类似的多个接合焊盘，并且依照图2和图3所示的实施例来构造。集成电路80包括多个接合焊盘82-85，它们沿着集成电路80的边缘81来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口86。每一个接合焊盘都被分成如图1中所论述过的探测区和引线结合区。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。所述接合焊盘一般是相同大小，并通常被设置在同外围81相等距离处。
探测区(由椭圆形表示)被以交错地、交替地方式形成于在引线接合区(圆形)相对侧，而引线接合区被维持在一条离集成电路80的边缘81等距的直线上。此外，每一个接合焊盘的中心也被维持在一条离边缘81等距的直线上。所有的接合焊盘82-85都在最终金属层焊盘上方被形成，如图3所示。
通过交错或交替安排探测区，探测区之间的距离会增大，这就允许更粗壮的探针测试于极细间距的器件，并且有使用各种探测技术的灵活性，例如悬臂和垂直的探针技术。当前的探测技术不支持低于最小规定尺寸的焊盘间距，此处间距是指焊盘之间的距离。通过拉长接合焊盘以及将探测区交错，当前的探测技术能够被扩展至具有更小间距的焊盘。将引线接合区维持在一条线上更加简化对引线接合设备的设计(programming)。注意在其它实施例中，探测区和引线接合区可以被互换。
图8图示出根据本发明的另一个实施例的半导体器件90的俯视图。集成电路90包括与图1中所示的接合焊盘相类似的多个接合焊盘，并且被依照图4所示的实施例进行构造。集成电路90包括多个接合焊盘92-95，它们沿着集成电路90的边缘91来形成。大量接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口96。
图8的接合焊盘安排和图7的接合焊盘安排一样，除了钝化层中的开口96更小并且只环绕一般用圆形表示的每一个引线接合区。探测区是用椭圆形表示的，并且如上面图7所述是交错开的。另外，探测区在半导体器件90的钝化层上方延伸。
图9图示出根据本发明的另一个实施例的半导体器件100的俯视图。集成电路100包括与图1中所示的接合焊盘相类似的多个接合焊盘，并且依照图2或图3所示的实施例来构造。集成电路100包括多个接合焊盘102-105，它们沿着集成电路100的边缘101来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口106。
钝化层中的开口106环绕接合焊盘102-105中的每一个的引线接合区(圆形)和探测区(椭圆形)。接合焊盘被安排成交错的形式，其中接合焊盘102和104被置于与接合焊盘103和105相比离外围101更远的地方。此外，每一个接合焊盘的探测区如上面图7和图8所述是交错开的。另外，每一个焊盘的引线接合区被安排在离参数101相等的距离上。
图9的接合焊盘比图8的接合焊盘要短，因为该区域没有被用于探针测试，或者已经去除了引线接合区域。由去除掉的那部分接合焊盘所提供的空间可以在半导体器件上提供更大的表面积来在集成电路上获得更多的特性或接合焊盘。
图10图示出根据本发明的另一个实施例的半导体器件110的俯视图。集成电路110包括多个与图1中所示的接合焊盘相类似的接合焊盘，并且依照图4所示的实施例来进行构造。集成电路110包括多个接合焊盘112-115，它们沿着集成电路110的边缘111来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口116。
接合焊盘112-115被安排成交错的形式，此处接合焊盘112和114被置于与接合焊盘113和115相比离外围111更远的地方。还有，每一个接合焊盘的探测区如上面图7、图8和图9所述是交错开的。另外，每一个焊盘的引线接合区被安排在离外围111相等的距离处。
钝化层中的开口116更小，并且只环绕一般用圆形表示的每一个引线接合区。探测区在半导体器件110的钝化层上方来延伸。
图11图示出根据本发明的另一个实施例的半导体器件120的俯视图。集成电路120包括多个与图1中所示的接合焊盘相类似的接合焊盘，并且依照图2或图3所示的实施例来构造。集成电路120包括多个接合焊盘122-125，它们沿着集成电路120的边缘121来形成。多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口126。每一个接合焊盘都被分成如图1中所论述过的探测区和引线结合区。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。所述多个接合焊盘被相对于外围121来排列。在图11的实施例中，探测区和引线接合区都是交错开的。
图12图示出根据本发明的另一个实施例的半导体器件130的俯视图。集成电路130包括多个与图1中所示的接合焊盘相类似的接合焊盘，并且依照图4所示的实施例来进行结构。集成电路130包括多个接合焊盘132-135，它们沿着集成电路130的边缘131来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口136。每一个接合焊盘都被分成如图1中所论述过的探测区和引线结合区。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。所述多个接合焊盘被相对于外围131来排列。在图12的实施例中，探测区和引线接合区都是交错开的。另外，探测区是在钝化层之上被形成的。
图13图示出根据本发明的另一个实施例的半导体器件140的俯视图。集成电路140包括与图1中所示的接合焊盘相类似的接合焊盘，并且依照图2或图3所示的实施例进行构造。集成电路140包括多个接合焊盘142-145，它们沿着集成电路140的边缘141来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口146。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。接合焊盘的长轴方向被定位为平行于边缘141。相邻接合焊盘的引线接合区和探测区都被维持在一条离边缘141等距的直线上。由于接合焊盘的长轴方向被定位为平行于边缘141，所以接合焊盘的整个高度就被减小，同时还为不受焊盘限制的集成电路保持分离的引线接合区和探测区。
图14图示出根据本发明的另一个实施例的半导体器件150的俯视图。集成电路150包括大多个与图1中所示的接合焊盘相类似的接合焊盘，并且依照图4所示的实施例来进行构造。集成电路150包括多个接合焊盘152-155，它们沿着集成电路150的边缘151来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口156。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。接合焊盘的长轴被定向为平行于边缘151。相邻接合焊盘的引线接合区和探测区都被维持在一条离边缘151等距的直线上。由于接合焊盘的长轴被定向为平行于边缘151，所以接合焊盘的整个高度就被减小，同时为不受焊盘限制的集成电路保持分离的引线接合区和探测区。在图14中，探测区是在钝化层上方被形成的。
图15图示出根据本发明的备选实施例的半导体器件200的俯视图。如虚线所示，接合焊盘200被分成第一引线接合区202和第二引线接合区204。按照适应引线接合设备的尺寸和精度的要求，引线接合区202和引线接合区204被布局和调整大小。在所示的实施例中，所示出的引线接合区202和引线接合区204具有同样大小。在其它实施例中，这些区可能会被定义成不同的尺寸。
接合焊盘200可以被设计到不同的半导体器件中，例如，举例来说，如图16中所示的半导体器件216的剖面图。如上所述，请注意在所有图示中在这里被用到的相像或类似的元素都被指定成相同的附图标记。另外要注意这些图都不是按比例画的。图16图示出根据本发明的备选实施例的半导体器件216(也可被称作集成电路216)的剖面图。半导体器件216具有边缘即外围25、钝化层18、互连区24、和有源区26，以及接合焊盘200。接合焊盘200包括铝焊盘210和最终金属层焊盘206。最终金属层焊盘206作为最终金属层28的一部分来形成。因此，在本实施例中，接合焊盘200可由铝形成，且最终金属层焊盘206可由铜形成。接合焊盘200被相对于半导体器件216的外围25来放置，并被分成两个引线接合区，如图16中由垂直的虚线所示出的那样。在这个如图16所示的实施例中，铝焊盘210通过阻挡层212与最终金属层焊盘206分开，阻挡层212在最终金属层焊盘206和铝焊盘210之间、以及铝焊盘210和钝化层18之间，提供了个扩散阻挡层和粘附层。然而，请注意，在备选实施例中，可以不存在阻挡层212。例如，如果最终金属层焊盘206是由铝而不是铜所形成，就可以需要阻挡层212。另外还要注意，接合焊盘200可由任何一种可引线接合的导电材料所形成，诸如铝、铜和金。
对半导体器件216施用如图4所述的制造技术和材料。正如图4，在图16的器件中，接合焊盘200的一部分在钝化层18、下层有源电路26和/或互连区24上方延伸，并且其余部分在钝化层18的开口处连接到最终金属层焊盘206。如上所述，焊盘200被分成引线接合区202和引线接合区204。在所示的实施例中，引线接合区204被形成于接合焊盘200的一部分上，该部分被连接到最终金属层焊盘206，而引线接合区202则被形成于在钝化层18上方。也就是说，请注意接合焊盘200的一部分在钝化层18上方。因此，在一个实施例中，引线接合区202或者引线接合区204的非外围部分，或者是引线接合区202或者引线接合区204的大部分，可以被置于钝化层18上方。例如，在一个实施例中，可以仅仅将引线结合区204的一部分形成在被连接到最终金属层焊盘206的接合焊盘200的部分上。在本实施例中，所有引线接合202和引线接合204的剩余部分都被置于钝化层18上方。可替换的是，所有引线接合204和部分的引线接合202可以被形成在连接到最终金属层焊盘206的接合焊盘200的部分上。在本实施例中，可以仅仅将引线接合202的剩余部分将置于钝化层18上方。在又一个实施例中，钝化层18可能有多个开口来露出最终金属层28，接合焊盘200的多个部分(包括引线接合204的部分、引线接合202的部分，或者是这两者的部分)可以在该开口处连接到最终金属层28。
请注意在钝化层18上方的引线接合区足够强来承受引线接合工具的冲击，而不会使下层钝化层18或电路被损坏或变形。还要注意尽管图15和16仅仅图示出两个引线接合区，但是接合焊盘200可以被制成包含任何数量的引线接合区而不仅仅限制于两个。
通过在在钝化层18上方延伸接合焊盘200，最终金属层焊盘206的尺寸没有受到影响，并且能够在不增大半导体器件的整体尺寸的情况下增加接合焊盘200的尺寸。接合焊盘200的增加的尺寸允许连接到一个接合焊盘上的多引线接合连接，这可以用于将多个集成电路芯片封装在一起，如在下文中参考图21所详细描述的那样要。而且，由于最终金属层焊盘206不没有被用于引线接合，所以最终金属层焊盘206的尺寸和形状、以及钝化层18中开口的尺寸和形状，都仅仅受限于提供与接合焊盘200的电连接所需要的面积。在其它实施例中，存在多个更小的最终金属层焊盘和相应的钝化层开口，它们共同给接合焊盘200提供足够的电连接。由于接合焊盘200是在钝化层18上方延伸的，并且最终金属层焊盘206的尺寸没有受到影响，所以在对引线结合区布局方面有更多的灵活性。例如，在其它实施例中，引线接合区可以不必是相邻的。
图17图示出根据本发明的另一个实施例的半导体器件230的俯视图。集成电路230包括多个与图15中所示的接合焊盘相类似的接合焊盘，并且依照图16所示的实施例来构造。集成电路230包括多个接合焊盘222-225，它们沿着集成电路230的边缘232来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口220。每一个接合焊盘被分成多个引线接合区(也就是，在这个例子中是两个区)，如图15中所论述的。每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。所述多个接合焊盘被相对于外围232来排列。在所示的实施例中，接合焊盘被维持在一条离边缘232等距的直线上。在其它实施例中，所述多个接合焊盘中的每一个都可以包括更多的引线接合区而不仅仅是如图17中所示的两个。
如图16中所示，接合焊盘222-225的一部分是在钝化层上方被形成，而接合焊盘的另一部分是在最终金属层焊盘上方被形成。请注意尽管所示的开口220被图示为处于整个一个引线接合区的下面，但是开口220也可以以上面参考图16所论述的多种方式来被形成。另外，开口220可以是任意大小或形状。举例来说，开口220可能同整个接合焊盘222一样大，或者可以比所示的要小。开口220也可以是任意形状，例如圆形、正方形等等。替换的是，开口220也可以在接合焊盘222下方包括多个开口(具有任意大小或形状)。还要注意的是，备选实施例可能为接合焊盘222-225采用备选结构。例如，它们可以被交错、调整大小、布局以及以多种不同的方式来定位。例如，即使没有出现探测区，也可以为具有多引线接合区的接合焊盘使用图7-14中所示的结构。然而，正如在下面将要描述的，备选实施例可以为具有多引线接合区和探测区(或多个探测区)的接合焊盘采用图5-14中的结构。
图18图示出根据本发明的备选实施例的接合焊盘300的俯视图。接合焊盘300被分成探测区302、第一引线接合区304和第二引线接合区306，如虚线所标明。按照适应引线接合和探测工具的大小和精度的要求，引线接合区304和306以及探测区302被布局和调整尺寸。在所示的实施例中，引线接合区304被示为与引线接合区306具有同样大小，并与之相邻。另外，在所示的实施例中，引线接合区304和306被示为小于探测区302。然而，在备选实施例中，这些区可能会被调整成不同的尺寸。此外，在备选实施例中，探测区302可被置于引线接合区304和引线接合区306之间，或者可以被置于与引线接合306邻近而不是与引线接合304邻近的相对侧。在其它的实施例中，探测区302可以与引线接合区304和306都邻近，或者只同引线接合区304和306之一相邻近。也就是说，可以使用引线接合区和探测区的任意排列来形成接合焊盘300。另外，尽管没有被示出，但接合焊盘300可以根据需要，以任何顺序来包含任意数量的接合焊盘区和任意数量的探测区。
接合焊盘300能够被设计在不同的半导体器件中例如，被设计位于具有如图19所示的剖面图的半导体器件314中。图19图示出根据本发明的一个备选实施例的半导体器件314(也可能被称为集成电路314)的剖面图。半导体器件314具有边缘、即外围25、钝化层18、互连区24和有源区26，以及接合焊盘300。接合焊盘300包括铝焊盘308和最终金属层焊盘206。最终金属层焊盘206作为最终金属层28的一部分被形成。因此，在一个实施例中，接合焊盘300可以由铝形成，而最终金属层焊盘206可由铜形成。接合焊盘300被相对于半导体器件314的外围25来定位，并被分成两个引线接合区304和306以及一个探测区302，如在图19通过垂直的虚线所示出的。在这个如图19所示的实施例中，铝焊盘308通过阻挡层310与最终金属层焊盘206分开，该阻挡层310在最终金属层焊盘206和铝焊盘308之间、以及铝焊盘308和钝化层18之间提供扩散阻挡层和粘附层。然而，请注意，在备选的实施例中，可以不提供阻挡层310。例如，如果最终金属层焊盘206是由铝而不是铜所形成，则可能不需要阻挡层310。另外还要注意的是，接合焊盘200可以由任何一种可引线接合的导电材料所形成，例如铝、铜和金。
对半导体器件314施用如图16所述的制造技术和材料。如在图16中，在图19的器件中，接合焊盘300的一部分在钝化层18、下层有源电路26和/或互连区24上方延伸，而其余部分在钝化层18的开口处连接到最终金属层焊盘206。如上所述，焊盘300被分成探测区302、引线接合区304和引线接合区306。在所示的实施例中，引线接合区306被形成于在接合焊盘300的一部分上，该部分被连接到最终金属层焊盘206，而引线接合区304和探测区302被形成于接合焊盘300的一部分上，该部分在钝化层18上方延伸(并且在互连区24的电互连层28、30和32以及有源区26上方延伸)。也就是说，请注意接合焊盘300的一部分是在钝化层18上方延伸。因此，在一个实施例中，引线接合区304、引线接合区306或者探测区302的非外围部分，或者是引线接合区304、引线接合区306或者探测区302的大部分都可以被置于钝化层18上方。例如在一个实施例中，可以仅仅在接合焊盘300的被连接到最终金属层焊盘206的部分上形成引线结合区306的一部分。在本实施例中，所有的引线接合304、探测区302和引线接合306的剩余部分都被置于钝化层18上方。替换的是，可以在接合焊盘300的被连接到最终金属层焊盘206的部分上形成引线接合区304和306以及探测区302的任意部分，其中剩余的部分是在钝化层18上方延伸的。还有在另一个实施例中，钝化层18可以具有多个开口来露出最终金属层28，在该开口处，接合焊盘300的多个部分可以被连接到最终金属层28。
请注意在钝化层18上方延伸的引线接合区304和306足够强来承受引线接合设备的冲击，而不会使下层的钝化层18和电路被损坏或变形。还要注意当探测区302是在钝化层18上方形成时，探测设备的冲击也不会损伤钝化层18。
通过在钝化层18上方延伸接合焊盘300，最终金属层焊盘206的尺寸没有受到影响，并且能够在不增加半导体器件的整体尺寸的情况下增加接合焊盘300的尺寸。接合焊盘300的增加的尺寸允许多个引线接合到单一的接合焊盘的连接，这可被用于将多个集成电路芯片封装在一起，正如在下文中参考图21中所详细描述的那样，同时还允许探针测试。此外，由于最终金属层焊盘206没有被用于探针测试或引线接合，所以最终金属层焊盘206的尺寸和形状、以及钝化层18中开口的尺寸和形状，都仅仅只受限于提供到接合焊盘300的电连接所需要的面积。在其它实施例中，可以有多个更小的最终金属层焊盘和相应的钝化层开口，它们共同给接合焊盘300提供足够的电连接。由于接合焊盘300是在钝化层18上方延伸的，并且最终金属层焊盘206的尺寸没有受到影响，所以在探测区和引线结合区布局方面有更大的灵活性。例如在其它实施例中，探测区和引线接合区可以不必是相邻的。
除了具有多个引线接合区来允许多个引线接合到同一个接合焊盘的连接之外，把探测区与引线接合区或多个引线接合区中分离开会带来更可靠的引线接合。此外，把探测区与引线接合区或多个引线接合区中分离开允许在钝化层18之上进行测试，这就消除了最终金属层焊盘206不利地暴露出铜的风险。暴露出的铜很容易被氧化并对引线接合形成一个不可靠的表面。
图20图示出根据本发明的另一个实施例的半导体器件324的俯视图。集成电路324包括多个与图18中所示接合焊盘300的类似的接合焊盘，并依照图19所示的实施例来进行构造。集成电路324包括多个接合焊盘318-321，它们沿着集成电路324的边缘322来形成。所述多个接合焊盘中的每一个上边的虚线表示形成于钝化层中的开口316。每一个接合焊盘被分成多个引线接合区(也就是，在这个例子中是两个区)和一个探测区，如图18中所论述的。每一个接合焊盘上被界定成椭圆形的区域，一般被设计成探针测试区；每一个接合焊盘上被界定成圆形的区域，一般被设计成引线接合区。所述多个接合焊盘被相对于参数322来排列。在所示的实施例中，与探测区相比，每一个接合焊盘的引线接合区离外围322更近，并且相邻接合焊盘的引线接合区被维持在一条离边缘322等距的直线上。同样地，相邻接合焊盘的探测区也被维持在一条离边缘322等距的直线上。在其它实施例中，所述多个接合焊盘中的每一个都可以包括更多的引线接合区而不仅仅如图20所示的两个，和/或包括更多的探测区。另外，如提到的图18中所论述的，可以以任意顺序来安排每一个接合焊盘的探测区和引线接合区。
如图19所示，接合焊盘318-321的一部分是在钝化层上方形成的，而接合焊盘的一部分是在在最终金属层焊盘上方形成的。注意的是，所示的开口316被图示为处于整个一个引线接合区的下方，但也可以如上文参考图19中所论述过的那样，以各种不同的方式来形成开口316。另外，开口316可以具有任意大小和形状。举例，开口316可以同整个接合焊盘318一样大，或者可以比所示的要小。开口316也可以是任意形状，例如圆形、正方形等等。替换的，开口316可以在接合焊盘318下方包括多个开口(任意大小和形状)。还要注意的是，备选实施例可以采用接合焊盘318-321的备选结构。例如，它们可以被交错、调整大小、布局以及以各种不同方式来定位，如上面图7-14所示。例如，如图7-14所示的结构也可以被用于带有多个引线接合区和一个或多个探测区的接合焊盘。
图21图示出根据本发明的一个实施例的使用具有多个引线接合区的接合焊盘的多集成电路芯片结构325的俯视图。请注意附图被按比例绘制，并且没有将所有的接合焊盘都示出来。也就是说，为便于解释而仅仅示出了接合焊盘的一部分，但是一名本领域普通技术人员能够理解如何完成该接合焊盘结构。图21图示出印刷电路板(PCB)326，该印刷电路板(PCB)326具有第一集成电路芯片328和堆叠于该第一集成电路芯片328之上的第二集成电路芯片330。也就是说，图21图示出在堆叠式多芯片封装中配置的多集成电路芯片。集成电路芯片330包括沿着集成电路芯片330的外围(也就是在集成电路芯片330的外围区域)放置的接合焊盘332-334、336、337和353，以及位于集成电路芯片330的非外围区中的接合焊盘350。在所示的实施例中，接合焊盘332-334、336、337和353每一个都具有单一的引线接合区，但是在备选实施例中，其也可以具有任意数量的引线接合区及一个或多个探测区。集成电路芯片328包括沿着集成电路芯片328的外围(也就是在集成电路芯片328的外围区域)放置的接合焊盘338-343，以及在集成电路芯片328的非外围区域中的接合焊盘351。在这个所示的实施例中，接合焊盘338-343每一个都具有多个引线接合区，并且接合焊盘343带有多个引线接合区和一个探测区。然而，在一个备选实施例中，每一个接合焊盘都可以具有任意数量的引线接合和探测区。PCB326包括接合柱344-348和352。
如图21所示，具有多引线接合区的接合焊盘可被用于提供到单一接合焊盘的多个电连接。例如，位于集成电路330的非外围区中的接合焊盘350，可被用于同时向集成电路330上的接合焊盘353和集成电路328上的接合焊盘351提供连接(即，引线连接)。例如在一个实施例中，接合焊盘350可以对应于需要被传送到集成电路330上的另一位置以及到集成电路328上的接合焊盘的电源或地电平。然后，具有两个引线接合区接合焊盘351，可以具有与接合柱352的第二引线接合连接，以致可以仅仅使用两个接合焊盘就能实现从集成电路330到集成电路328再到PCB326个的连接(即，引线连接)。类似的，在集成电路328上的接合焊盘339和342分别实现了集成电路330的接合焊盘334和336到PCB326(到接合柱345和347)之间的电连接(也就是引线连接)，并且实现了从接合焊盘339和342到PCB326(到接合柱345和347)之间的连接。由于使用了具有多个引线接合区的接合焊盘，因此不再需要额外的接合焊盘来实现多个芯片到PCB326的连接。还要注意，尽管没有被示出，但可以形成直接从集成电路芯片330到PCB326的电连接。例如，来自接合焊盘350的连接之一可以被直接连接到接合柱352，而不是通过集成电路芯片328上的接合焊盘351连接到接合柱352。
接合焊盘343说明了除探测区之外还具有多个引线接合区的接合焊盘的例子。接合焊盘338说明了接合焊盘的例子，该接合焊盘具有多个引线接合区，以致可以通过仅仅使用单一接合焊盘来从集成电路芯片330接受多个引线接合连接(从接合焊盘332和333)并且可以提供一个引线接合连接到PCB326(到接合柱344)。另外，具有多个引线接合区的接合焊盘可被用于提供同一个集成电路芯片的接合焊盘之间的电连接。举例，接合焊盘350允许连接到集成电路芯片330外部(到接合焊盘351)的一个引线接合连接以及连接到集成电路芯片330内部(到接合焊盘353)的一个引线接合连接。类似的，接合焊盘341允许连接到集成电路芯片328外部(到接合柱346)的一个引线接合连接以及连接到集成电路芯片328内部(到接合焊盘340)的一个引线接合连接。因此，可以看出，具有多个引线接合区以及在期望情况下还具有一个探测区的接合焊盘允许在连接多个集成电路芯片同时最低程度地影响芯片尺寸方面有更大的灵活性。另外，尽管没有说明所有的可能性，但是具有多个引线接合区以及在期望情况下还具有一个或多个探测区的接合焊盘可被置于集成电路芯片330或集成电路芯片328上。
在所示的实施例中，集成电路芯片330和集成电路芯片328是被纳入到同一个封装中的堆叠集成电路芯片。然而，在备选实施例中，集成电路芯片330可以是相邻于集成电路芯片328，而不是堆叠的。也就是说，在这里所述的接合焊盘可以被用于具有任意数目的采用任意结构的集成电路芯片的任何多芯片封装。另外应注意的是，可以使用此处所述的接合焊盘和电连接，将任意数量的集成电路芯片彼此之间连接起来。在本实施例中，在参考图21所述的接合焊盘还可被用于提供多个引线接合连接同时允许探针测试(如果在接合焊盘上存在探测区)。
另外，如图21中所示，集成电路芯片328被连接到PCB326的。然而，在备选实施例中，可以使用引线框架而不是PCB，在此接合柱344-348和352将位于一个引线框架上，如现在技术中所知的那样。另外，如现在技术中所知的那样，可以使用任何类型的引线接合来提供参考图21所述的连接。例如，球焊接、楔形焊剂、在柱头螺栓上球焊等等均可被采用。此外，可以使用现在技术中所知的任何类型的材料例如举例金、铝、铜和隔热的引线。
在前面的详细说明中，已经参考具体实施例描述了本发明。然而，本领域普通技术人员可理解的是做出各种改进和变更，而不会偏离如权利要求书中所阐明的范围。因此，说明书及附图应被认为是说明性的而不是限定作用，并且所有这样的改进都应被包括在本发明的范围内。
上文中已相对于具体实施例描述了益处、其它优点和问题的解决方案。然而，益处、其它优点和问题的解决方案，以及可能产生益处、其它优点和问题的解决方案或使之变得更显著的任何元素不应被认为是任一或所有权利要求的关键的、必需的、或必要的特征或元素。此处所使用的术语“包括”或它的其它任何变型均意图涵盖非排他性的包含，以致包含元素列表的过程、方法、制品或设备并不仅仅包括那些元素，还可能包含没有被明确列出的或是与这些工艺、方法、物件或设备存在固有联系的其他元素。

Claims (10)

1.一种集成电路，包括：
衬底；
衬底之上的钝化层；和
衬底之上的接合焊盘，所述接合焊盘包括：
用于将第一引线接合耦合到集成电路的第一引线接合区；和
用于将第二引线接合耦合到集成电路的第二引线接合区，
其中至少所述第一引线接合区的非外围部分位于钝化层之上，并且所述接合焊盘之下的钝化层具有开口，且该开口是任意形状的；并且其中所述衬底具有互连区域；并且
其中对于处在钝化层之上的接合焊盘的一部分，所述互连区域的至少一部分位于接合焊盘的该部分的下方。
2.如权利要求1所述的集成电路，其中衬底具有有源电路，并且其中所述有源电路的至少一部分位于处在钝化层之上的接合焊盘的一部分的下方。
3.如权利要求1所述的集成电路，其中所述集成电路被封装在多芯片封装中，且其中所述多芯片封装包括：
包括第二接合焊盘的第二集成电路；以及
用于电耦合第一引线接合区和第二接合焊盘的引线。
4.一种集成电路，包括：
衬底；
衬底之上的钝化层；和
衬底之上的接合焊盘，所述接合焊盘包括：
用于将第一引线接合耦合到集成电路的第一引线接合区，
用于将第二引线接合耦合到集成电路的第二引线接合区，以及
用于承受探针的探测区，
其中至少所述第一引线接合区的非外围部分位于钝化层之上。
5.一种用于形成集成电路的方法，包括：
提供衬底；
在所述衬底上形成钝化层；以及
在所述衬底上形成接合焊盘，其中所述形成接合焊盘的步骤包括：
形成第一引线接合区，其用于将第一引线接合耦合到集成电路；以及
形成第二引线接合区，其用于将第二引线接合耦合到集成电路，
其中至少所述第一引线接合区的非外围部分位于钝化层之上，以及其中所述接合焊盘之下的钝化层具有开口，且该开口是任意形状的；以及其中所述衬底具有互连区域，并且其中对于处在钝化层之上的接合焊盘的一部分，所述互连区域的至少一部分位于接合焊盘的该部分的下方。
6.一种多芯片封装，包括：
第一集成电路，包括
衬底；
衬底之上的钝化层；和
衬底之上的第一接合焊盘，所述第一接合焊盘包括：
用于将第一引线接合耦合到第一集成电路的第一引线接合区；和
用于将第二引线接合耦合到第一集成电路的第二引线接合区，
其中至少所述第一引线接合区的非外围部分位于钝化层之上；
第二集成电路，包括：
第二接合焊盘；以及
用于电耦合第一引线接合区和第二接合焊盘的第一引线。
7.一种集成电路，包括：
具有有源电路的衬底；
所述衬底之上的钝化层；以及
所述衬底之上的接合焊盘，所述接合焊盘包括：
用于将第一引线接合耦合到集成电路的第一引线接合区；和
用于将第二引线接合耦合到集成电路的第二引线接合区，
其中至少所述第一引线接合区的非外围部分位于钝化层之上，以及其中所述有源电路的至少一部分位于处在钝化层之上的接合焊盘的一部分之下。
8.如权利要求7所述的集成电路，其中所述衬底具有互连区域，并且其中所述互连区域的至少一部分位于处在钝化层之上的接合焊盘的一部分的下方。
9.一种用于形成集成电路的方法，包括：
提供具有有源电路的衬底；
在所述衬底上形成钝化层；以及
在所述衬底上形成接合焊盘，其中形成接合焊盘的步骤包括：
形成第一引线接合区，其用于将第一引线接合耦合到所述集成电路；以及
形成第二引线接合区，其用于将第二引线接合耦合到所述集成电路，
其中至少所述第一引线接合区的非外围部分位于钝化层之上；并且其中对于处在钝化层之上的接合焊盘的一部分，所述有源电路的至少一部分位于接合焊盘的该部分的下方。
10.一种用于形成集成电路的方法，包括：
提供衬底；
在所述衬底上形成钝化层；以及
在所述衬底上形成接合焊盘，其中所述形成接合焊盘的步骤包括：
形成第一引线接合区，其用于将第一引线接合耦合到集成电路；
形成第二引线接合区，其用于将第二引线接合耦合到集成电路；以及
用于承受探针的探测区，
其中至少所述第一引线接合区的非外围部分位于钝化层之上。
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