JP5148825B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP5148825B2 JP5148825B2 JP2005299674A JP2005299674A JP5148825B2 JP 5148825 B2 JP5148825 B2 JP 5148825B2 JP 2005299674 A JP2005299674 A JP 2005299674A JP 2005299674 A JP2005299674 A JP 2005299674A JP 5148825 B2 JP5148825 B2 JP 5148825B2
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Description
また、特許文献2には、ボンディング領域の形状を四角形として、四つの角の直角状態を認知して、ボンディングする位置を設定することが記載されている。
開口部が設けられた第1の絶縁膜と前記開口部内において露出している導電膜とを含むボンディングパッドを備え、
前記導電膜は、
第一領域と、
第二領域と、
前記第一領域と前記第二領域との間に設けられた第三領域と、
前記第一領域と前記第三領域との第一境界を示す第一エリア識別マークと、
前記第二領域と前記第三領域との第二境界を示す第二エリア識別マークと、を含み、
前記第三領域は、前記開口部内において、前記第一領域と前記第二領域にそれぞれ連結し、
前記第一エリア識別マークと前記第二エリア識別マークとが、前記開口部内において露出している前記導電膜の周縁部に設けられている、半導体装置が提供される。
前記半導体装置を準備する工程と、
前記第一エリア識別マークまたは前記第二エリア識別マークにより、前記第一境界または前記第二境界を検知し、検知された前記第一境界または前記第二境界に基づいて、前記第一領域と前記第三領域とから構成される領域または前記第二領域と前記第三領域とから構成される領域に試験用プローブを接触させる工程と、
試験用プローブを接触させる前記工程の後、検知された前記第一境界または前記第二境界に基づき、前記第二領域または前記第一領域に外部接続用導体を接合させる工程と、
を含む半導体装置の製造方法が提供される。
図1は、本実施形態の半導体装置の構成を示す平面図である。
図1に示した半導体装置100は、ボンディングパッド110と、ボンディングパッド110に設けられたエリア識別マークと、を含む。ボンディングパッド110は、第一領域125と、第二領域129と、第一領域125と第二領域129との間に設けられた第三領域127と、を含む。また、エリア識別マークは、第一領域125と第三領域127との第一境界(Q−Q’)を示す第一エリア識別マーク(第一切欠部121)と、第二領域129と第三領域127との第二境界(P−P’)を示す第二エリア識別マーク(第二切欠部123)と、を含む。そして、第一領域125と第二領域129とは、いずれも、試験用プローブ接触領域(プロービング傷111の形成領域)とすることができるように構成されている。
一つのボンディングパッド110には、プロービング傷111の形成領域であるプローブ接触領域と、ボンディング部113が形成されるボンディング領域とが設けられる。第一切欠部121および第二切欠部123は、プロービング傷111の形成領域とボンディング部113の形成領域とのエリア分けを行う。ボンディングパッド110は、第一切欠部121および第二切欠部123の位置に基づいて、ボンディング部113の形成領域とプロービング傷111の形成領域との境界を検知することができるように構成されている。第一切欠部121および第二切欠部123は、半導体装置100の素子形成面において、目視またはカメラもしくは顕微鏡を用いた観察等により識別可能に形成されている。
エリア識別マークは、凹部155の外周縁に設けられた切欠部(第一切欠部121および第二切欠部123)である。第一切欠部121および第二切欠部123は、ボンディングパッド110の周縁から内部に向かって凸状に形成されている。
半導体装置100を準備する工程、
第一切欠部121または第二切欠部123により、第一境界(Q−Q’)または第二境界(P−P’)を検知し、検知された境界に基づいて、第一領域125と第三領域127とから構成される領域または第二領域129と第三領域127とから構成される領域に試験用プローブを接触させる工程、および
試験用プローブを接触させる上記工程の後、検知された境界Q−Q’または境界P−P’に基づいて、第二領域129または第一領域125に外部接続用導体(図5に示したワイヤ131)を接合させる工程。
外部接続用導体は、たとえばワイヤボンディング接続に用いられる導体とする。
はじめに、シリコン基板101上に、配線層および層間絶縁膜等が積層した多層膜103を形成する。そして、多層膜103の所定の位置に、凹部155を形成する。このとき、凹部側壁157の平面形状が、所定の、つまり第一切欠部121と第二切欠部123を有する形状とする。
半導体装置100においては、一つのボンディングパッド110に第一切欠部121と第二切欠部123とが設けられている。このため、第一切欠部121または第二切欠部123を用いて、第一領域125または第二領域129と第三領域127との境界を確実に検知することができる。これらの二つの境界を検知することができるため、第一領域125と第二領域129のうちのいずれか一方をボンディング部113形成領域として任意に選択することができる。そして、選択した領域内に確実にボンディング部113を設けるとともに、選択しなかった領域内に確実にプロービングを行うことができる。このため、半導体装置100は、ボンディング部113の形成領域の選択の自由度に優れるとともに、試験用プローブの接触により生じた傷跡上にボンディングされることを防ぎ、信頼性に優れたボンディングを行うことが可能な構成となっている。
第一の実施形態においては、凹部側壁157に切欠部または突起部を設けて境界を検知する構成としたが、境界を示す態様はこれには限られない。たとえば、エリア識別マークが、凹部155に設けられた角部であってもよい。凹部155の角部をエリア識別マークとする構成として、たとえば、第一領域125および第二領域129に対して第三領域127が引っ込んだり張り出したりした構成が挙げられる。本実施形態では、こうした構成について説明する。
図12に示した半導体装置の基本構成は図8に示した半導体装置130と同様であるが、ボンディングパッド118に代えてボンディングパッド122が設けられた点が異なる。ボンディングパッド122においては、後退面145に代えて、凹部側壁157に前進面151が設けられている。そして、前進面151の一端が第一角部147をなし、第一領域125と第三領域127との境界を示す箇所となっている。また、前進面151の他端が第二角部149をなし、第二領域129と第三領域127との境界を示している。よって、図12においても、図8と同様の効果が得られる。
101 シリコン基板
103 多層膜
105 ポリイミド膜
107 Al膜
110 ボンディングパッド
111 プロービング傷
112 ボンディングパッド
113 ボンディング部
114 ボンディングパッド
116 ボンディングパッド
118 ボンディングパッド
120 パッケージ基板
121 第一切欠部
122 ボンディングパッド
123 第二切欠部
125 第一領域
127 第三領域
129 第二領域
130 半導体装置
131 ワイヤ
133 電源リング
135 ステッチ
137 第一突起部
139 第二突起部
141 第一角部
143 第二角部
145 後退面
147 第一角部
149 第二角部
151 前進面
153 開口部側壁
155 凹部
157 凹部側壁
210 ボンディングパッド
211 プロービング傷
213 ボンディング部
221 切欠部
225 第一領域
229 第二領域
Claims (9)
- 開口部が設けられた第1の絶縁膜と前記開口部内において露出している導電膜とを含むボンディングパッドを備え、
前記導電膜は、前記開口部内に露出している領域である露出領域に、
第一領域と、
第二領域と、
前記第一領域と前記第二領域との間に設けられた第三領域と、
前記第一領域と前記第三領域との第一境界を示す第一エリア識別マークと、
前記第二領域と前記第三領域との第二境界を示す第二エリア識別マークと、を含み、
前記第三領域は、前記開口部内において、前記第一領域と前記第二領域にそれぞれ連結し、
前記第一エリア識別マークは、前記露出領域の縁のうち、互いに対向している2箇所に位置し、
前記第一エリア識別マークを結ぶ直線によって、第一境界が定義され、
前記第二エリア識別マークは、前記露出領域の縁のうち、互いに対向している2箇所に位置し、
前記第二エリア識別マークを結ぶ直線によって、第二境界が定義されており、
前記第1の絶縁膜の下に設けられており、前記開口部内に凹部が設けられた第2の絶縁膜と、をさらに備え、
前記導電膜は、前記凹部の側壁上を覆うように設けられており、
前記第一エリア識別マークと前記第二エリア識別マークとが、前記凹部の側壁の形状に沿って、前記開口部内かつ前記導電膜の周縁部に設けられており、
上面視において、前記第一エリア識別マークは、前記開口部内部に設けられた前記凹部の前記側壁のうち、前記第一境界をまたぐ部分が内側又は外側に突出することにより形成され、かつ前記第二エリア識別マークは、前記側壁のうち、前記第二境界をまたぐ部分が内側又は外側に突出することにより形成されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記ボンディングパッドの平面形状が略矩形であって、前記矩形の辺に沿って、前記第一エリア識別マークと前記第二エリア識別マークとが並んで配置されている半導体装置。 - 開口部が設けられた第1の絶縁膜と前記開口部内において露出している導電膜とを含むボンディングパッドを備え、
前記導電膜は、前記開口部内に露出している領域である露出領域に、
第一領域と、
第二領域と、
前記第一領域と前記第二領域との間に設けられた第三領域と、
前記第一領域と前記第三領域との第一境界を示す第一エリア識別マークと、
前記第二領域と前記第三領域との第二境界を示す第二エリア識別マークと、を含み、
前記第三領域は、前記開口部内において、前記第一領域と前記第二領域にそれぞれ連結し、
前記第一エリア識別マークは、前記露出領域の縁のうち、互いに対向している2箇所に位置し、
前記第一エリア識別マークを結ぶ直線によって、第一境界が定義され、
前記第二エリア識別マークは、前記露出領域の縁のうち、互いに対向している2箇所に位置し、
前記第二エリア識別マークを結ぶ直線によって、第二境界が定義されており、
前記第1の絶縁膜の下に設けられており、前記開口部内に凹部が設けられた第2の絶縁膜と、をさらに備え、
前記導電膜は、前記凹部の側壁上を覆うように設けられており、
前記第一エリア識別マークと前記第二エリア識別マークとが、前記凹部の側壁の形状に沿って、前記開口部内かつ前記導電膜の周縁部に設けられており、
上面視において、前記開口部内部に設けられた前記凹部の前記側壁が、前記第一境界から前記第二境界に亘って内側又は外側に突出する矩形の突出部を有しており、当該突出部の2つの角部が、それぞれ前記第一エリア識別マーク及び前記第二エリア識別マークである、半導体装置。 - 開口部が設けられた第1の絶縁膜と前記開口部内において露出している導電膜とを含むボンディングパッドを備え、
前記導電膜は、前記開口部内に露出している領域である露出領域に、
第一領域と、
第二領域と、
前記第一領域と前記第二領域との間に設けられた第三領域と、
前記第一領域と前記第三領域との第一境界を示す第一エリア識別マークと、
前記第二領域と前記第三領域との第二境界を示す第二エリア識別マークと、を含み、
前記第三領域は、前記開口部内において、前記第一領域と前記第二領域にそれぞれ連結し、
前記第一エリア識別マークは、前記露出領域の縁のうち、互いに対向している2箇所に位置し、
前記第一エリア識別マークを結ぶ直線によって、第一境界が定義され、
前記第二エリア識別マークは、前記露出領域の縁のうち、互いに対向している2箇所に位置し、
前記第二エリア識別マークを結ぶ直線によって、第二境界が定義されており、
前記第1の絶縁膜の下に設けられており、前記開口部内に凹部が設けられた第2の絶縁膜と、をさらに備え、
前記導電膜は、前記凹部の側壁上を覆うように設けられており、
前記第一エリア識別マークと前記第二エリア識別マークとが、前記凹部の側壁の形状に沿って、前記開口部内かつ前記導電膜の周縁部に設けられており、
前記導電膜には、前記第一領域から前記第三領域までに跨るプロービング傷、または前記第二領域から前記第三領域までに跨るプロービング傷が形成されており、
前記第一領域及び前記第三領域のうち前記プロービング跡が形成されていない領域には、前記ボンディングワイヤが接続されている、半導体装置。 - 請求項1乃至4いずれか1項に記載の半導体装置において、前記第一領域、前記第三領域および前記第二領域がこの順に並置されており、前記ボンディングパッドの平面形状が、前記第一領域、前記第三領域および前記第二領域の並置方向に垂直に延在する中心軸に対して線対称である半導体装置。
- 請求項1乃至5いずれか1項に記載の半導体装置において、前記第一領域と前記第二領域とが、前記第三領域に対して略対称な形状を有する半導体装置。
- 請求項1乃至6いずれか1項に記載の半導体装置において、前記第一領域と前記第三領域とからなる領域の平面形状と、前記第二領域と前記第三領域とからなる領域の平面形状が略同一であるように構成された半導体装置。
- 請求項1乃至7いずれか1項に記載の半導体装置において、
前記第一領域、前記第二領域および前記第三領域の平面形状が、いずれも略矩形である半導体装置。 - 請求項1乃至8いずれか1項に記載の半導体装置を準備する工程と、
前記第一エリア識別マークまたは前記第二エリア識別マークにより、前記第一境界または前記第二境界を検知し、検知された前記第一境界または前記第二境界に基づいて、前記第一領域と前記第三領域とから構成される領域または前記第二領域と前記第三領域とから構成される領域に試験用プローブを接触させる工程と、
試験用プローブを接触させる前記工程の後、検知された前記第一境界または前記第二境界に基づいて、前記第二領域または前記第一領域に外部接続用導体を接合させる工程と、
を含む半導体装置の製造方法。
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