JP6901902B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6901902B2 JP6901902B2 JP2017087869A JP2017087869A JP6901902B2 JP 6901902 B2 JP6901902 B2 JP 6901902B2 JP 2017087869 A JP2017087869 A JP 2017087869A JP 2017087869 A JP2017087869 A JP 2017087869A JP 6901902 B2 JP6901902 B2 JP 6901902B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
図1は、本実施の形態の半導体装置が備える回路の一例を模式的に示す説明図である。また、図2は、図1に示す電界効果トランジスタの素子構造例を示す要部断面図である。
次に、図1に示す半導体装置PKG1のパッケージ構造について説明する。図3は、図1に示す半導体装置の上面図である。また、図4は、図3に示す半導体装置の下面図である。また、図5は、図3に示す封止体を取り除いた状態で、半導体装置の内部構造を示す透視平面図である。また、図6は、図5のA−A線に沿った断面図である。
は、ワイヤ12(詳しくはワイヤ12G)を介して電気的に接続されている。同様に、半導体チップ10のソース電極パッドSEとリード30Sは、ワイヤ(導電性部材、金属線)12(詳しくはワイヤ12S)を介して電気的に接続されている。ワイヤ12は、半導体チップ10の表面10t側の電極パッドとリード30とを接続する導電性部材であって、例えばアルミニウム(Al)を主成分としている。なお、ワイヤ12の構成材料には種々の変形例があり、例えば、銅(Cu)、銀(Ag)、あるいは金(Au)などの金属材料が主成分であっても良い。
ここで、半導体チップの電極パッドと、ワイヤとが接続される部分の詳細について説明する。図7は、図5に示す半導体チップに接続される複数のワイヤのうちの一部を拡大して示す拡大平面図である。また、図8は、図7のA−A線に沿った拡大断面図である。また、図9は、図7に示すソース電極パッド用の開口部の拡大平面図である。図10は図9に示す接合面にソースワイヤを接合した状態を示す拡大平面図である。また図11は、図10のA−A線に沿った拡大断面図である。また、図12は、図10に対する検討例である接合面の拡大平面図である。また、図13は、図10に示すワイヤの接合位置がずれた場合のループ部の周辺を拡大して示す拡大平面図である。図8では、半導体チップ10が備える多数のトランジスタQ1のうち、二個のトランジスタQ1を代表的に示している。また、図5に示すソース電極SEの一部分を露出させる複数の接合面のそれぞれ、およびこれらに接合される複数のワイヤ12のそれぞれは、互いに同様な構造になっている。したがって、図9および図10では、代表例として図7に示す接合面SEt1、およびこれに接続されるワイヤ12S1を用いて説明し、他の接合面(およびワイヤ)の構造については重複する説明を省略する。
次に、図1〜図11を用いて説明した半導体装置PKG1の製造工程について説明する。半導体装置PKG1は、図15に示すフローに沿って製造される。図15は、図1〜図11を用いて説明した半導体装置の製造工程の概要を示す説明図である。以下の説明では、半導体装置PKG1の構成部品の説明に際し、必要に応じて既に説明した図1〜図14を参照して説明する場合がある。
図15に示す半導体チップ準備工程では、図16に示す半導体チップ10を準備する。図16は、図15に示す半導体チップ準備工程で準備する半導体チップの表面(電極露出面)側の平面図である。
また、図15に示すリードフレーム準備工程では、図17に示すリードフレームLFを準備する。また、図17は、図15に示すリードフレーム準備工程で準備するリードフレームの一部を示す拡大平面図である。
次に、図15に示す半導体チップ搭載工程では、図5に示すように、リードフレームLFのダイパッド20に半導体チップ10を搭載する。
次に、図15に示すワイヤボンド工程では、図5に示すように、半導体チップ10の複数の電極パッド(ゲート電極パッドGEおよびソース電極パッドSE)と複数のリード30のそれぞれをワイヤ(金属ワイヤ)12を介して電気的に接続する。
次に、図15に示す封止工程では、図5に示す、半導体チップ10、ダイパッド20の一部、複数のリード30のそれぞれの一部分(図19に示すインナ部30M)、および複数のワイヤ12を絶縁樹脂で封止し、図18に示す封止体40を形成する。図18は、図15に示す封止工程において半導体チップおよびワイヤを封止する封止体を形成した状態を示す拡大平面図である。また、図19は、図18のA−A線に沿った断面において、成形金型内にリードフレームが配置された状態を示す拡大断面図である。また、図20は、封止工程において、樹脂に封止されたワイヤの周辺を示す拡大断面図である。
次に、図15に示すめっき工程では、図18に示すリードフレームLFを図示しないめっき溶液に浸し、封止体40から露出した金属部分(アウタ部)の表面に金属膜(図6に示す金属膜22および金属膜32)を形成する。
次に、図15に示す個片化工程では、図3に示す半導体装置PKG1(図3参照)に相当する組立体を図18に示すリードフレームLFの枠部LFfおよびタイバーLFtから分離して、個片化する。
図9および図10を用いて説明したように、接合面SEt1の露出面積を小さくした場合、ワイヤボンド工程においてワイヤの接合位置の位置ずれに対するマージンが小さくなる。このため、ワイヤボンド工程では、ワイヤ12S1の接合部12B1、12B2と接合面SEt1との位置関係を目視あるいはイメージセンサ等を用いて確認し、確認結果に基づいてワイヤボンド位置の微調整を行うことが好ましい。また、ワイヤ12S1の接合部12B1、12B2と接合面SEt1との位置関係を確認する場合、接合部12B1、12B2の近傍に位置ずれの程度を把握可能なマークがあれば、容易に微調整を実施できる。本変形例では、図9に示す接合面SEt1の一部分に位置ずれの程度を把握するマークを形成した構造例について説明する。図21は、図9に対する変形例を示す拡大平面図である。また、図22および図23は、図21に示す接合面にワイヤを接合した状態例を示す拡大平面図である。
また、上記実施の形態では、図9に示すように、開口部13H1の辺HS1および辺HS2の両方にくびれ部が形成された実施態様を取り上げて説明した。しかし、変形例としては、図26に示すように、辺HS1および辺HS2のうちいずれか一方にくびれ部が形成されていても良い。図26は、図13に対する変形例を示す拡大平面図である。
また、上記実施の形態では、例えば図8に示すように、一つのソース電極パッドSEの複数の部分が絶縁膜13に設けられた複数の開口部13H1において露出している実施態様について説明した。しかし、図8に示す接合面SEt1が、絶縁膜13に覆われた第1のソース電極パッド(電極、ソース電極)SE1の一部であり、接合面SEt2が、絶縁膜13に覆われた第2のソース電極パッド(電極、ソース電極)SE2の一部であっても良い。
また、上記実施の形態では、例えば図7に示すように、接合面SEt1と接合面SEt2の形状が長方形である場合について説明した。しかし、接合面SEt1と接合面SEt2の形状は長方形には限定されず、例えば、多角形や円形(楕円形を含む)など種々の変形例がある。
また、図示は省略するが、図7に対する他の変形例として、ワイヤ12S1が、三箇所以上で一つの接合面SEt1に接合されていても良い。この場合、ワイヤ12S1と接合面SEt1の接合面積が増えるので、ワイヤ12S1を介する導電経路のインピーダンスを低減できる。ワイヤ12S2についても同様である。
また、上記実施の形態では、パワー半導体装置が備えるパワートランジスタの例として、MOSFETを例示したが、種々の変形例を適用できる。例えば、MOSFETに代えて、IGBTを備えていても良い。この場合、上記実施の形態で説明したMOSFETのドレインをIGBTのコレクタと読み替え、MOSFETのソースをIGBTのエミッタと読み替えて適用できる。また、IGBTを利用する場合、負荷電流の流れ方向を制御するダイオード(FWD,Free Wheeling Diode)チップがIGBTチップとは別に搭載される場合が多い。このため、図5に示すダイパッド20上には、IGBTチップおよびFWDチップが搭載される。
また、上記実施の形態では、例えば図7に示す半導体チップ10のように、接合面SEt1および接合面SEt2の配列方向であるX方向と、接合面SEt1および接合面SEt2の延在方向であるY方向とが半導体チップ10の表面10tの外縁の各辺に沿って延びている実施態様について説明した。しかし、上記した各構成は、X方向およびY方向のそれぞれが半導体チップ10の表面10tの外縁の各辺に対して、直交以外の角度で交差している場合にも適用可能である。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。また、各変形例の一部分を抽出して組み合わせても良い。
10b 裏面(面、主面、下面)
10s 側面(面)
10t 表面(面、主面、上面)
11 ダイボンド材(接着材)
12、12G、12S,12S1,12S2 ワイヤ(金属ワイヤ、導電性部材、金属線)
12B1,12B2,12B3 接合部(接続部、ステッチ部)
12L1,12L2 ループ部(中間部、延在部)
13 絶縁膜(保護膜)
13H1,13H2,13H3,13H4,13H5 開口部
20 ダイパッド(金属板、チップ搭載部、放熱板)
20b 下面(面、主面、裏面、露出面、実装面)
20s,20s1,20s2 側面
20t 上面(面、主面、表面、チップ搭載面)
21,31 基材
22,32 金属膜(めっき膜)
30,30D,30G,30S リード(端子)
30b 下面(面)
30M インナ部(インナリード部、被封止部)
30s 側面
30t 上面(面、ワイヤボンディング面)
30W ワイヤ接合部((リードポスト、パッド、ボンディングパッド、ワイヤ接続部、接合部)
30X アウタ部(アウタリード部、露出部)
40 封止体(樹脂封止体、樹脂体、モールド樹脂)
40b 下面(実装面)
40s 側面
40t 上面
62 成形金型
62B 下型(第2金型)
62C キャビティ
62T 上型(第1金型)
CH チャネル形成領域
D ドレイン
DE ドレイン電極(電極)
EP エピタキシャル層
G ゲート電極
GE ゲート電極パッド(電極、ゲート電極)
GEt,SEt1,SEt2,SEt3,SEt4,SEtH 接合面(露出面、接合部)
GI ゲート絶縁膜
GP1,GP2 離間距離
GP3 長さ
GW 配線(ゲート配線)
HS1,HS2,HS3,HS4 辺(部分)
HSM1,HSM2,HSM3,HSM4 突出部
HSM5,HSM6 窪み部
HSP1,HSP2,HSP3,HSP4,HSP5,HSP21,HSP22,HSP23,HSP24,HSP25 部分
HSM1,HSM2,HSM3,HSM4 突出部
HSM5,HSM6 窪み部
HSP1,HSP2,HSP3,HSP4,HSP5,HSP21,HSP22,HSP23,HSP24,HSP25 部分
HT1 ループ高さ
LE1 ループ長さ
LE2 長さ
LF リードフレーム
LFd デバイス形成部
LFf 枠部(フレーム部)
LFt タイバー
LM1,LM2,LM3,LM4,LM5,LM6 長さ
PKG1 半導体装置
PRM プローブ痕
Q1 トランジスタ
S ソース
SE ソース電極パッド(電極、ソース電極)
SR ソース領域
SW 配線(ソース配線)
TR1 トレンチ(開口部、溝)
VL1,VL2 延長線(仮想線)
WC1,WC2,WH1,WH2,WH3,WH4,WH5,WR1,WR2,WR3,WR4,WR5,WR6,WRP,WW1,WW2 幅(長さ、太さ)
WH 半導体基板
WHt 主面
WS1,WS2 距離
Claims (20)
- 第1接合面を有する電極パッドと、前記電極パッドの前記第1接合面を露出する第1開口部を備えた絶縁膜と、を有する半導体チップと、
前記電極パッドの前記第1接合面と接合される第1ワイヤと、
前記電極パッドの前記第1接合面に接触するように、前記半導体チップと、前記第1ワイヤを封止する封止体と、を有し、
前記第1接合面は、金属から成り、
前記封止体は、絶縁材料から成り、
平面視において、前記第1接合面は、第1領域、第2領域、および前記第1領域と前記第2領域との間にある第3領域、を有し、
前記第1ワイヤは、前記第1接合面の前記第1領域に接合される第1接合部、前記第1接合面の前記第2領域に接合される第2接合部、および、前記第1接合部と前記第2接合部の間に位置する第1中間部を有し、
平面視において前記第1中間部は第1方向に沿って延在し、かつ、前記第1中間部と前記第3領域とは互いに離間し、
平面視において、前記第1方向に直交する第2方向における前記第1領域の幅と、前記第2方向における前記第2領域の幅は、前記第2方向における前記第3領域の幅よりも大きい、半導体装置。 - 請求項1において、
前記第1開口部は、前記第2方向において前記第1開口部の一方の端部にあり、かつ、前記第1方向に延在する第1辺と、前記第1辺の反対側の端部にあり、かつ、前記第1方向に延在する第2辺と、を有し、
前記第1辺は、前記第1領域と前記第3領域の間、および前記第2領域と前記第3領域の間においてそれぞれ屈曲し、
前記第2辺は、前記第1領域と前記第3領域の間、および前記第2領域と前記第3領域の間においてそれぞれ屈曲する、半導体装置。 - 請求項1において、
平面視において、前記第2方向における前記第3領域の幅は、前記第2方向における前記第1ワイヤの前記第1中間部の幅以下である、半導体装置。 - 請求項1において、
前記第2方向において、前記第1ワイヤの隣には第2ワイヤが配置され、
前記第2方向における前記第1ワイヤと前記第2ワイヤとの離間距離は、前記第1ワイヤの線径より小さい、半導体装置。 - 請求項1において、
平面視において、前記第1開口部は、前記第1方向に沿って延在する第1辺、および前記第1辺の反対側の第2辺と、を有し、
前記第1辺は、平面視において、前記第1領域に沿って延在する第1部分と、前記第2領域に沿って延在する第2部分と、前記第1部分と前記第2部分との間に位置し、かつ、前記第3領域に沿って延在する第3部分と、を有し、
前記第1辺の前記第1部分の延長線と前記第3部分との間の幅は、前記第1辺の前記第3部分と前記第1ワイヤの前記第1中間部との間の幅より大きい、半導体装置。 - 請求項1において、
平面視において、前記第1開口部は、前記第1方向に沿って延在する第1辺、および前記第1辺の反対側の第2辺と、を有し、
前記第1辺は、平面視において、前記第1領域に沿って延在する第1部分と、前記第2領域に沿って延在する第2部分と、前記第1部分と前記第2部分との間に位置し、かつ、前記第3領域に沿って延在する第3部分と、を有し、
前記第2辺は、平面視において、前記第1領域に沿って延在する第4部分と、前記第2領域に沿って延在する第5部分と、前記第4部分と前記第5部分との間に位置し、かつ、前記第3領域に沿って延在する第6部分と、を有し、
前記第1辺の前記第3部分は、前記第1部分の延長線と前記第2辺との間にあり、
前記第2辺の前記第6部分は、前記第4部分の延長線と前記第1辺との間にある、半導体装置。 - 請求項1において、
前記第1接合面の前記第1領域は、前記第2方向に沿って突出する第1突出部を有し、
平面視において、前記第1方向における前記第1突出部の長さは、前記第1方向における前記第1領域の長さより短い、半導体装置。 - 請求項7において、
平面視において、前記第2方向における前記第1突出部の長さは、前記第1方向における前記第1突出部の長さより短い、半導体装置。 - 請求項1において、
平面視において、前記第1開口部は、前記第1方向に沿って延在する第1辺、および前記第1辺の反対側の第2辺と、を有し、
前記第1接合面の前記第1領域は、前記第1開口部の前記第1辺において前記第2方向に沿って突出する第1突出部と、前記第1開口部の前記第2辺において前記第2方向に沿って突出する第2突出部と、を有し、
平面視において、前記第1方向における前記第1突出部の長さおよび前記第1方向における前記第2突出部の長さのそれぞれは、前記第1方向における前記第1領域の長さより短い、半導体装置。 - 請求項9において、
前記第1接合面の前記第2領域は、前記第1開口部の前記第1辺において前記第2方向に沿って突出する第3突出部と、前記第1開口部の前記第2辺において前記第2方向に沿って突出する第4突出部と、を有し、
平面視において、前記第1方向における前記第3突出部の長さおよび前記第1方向における前記第4突出部の長さのそれぞれは、前記第1方向における前記第2領域の長さより短い、半導体装置。 - 請求項1において、
前記第1接合面の前記第3領域は、前記第2方向に沿って前記第3領域に向かって窪む第1窪み部を有し、
平面視において、前記第1方向における前記第1窪み部の長さは、前記第1方向における前記第3領域の長さより短い、半導体装置。 - 請求項1において、
平面視において、前記第1開口部は、前記第1方向に沿って延在する第1辺、および前記第1辺の反対側の第2辺と、を有し、
前記第1接合面の前記第3領域は、前記第1開口部の前記第1辺において前記第2方向に沿って前記第2辺に向かって窪む第1窪み部と、前記第1開口部の前記第2辺において前記第2方向に沿って前記第2辺に向かって窪む第2窪み部と、を有し、
平面視において、前記第1方向における前記第1窪み部の長さおよび前記第2窪み部の長さのそれぞれは、前記第1方向における前記第3領域の長さより短い、半導体装置。 - 請求項1において、
前記第3領域は、試験用の端子が食い込んだ痕跡を有している、半導体装置。 - 第1接合面を有する電極パッドと、前記電極パッドの前記第1接合面を露出する第1開口部を備えた絶縁膜と、を有する半導体チップと、
前記電極パッドの前記第1接合面と接合される第1ワイヤと、
前記電極パッドの前記第1接合面に接触するように、前記半導体チップと、前記第1ワイヤを封止する封止体と、を有し、
前記第1接合面は、金属から成り、
前記封止体は、絶縁材料から成り、
前記第1ワイヤは、前記第1接合面に接合される第1接合部、前記第1接合面に接合される第2接合部、および、前記第1接合部と前記第2接合部の間に位置する第1中間部を有し、
平面視において前記第1中間部は第1方向に沿って延在し、かつ、前記第1中間部と前記第1接合面とは互いに離間し、
平面視において、前記第1開口部は、前記第1方向に沿って延在する第1辺、および前記第1辺の反対側の第2辺と、前記第1方向に直交する第2方向に沿って延在する第3辺と、前記第3辺の反対側の第4辺と、を有し、
前記第1辺は、平面視において、前記第1方向に沿って延在する第1部分と、前記第1方向に沿って延在する第2部分と、前記第1部分と前記第2部分との間に位置し、かつ、前記第1方向に沿って延在する第3部分と、を有し、
平面視の前記第2方向において、前記第1接合部は、前記第1辺の前記第1部分と前記第2辺との間に位置し、
平面視の前記第2方向において、前記第2接合部は、前記第1辺の前記第2部分と前記第2辺との間に位置し、
平面視の前記第2方向において、前記第1中間部は、前記第1辺の前記第3部分と前記第2辺との間に位置し、
平面視において、前記第1辺の前記第1部分から前記第2辺までの前記第2方向における長さ、および前記第1辺の前記第2部分から前記第2辺までの前記第2方向における長さ、のそれぞれは、前記第3部分から前記第2辺までの前記第2方向における長さより大きい、半導体装置。 - 請求項14において、
前記第2辺は、平面視において、前記第1方向に沿って延在する第4部分と、前記第1方向に沿って延在する第5部分と、前記第1部分と前記第2部分との間に位置し、かつ、前記第1方向に沿って延在する第6部分と、を有し、
前記第1辺の前記第3部分は、前記第1部分の延長線と前記第2辺との間にあり、
前記第2辺の前記第6部分は、前記第4部分の延長線と前記第1辺との間にある、半導体装置。 - 請求項14において、
前記第1接合面のうち、前記第1ワイヤの前記第1中間部と重畳する領域は、試験用の端子が食い込んだ痕跡を有している、半導体装置。 - 以下の工程を有する半導体装置の製造方法:
(a)第1表面と、前記第1表面の反対側の第1裏面と、第1接合面を有する電極パッドと、前記第1表面を持ち、前記電極パッドの前記第1接合面を露出する第1開口部を備えた絶縁膜と、を有する半導体チップを準備する工程と、
(b)前記半導体チップが固定されるチップ搭載部と、前記チップ搭載部と離間する第1リードと、を有するリードフレームを準備する工程と、
(c)前記(a)工程と、前記(b)工程の後、前記半導体チップの前記第1裏面と前記チップ搭載部とが向い合うように前記半導体チップを前記チップ搭載部に搭載する工程と、
(d)前記(c)工程の後、前記半導体チップの前記第1接合面に第1ワイヤを接合する工程と、
(e)前記(d)工程の後、前記電極パッドの前記第1接合面に接触するように、前記半導体チップと、前記第1ワイヤを、絶縁材料で封止する工程と、を有し、
前記第1接合面は、金属から成り、
平面視において、前記第1接合面は、第1領域、第2領域、および前記第1領域と前記第2領域との間にある第3領域、を有し、
前記(d)工程には、
(d1)前記第1ワイヤの第1接合部を前記第1接合面の前記第1領域に接合する工程と、
(d2)前記(d1)工程の後、前記第1接合部に連結され、かつ、第1方向に沿って延びる前記第1ワイヤの第1中間部を、前記第1接合面の前記第3領域を跨ぐように成形する工程と、
(d3)前記(d2)工程の後、前記第1ワイヤの前記第1中間部に連結される前記第1ワイヤの第2接合部を前記第1接合面の前記第2領域に接合する工程と、
が含まれ、
前記第1ワイヤの前記第1中間部と前記第3領域とは互いに離間し、
平面視において、前記第1方向に直交する第2方向における前記第1領域の幅と、前記第2方向における前記第2領域の幅は、前記第2方向における前記第3領域の幅よりも大きい、半導体装置の製造方法。 - 請求項17において、
前記第1接合面の前記第1領域は、前記第2方向に沿って突出する第1突出部を有し、
平面視において、前記第1方向における前記第1突出部の長さは、前記第1方向における前記第1領域の長さより短く、
前記(d)工程には、
(d4)前記(d1)工程の後、前記第1ワイヤと前記第1接合面との位置関係を確認し、前記確認した結果に基づいてワイヤボンディング位置を調整する工程が含まれ、
前記(d4)工程では、前記第2方向における前記第1突出部の長さを参照して、前記第1ワイヤの前記第1接合部の位置のずれ量を確認する、半導体装置の製造方法。 - 請求項17において、
前記第1接合面の前記第3領域は、前記第2方向に沿って前記第3領域に向かって窪む第1窪み部を有し、
平面視において、前記第1方向における前記第1窪み部の長さは、前記第1方向における前記第3領域の長さより短く、
前記(d)工程には、
(d4)前記(d1)工程の後、前記第1ワイヤと前記第1接合面との位置関係を確認し、前記確認した結果に基づいてワイヤボンディング位置を調整する工程が含まれ、
前記(d4)工程では、前記第2方向における前記第1窪み部の長さと、前記第1ワイヤの前記第1中間部の位置関係を確認する、半導体装置の製造方法。 - 請求項17において、
前記(a)工程には、前記第3領域に試験用の端子を接触させる工程が含まれる、半導体装置の製造方法。
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CN201810226534.4A CN108807323A (zh) | 2017-04-27 | 2018-03-19 | 半导体器件及其制造方法 |
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JPS61290747A (ja) | 1985-06-19 | 1986-12-20 | Hitachi Ltd | 電子回路装置 |
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EP0882308B1 (de) | 1996-11-11 | 2004-02-11 | Infineon Technologies AG | Optimierung der leistungsverbindung zwischen chip und leiterrahmen für leistungsschalter |
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US7443018B2 (en) | 2005-11-09 | 2008-10-28 | Stats Chippac Ltd. | Integrated circuit package system including ribbon bond interconnect |
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US9147628B2 (en) * | 2012-06-27 | 2015-09-29 | Infineon Technoloiges Austria AG | Package-in-packages and methods of formation thereof |
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