TWI745516B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI745516B
TWI745516B TW106146132A TW106146132A TWI745516B TW I745516 B TWI745516 B TW I745516B TW 106146132 A TW106146132 A TW 106146132A TW 106146132 A TW106146132 A TW 106146132A TW I745516 B TWI745516 B TW I745516B
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Taiwan
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wire
area
bonding
length
semiconductor device
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TW106146132A
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TW201839932A (zh
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佐藤幸弘
清原俊範
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日商瑞薩電子股份有限公司
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Abstract

本發明之課題在於提高半導體裝置之性能。 本發明之一實施形態之半導體裝置具有於形成於半導體晶片之絕緣膜之開口部13H1中於一個接合面SEt1之複數個部位接合之導線12。又，半導體裝置具有以與接合面SEt1相接之方式密封上述半導體晶片及導線12之密封體。接合面SEt1具有：供接合導線12之接合部12B1之區域SER1、供接合導線12之接合部12B2之區域SER2、及位於區域SER1與區域SER2之間的區域SER3。區域SER3之寬度WH3小於區域SER1之寬度WH1及區域SER2之寬度WH2。

Description

半導體裝置及其製造方法
本發明係關於半導體裝置及其製造方法，例如關於藉由樹脂密封體密封連接有導線之引腳之一部分的半導體裝置。
日本專利特表2000-503491號公報(專利文獻1)中，記載一種於位於半導體晶片之上表面之複數個電極墊連接有複數條導線之功率半導體裝置。又，專利文獻1中記載一種於複數個電極墊中之一部分，於電極墊之複數個部位連接導線的構造。 又，日本專利特開昭61-290747號公報(專利文獻2)中記載一種將接合墊與測試用焊墊經由配線而連接之構造。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特表2000-503491號公報 [專利文獻2]日本專利特開昭61-290747號公報
[發明所欲解決之問題] 本案發明者對提高半導體裝置之性能進行探討。例如，有於半導體晶片之一個電極墊之複數個部位接合一條導線之技術。半導體晶片之電極形成面由作為保護膜之絕緣膜覆蓋，且於電極墊之複數個部位接合導線之情形時，藉由擴大形成於保護膜之開口部之開口面積，較易於連接導線。然而，已知由於構成電極墊之金屬材料與密封導線之樹脂材料之接合界面之強度較弱，因而電極墊之中未連接導線且自保護膜露出之部分會與密封導線之樹脂(樹脂密封體)剝離。即使電極墊與樹脂密封體剝離，亦不會立即有損半導體裝置之功能。然而，若考量半導體裝置之製品壽命等長期之製品品質，較佳為能夠抑制電極墊與樹脂密封體之剝離。 其他之課題與新穎之特徵可根據本說明書之記述及隨附圖式予以明瞭。 [解決問題之技術手段] 一實施形態之半導體裝置具有於形成於半導體晶片之絕緣膜之第1開口部中於一個接合面之複數個部位接合之導線。又，半導體裝置具有以與上述接合面相接之方式密封上述半導體晶片及上述導線之密封體。上述接合面具有供接合上述導線之第1接合部之第1區域、供接合上述導線之第2接合部之第2區域、及位於上述第1區域與上述第2區域之間的第3區域。上述第3區域之寬度小於上述第1區域之寬度及上述第2區域之寬度。 [發明之效果] 根據上述一實施形態，可提高半導體裝置之性能。
(本案之記載形式、基本用語、用法之說明) 於本案中，實施形態之記載係根據需要且為了方便起見而分成複數個部分等記載，但除了特別明示為否定之情形以外，該等並非相互獨立者，不論記載之前後順序，均存在單一例之各部分之一者為另一者之一部分細節、一部分或全部之變化例等。又，原則上同樣部分省略反復之說明。又，實施形態之各構成要素除了特別明示為否定之情形、邏輯上限定為其數之情形及根據上下文明確為否定之情形以外，並非為必要者。 同樣地，於實施態樣等之記載中，關於材料、組成等，即使敘述為「包含A之X」等，但除了特別明示為否定及根據上下文明確為否定之情形以外，並非排除包含A以外之要素者。例如關於成分，則意指「包含以A為主要成分之X」等。例如，即使敘述為「矽構件」等，亦非僅限定於單純之矽，當然亦可為SiGe(矽-鍺)合金、或其他以矽為主要成分之多元合金、包含含有其他添加物等之構件者。又，即使敘述為鍍金、Cu層、鍍鎳等，但除了特別明示為否定之情形以外，並非僅為單一者，而可設為包含分別以金、Cu、鎳等為主要成分之構件者。 進而，提及特定之數值、數量時，除了特別明示為否定之情形、邏輯上限定於其數之情形、及根據上下文明確為否定之情形以外，可為超過該特定數值之數值，亦可為未達該特定數值之數值。 又，於實施形態之各圖中，以相同或類似之記號或參照編號表示相同或同樣之部分，原則上不重複說明。 又，於隨附圖式中，若加上陰影線等反而會變得繁雜、或與空隙之區別明確之情形時，有時即便為剖面但仍省略陰影線等。與此相關聯，於根據說明等明確之情形等時，有時即使為俯視下封閉之孔，仍省略背景輪廓線。再者，即使非剖面，但為了明示並非空隙，或為了明示區域之交界，而有附加陰影線或點圖案之情形。 於以下之說明中，使用「接觸」、「接著」、「接合」、「剝離」、及「連接」等用語，但根據以下之涵義而使用。「接觸」指可分離之兩個構件之至少一部分彼此相接之狀態。「接著」指可分離之兩個構件(被著材)之至少一部分經由接著劑彼此結合、固定之狀態。又，「接合」指可分離之兩個構件(被著材)之至少一部分彼此結合、固定之狀態。上述「結合」包含錨定效應等之機械結合、利用分子間力等物理性相對作用之結合、及利用共價鍵結等化學性相互作用之結合。又，「接合」除了於被著材之間介隔有其他構件(例如接著劑)之情形以外，亦包含不介置其他構件之情形。即，「接合之狀態」包含「接著之狀態」。又，「剝離」指解除上述之「結合」狀態而變化為可分離之狀態。又，於簡單記載為「剝離」之情形時，除了於兩個構件之接合部分之整體解除結合之情形以外，並包含於接合部分之一部分解除結合之狀態。又，「連接」指兩個構件連通之狀態(連接路徑不中途分斷而連續地相連)。不論是否有另外之構件介置於兩個構件之間。例如「A構件與B構件電性連接之狀態」意指A構件與B構件可電性導通之狀態，且包含A構件與B構件之間介置有C構件之情形。又，單純之「A構件與B構件連接之狀態」意指將A構件與B構件固定之狀態，且亦包含A構件與B構件之間介置有C構件之情形。又，例如，「將A構件與B構件連接之狀態」亦包含將A構件與B構件作為無法分離之一體物形成，而在形狀或功能上有所區別之情形。如此，亦有將A構件與B構件作為一體物形成之狀態記載為「連結」之情形。 又，於以下之說明中，於記載為焊料、焊材、焊料材料、或焊料成分之情形時，指例如含鉛(Pb)之Sn-Pb焊料、或實質上不含Pb之所謂無鉛焊料。作為無鉛焊料之一例，列舉例如僅錫(Sn)、錫-鉍(Sn-Bi)、或錫-銅-銀(Sn-Cu-Ag)、錫-銅(Sn-Cu)等。此處，無鉛焊料意指鉛(Pb)之含有量為0.1 wt%以下者，該含有量係定為RoHS(Restriction of Hazardous Substances：有害物質限用)指令之基準。 於本實施形態中，作為半導體裝置之例，採用組入電源電路等電力控制電路之功率器件、或稱作功率半導體裝置之半導體裝置進行說明。以下說明之半導體裝置係組入電力轉換電路，作為開關元件發揮功能。 ＜電路構成例＞ 圖1係模式性顯示本實施形態之半導體裝置所具備之電路之一例的說明圖。又，圖2係顯示圖1所示之場效電晶體之元件構造例的要部剖視圖。 稱作功率半導體裝置之電力控制用之半導體裝置中，有具有例如二極體、半導體開關元件(thyrector)、或電晶體等半導體元件者。電晶體運用於各種領域，但如本實施形態所述，將組入例如流通1 A(安培)以上之大電流之電力控制電路內、作為開關元件而動作之電晶體稱為功率電晶體。本實施形態之半導體裝置PKG1如圖1所示，具有形成有功率電晶體即電晶體Q1之半導體晶片10。於圖1及圖2所示之例中，形成於半導體晶片10之電晶體Q1為場效電晶體，詳細而言為MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金屬氧化物半導體場效電晶體)。於功率半導體裝置中，電晶體作為例如開關元件使用。用於功率半導體裝置之MOSFET被稱為功率MOSFET。 將上述之MOSFET記載為廣泛表示於閘極絕緣膜上配置有包含導電性材料之閘極電極之構造的場效電晶體之用語。因此，即使記載為MOSFET，亦非排除氧化膜以外之閘極絕緣膜者。又，即使記載為MOSFET，亦非排除例如多晶矽等金屬以外之閘極電極材料者。 又，圖1所示之電晶體Q1由例如如圖2所示之n通道型場效電晶體形成。圖2係顯示圖1所示之場效電晶體之元件構造例的要部剖視圖。 於圖2所示之例中，例如於包含n型單晶矽之半導體基板WH之主面WHt上形成有n- 型之磊晶層EP。該半導體基板WH及磊晶層EP構成MOSFET之汲極區域(相當於圖1所示之汲極D之區域)。該汲極區域與形成於半導體晶片10之背面側之汲極電極DE電性連接。 於磊晶層EP上形成有p+ 型半導體區域即通道形成區域CH，於該通道形成區域CH上形成有n+ 型半導體區域即源極區域(相當於圖1所示之源極S之區域)SR。源極區域SR經由引出配線與形成於半導體晶片10之主面側之源極電極墊(電極、源極電極)SE電性連接。又，於積層於半導體基板WH上之半導體區域，形成有自源極區域SR之上表面貫通通道形成區域CH且到達磊晶層EP之內部的溝槽(開口部、溝渠)TR1。 又，於溝槽TR1之內壁形成有閘極絕緣膜GI。又，於閘極絕緣膜GI上，形成有以嵌入溝槽TR1之方式積層之閘極電極G。閘極電極G經由引出配線與半導體晶片10之閘極電極墊(電極、閘極電極)GE電性連接。 又，電晶體Q1由於隔著通道形成區域CH於厚度方向上配置汲極區域與源極區域SR，故於厚度方向上形成通道(以下稱為縱型通道構造)。於該情形時，與沿著主面WHt形成通道之場效電晶體相比，可降低俯視時之元件之佔有面積。因此，可降低半導體晶片10之平面尺寸。 又，於上述之縱型通道構造之情形時，於俯視時，由於可增加每單位面積之通道寬度，故可降低接通電阻。另，圖2係顯示場效電晶體之元件構造之圖，且於圖1所示之半導體晶片10中，並聯連接有具有例如圖2所示之元件構造之複數個(多個)電晶體Q1。藉此，可構成供如超過例如1安培之大電流流通之功率MOSFET。 如上所述，於並聯連接縱型通道構造之複數個電晶體Q1而構成MOSFET之情形時，MOSFET之電氣特性(主要為耐壓特性、接通電阻特性、電容特性)根據半導體晶片10之平面尺寸而變化。例如，若擴大半導體晶片10之平面面積，則並聯連接之電晶體Q1之單元數(即元件之數量)增加，因而接通電阻降低，電容增大。 另，於圖1及圖2中，例示MOSFET作為功率半導體裝置所具備之功率電晶體之例，但可應用各種變化例。例如，亦可取代MOSFET而具備絕緣閘雙極型電晶體(IGBT：Insulated Gate Bipolar Transistor)。 ＜半導體裝置＞ 接著，對圖1所示之半導體裝置PKG1之封裝構造進行說明。圖3係圖1所示之半導體裝置之俯視圖。又，圖4係圖3所示之半導體裝置之仰視圖。又，圖5係以去除圖3所示之密封體之狀態顯示半導體裝置之內部構造之透視俯視圖。又，圖6係沿著圖5之A-A線之剖視圖。 本實施形態之半導體裝置PKG1具有：半導體晶片10(參照圖5、圖6)、供搭載半導體晶片10之晶片焊墊(金屬板、晶片搭載部、散熱板)20(參照圖3～圖6)、及外部端子即複數條引腳(端子)30。半導體晶片10與複數條引腳30經由複數條導線12(參照圖5、圖6)電性連接。又，半導體晶片10、晶片焊墊20之上表面20t及複數條引腳30之內部(內引腳部、被密封部)30M(參照圖5、圖6)由密封體(樹脂密封體、樹脂體、模塑樹脂)40密封。 於本實施形態中，如圖5所示，於俯視時，複數條引腳30各者以沿著Y方向與晶片焊墊20並排地配置，且沿著與Y方向交叉(於圖5之例中係正交)之X方向並排之方式配置。又，於圖5所示之例中，於俯視時，複數條源極用之引腳(源極引腳、源極端子)30S、汲極用引腳(汲極引腳、汲極端子)30D、及閘極用引腳(閘極引腳、閘極端子)30G係以沿著X方向依序並排之方式排列。複數條引腳30各自具備由密封體40密封之內部30M、自密封體40露出之外部(外引腳部、露出部)30X。又，如圖6所示，複數條引腳30各自具有上表面30t及上表面30t之相反側之下表面30b。 又，如圖6所示，半導體晶片10具有：表面(面、上表面)10t、位於表面10t相反側之背面(面、下表面)10b。又，如圖5所示，半導體晶片10之表面10t(或圖6所示之背面10b)於俯視時呈四角形，且於周緣部具有四個側面10s。於圖5所示之例中半導體晶片10於俯視時呈長方形，且長邊沿著X方向配置。 又，如圖5所示，於半導體晶片10之表面10t形成有與閘極電極G(參照圖1)電性連接之閘極電極墊GE、與源極S(參照圖1)電性連接之源極電極墊SE。又，如圖6所示，於半導體晶片10之背面10b形成有與汲極D(參照圖1)電性連接之汲極電極(電極)DE。於圖6所示之例中，半導體晶片10之背面10b整體為汲極電極DE。 如圖2所示，於將半導體晶片10設為縱型通道構造之情形時，可藉由將半導體晶片10之厚度薄化(減小圖6所示之表面10t與背面10b之距離)而降低接通電阻。另一方面，基於增大晶片焊墊20之熱電容之觀點，或擴大電流流通之導電路徑之剖面積之觀點，晶片焊墊20之厚度宜為較厚。因此，於圖6所示例中，晶片焊墊20之厚度厚於半導體晶片10之厚度。 又，半導體裝置PKG1具有供搭載半導體晶片10之晶片焊墊(金屬板、晶片搭載部、散熱板)20。如圖6所示，晶片焊墊20具有：經由固晶材11而搭載有半導體晶片10之上表面(面、主面、表面、晶片搭載面)20t、與上表面20t為相反側之下表面(面、主面、背面、露出面、安裝面)20b。於圖5所示之例中，半導體晶片10之平面尺寸(表面10t之面積)小於晶片焊墊20之平面尺寸(上表面20t之面積)。又，如圖4所示，晶片焊墊20於周緣部具有與下表面20b相連之複數個側面20s。 又，如圖5所示，晶片焊墊20與汲極電子即引腳30D一體形成。引腳30D為與圖1所示之汲極D電性連接之外部端子。如圖6所示，於半導體晶片10之背面10b形成有連接於MOSFET即電晶體Q1(參照圖1)之汲極D的汲極電極DE。汲極電極DE經由包含導電性材料之固晶材11而與晶片焊墊20電性連接。固晶材11係例如焊料、或銀(Ag)粒子等導電性粒子與樹脂之混合物之硬化物，即導電性樹脂。引腳30D連接於晶片焊墊20，且經由晶片焊墊20及固晶材11與半導體晶片10之汲極電極DE電性連接。又，引腳30D連接(連結)於晶片焊墊20，且於後述之半導體裝置之製造步驟中，具備作為支持晶片焊墊20之懸架引腳之功能。 另，於本實施形態中，由於晶片焊墊20之下表面20b自密封體40露出，故可將晶片焊墊20自身作為汲極端子處理。又，於本實施形態中，由於採用使用MOSFET作為功率電晶體之例之實施態樣進行說明，故引腳30及晶片焊墊20於電路上作為半導體裝置PKG1之汲極端子動作。然而，作為變化例，於將IGBT用於功率電晶體之情形時，於半導體晶片之背面形成有集極電極。因此，於功率電晶體為IGBT之情形時，引腳30與晶片焊墊20於電路上作為半導體裝置PKG1之集極端子動作。 又，如圖5所示，晶片焊墊20之複數個側面20s包含俯視時以與複數條引腳30各者對向之狀態設置、且由密封體40密封之側面20s1。又，複數個側面20s包含設置於側面20s1之相反側、自密封體40露出、且由金屬膜22(參照圖6)覆蓋之側面20s2。 又，如圖4及圖6所示，晶片焊墊20之下表面20b於密封體40之下表面40b側自密封體40露出。於圖4所示之例中，晶片焊墊20之下表面20b之面積為密封體40之下表面40b之面積以下。又，如圖3所示，晶片焊墊20之一部分於自晶片焊墊20之上表面20t側觀察之俯視時，自密封體40所具有之複數個側面40s中之一個側面40s朝向外側突出。且，如圖3及圖6所示，晶片焊墊20之上表面20t之一部分、及複數個側面20s中之一部分(至少側面20s2)自密封體40露出。如本實施形態般，可藉由擴大晶片焊墊20之平面尺寸，且使晶片焊墊20之一部分自密封體40露出，而提高半導體晶片10中產生之熱之散熱效率。 又，藉由連接於外部端子即引腳30D之晶片焊墊20之下表面20b自密封體40露出，可擴大電流流通之導通路徑之剖面積。因此，可降低導通路徑中之阻抗。尤其於引腳30D為與半導體裝置PKG1所具有之電路之輸出節點對應之外部端子之情形時，其較佳之點在於，藉由降低連接於引腳30D之導通路徑之阻抗成分而可直接降低輸出配線之電力損失。 晶片焊墊20具有包含與複數條引腳30相同之金屬材料例如銅(Cu)、或以銅(Cu)為主要成分之合金材料之基材21。又，複數條引腳30各自具有包含與晶片焊墊20相同之金屬材料，例如銅(Cu)、或以銅(Cu)為主要成分之合金材料之基材31。 又，晶片焊墊20中之自密封體40露出之部分(外部、露出部)由金屬膜22覆蓋。同樣地，引腳30之中自密封體40露出之部分(外部30X)由金屬膜32覆蓋。該金屬膜22及金屬膜32係於將半導體裝置PKG1安裝於安裝基板時，用以提高作為連接材料使用之焊料材之濡濕性之金屬膜。金屬膜22及金屬膜32為例如藉由電解鍍覆法形成之鍍覆金屬膜。詳如後述，但金屬膜22及金屬膜32包含例如含錫(Sn)之焊料材料。 又，圖5及圖6所示之固晶材(接著材)11為用以將半導體晶片10固定於晶片焊墊20上且電性連接半導體晶片10與晶片焊墊20之導電性構件(固晶材)。固晶材11可使用例如焊料材料。或，固晶材11可為含複數個銀(Ag)粒子(Ag填料)之所謂稱為銀(Ag)膏之導電性樹脂接著材。另，雖省略圖示，但可將與固晶材11之接著性高於晶片焊墊20之基材即銅(Cu)或銅合金之金屬膜(省略圖示)形成於晶片焊墊20之上表面20t之一部分。藉此，可提高固晶材11與晶片焊墊20之接著強度。 又，如圖5所示，半導體晶片10之閘極電極墊GE與引腳30G經由導線12(詳細而言為導線12G)電性連接。同樣地，半導體晶片10之源極電極墊SE與引腳30S經由導線(導電性構件、金屬線)12(詳細而言為導線12S)電性連接。導線12為連接半導體晶片10之表面10t側之電極墊與引腳30之導電性構件，以例如鋁(Al)為主成分。另，導線12之構成材料有各種變化例，例如亦可將銅(Cu)、銀(Ag)、或金(Au)等金屬材料作為主成分。 如圖5所示，導線12G之一端接合於半導體晶片10之閘極電極墊GE。另一方面，導線12G之與上述一端相反側之另一端接合於形成於引腳30G之一部分之導線接合部(引腳柱、焊墊、接合墊、導線連接部、接合部)30W之上表面30t。 又，如圖5及圖6所示，導線12S之一端接合於半導體晶片10之源極電極墊SE。另一方面，導線12S之與上述一端相反側之另一端接合於形成於引腳30S之一部分之導線接合部(引腳柱、焊墊、接合墊、導線連接部、接合部)30W之上表面30t。 又，於功率半導體裝置中，於連接於源極電極墊SE之配線路徑流通較連接於閘極電極墊GE之配線路徑更大的電流。因此，於圖5所示之例中，導線12S之粗細粗於導線12G之粗細。另，導線12之形狀或條數不限定於圖5所示之態樣，而有各種變化例。例如，導線12G與導線12S之粗細可為相同。又，例如源極電極墊SE與引腳30S亦可經由複數條導線12S而電性連接。詳如後述，但於本實施形態中，於半導體晶片10之源極電極墊SE連接有複數條導線12S。如此，可藉由將複數條較粗之導線12S連接於源極電極墊SE，而降低與圖1所示之源極S相連之導電路徑之阻抗。 又，半導體晶片10、複數條引腳30、及複數條導線12由密封體40密封。密封體40為密封半導體晶片10及複數條導線12之樹脂體。詳細而言，如後述之圖7所示，密封體40係以與源極電極墊SE之露出面即接合面SEt1、SEt2相接之方式密封半導體晶片10及複數條導線12之樹脂體。密封體40具有：上表面40t(參照圖3、圖6)及位於上表面40t的相反側之下表面(安裝面)40b(參照圖4、圖6)。又，如圖3及圖4所示，密封體40之上表面40t(參照圖3)及下表面40b(參照圖4)各自於周緣部具有複數個側面40s。又，密封體40包含有機絕緣材料作為主要材料。例如，主要包含環氧系樹脂等熱硬化性樹脂。又，於本實施形態中，為了提高密封體40之特性(例如因熱影響所致之膨脹特性)，而於樹脂材料中混合有例如Silica(二氧化矽；SiO2 )粒子等填料粒子。 ＜導線與電極墊之連接部分之細節＞ 此處，對半導體晶片之電極墊、與導線連接之部分之細節進行說明。圖7係將連接於圖5所示之半導體晶片之複數條導線中之一部分放大顯示的放大俯視圖。又，圖8係沿著圖7之A-A線之放大剖視圖。又，圖9係圖7所示之源極電極墊用之開口部之放大俯視圖。圖10係顯示將源極導線接合於圖9所示之接合面之狀態之放大俯視圖。又，圖11係沿著圖10之A-A線之放大剖視圖。又，圖12係相對於圖10之探討例之接合面之放大俯視圖。又，圖13係將圖10所示之導線接合位置偏移之情形時之環部之周邊放大顯示的放大俯視圖。於圖8中，代表性顯示半導體晶片10所具備之多個電晶體Q1中之兩個電晶體Q1。又，使圖5所示之複數個源極電極墊SE之一部分露出之複數個接合面各者、及接合於該等之複數條導線12各者彼此為同樣之構造。因此，於圖9及圖10中，作為代表例使用圖7所示之接合面SEt1、及連接於其之導線12S1進行說明，關於其他之接合面(及導線)之構造省略重複之說明。 如圖7所示，於半導體晶片10形成具有表面10t之絕緣膜13。絕緣膜13為保護半導體晶片10之表面10t側之保護膜。絕緣膜(保護膜)13之上表面構成半導體晶片10之表面10t之大部分。於本實施形態之情形時，絕緣膜13為包含有機材料(有機絕緣材料)之有機膜，為例如聚醯亞胺膜。於絕緣膜13為有機膜之情形時，絕緣膜13與以有機絕緣材料為主成分之密封體40(參照圖6)之接合強度尤其提高。惟作為絕緣膜13之構成材料，有各種變化例。例如，可為聚醯亞胺膜以外之有機膜。又，例如，可為二氧化矽(SiO2 )或氮化矽(SiN)等無機絕緣膜。若考慮與密封體40之接合強度，則有機膜較無機絕緣膜更佳。然而，若和金屬材料與密封體40之接合強度相比，則無機絕緣膜與密封體40之接合強度較高。 又，於絕緣膜13形成有複數個開口部。於圖7所示之例中，於絕緣膜13形成有開口部13H1、開口部13H2、及開口部13H3。於開口部13H1、13H2、13H3各者中，形成於絕緣膜13下層之導體圖案之一部分露出。詳細而言，如圖8所示，於開口部13H1中，源極電極墊SE之一部分即接合面(露出面、接合部)SEt1自絕緣膜13露出。又，於開口部13H2中，源極電極墊SE之另一部分即接合面(露出面、接合部)SEt2自絕緣膜13露出。又，於開口部13H3中，閘極電極墊GE之一部分即接合面GEt自絕緣膜13露出。由於接合面SEt1、SEt2、及GEt各者自絕緣膜13露出，故構成半導體晶片10之表面10t之一部分。 又，如圖7所示，於接合面SEt1、SEt2、及GEt各者連接有導線12。詳細而言，於接合面SEt1接合有導線(源極導線)12S1，於接合面SEt2接合有導線(源極導線)12S2。又，於接合面GEt接合有導線(閘極導線)12G。圖7所示之複數條導線12之中，導線12S1在複數個部位(於圖7中係兩個部位)接合於接合面SEt1。於該情形時，由於導線12S1與接合面SEt1之接合面積(合計值)增大，故可降低經由導線12S1供給之電位供給路徑之阻抗。 詳細而言，如圖9所示，接合面SEt1具有區域(接合區域)SER1、區域(接合區域)SER2、及俯視時位於區域SER1與區域SER2之間之區域(中間區域、非接合區域)SER3。又，如圖10所示，導線12S1具有：接合於接合面SEt1之區域SER1之接合部(連接部、針腳部)12B1，接合於接合面SEt1之區域SER2之接合部(連接部、針腳部)12B2，及俯視時位於接合部12B1與接合部12B2之間之環部(中間部)12L1。 接合部12B1及接合部12B2各者為導線12中之熱壓接於半導體晶片10之電極墊之部分，且接合部12B1及接合部12B2各者之下表面接合於同一(共通)之接合面SEt1。又，環部12L1為連結接合部12B1與接合部12B2之部分，且與接合面SEt1分隔(參照圖8)。又，導線12S1具有接合於圖5所示之引腳30S之導線接合部30W之部分即接合部(連接部、針腳部)12B3。又，導線12S1位於圖7所示之接合部12B2與接合部12B3(參照圖5)之間，且具有連結接合部12B2及接合部12B3之環部12L2。 圖5所示之源極電極墊SE之一部分露出之四個接合面各者為與圖9及圖10所示之接合面SEt1同樣之構造。又，接合於使源極電極墊SE露出之四個接合面之四條導線12各者為與圖10所示之導線12S1同樣之構造。 又，圖7所示之複數條導線12中之連接於閘極電極墊GE之導線12G與導線12S1、12S2構造不同。即，導線12G於一個部位接合於一個接合面GEt。詳細而言，導線12G具有：接合於接合面GEt之接合部(連接部、針腳部)12B2，接合於引腳30G(參照圖5)之導線接合部30W(參照圖5)之接合部(連接部、針腳部)12B3(參照圖5)，及位於接合部12B2與接合部12B3之間之環部12L2。然而，導線12G不具有相當於導線12S1之接合部12B1及環部12L1之部分。於導線12G，傳送控制電晶體Q1(參照圖1)之開關動作之信號(閘極信號)。經由導線12G之傳送路徑與經由導線12S1之傳送路徑相比，即使傳送路徑中之阻抗增大，對開關電路之性能造成之影響亦相對較小。因此，導線12G於一個部位接合於一個接合面GEt。可藉由將導線12G與半導體晶片10之連接部分之構造簡單化而簡化製作步驟。 如圖8所示，於本實施形態之情形時，接合面SEt1及接合面SEt2各者為由絕緣膜13覆蓋之一個源極電極墊SE之一部分。換言之，接合面SEt1為源極電極墊SE之第1部分，接合面SEt2為源極電極墊SE之第2部分。於將複數條導線12連接於一個源極電極墊SE之情形時，考慮例如擴大開口部13H1之開口面積，於一個開口部13H1中露出之接合面SEt1接合導線12S1及導線12S2兩者之方法。於該情形時，可擴大將導線12接合於接合面SEt1時之位置偏移之裕度(容許範圍)。 然而，根據本案發明者之探討得知，因以有機系材料為主成分之密封體40(參照圖6)與以金屬材料(例如鋁)為主成分之源極電極墊SE之接合強度較低，故而容易於密封體40與源極電極墊SE之接合界面產生剝離。又，源極電極墊SE與密封體40兩者之間由於線膨脹係數之差較大，故會因施加於形成密封體40後之封裝之溫度變化而容易產生剝離。如上所述，於密封體40中，於樹脂材料中混合有二氧化矽粒子等之填料粒子。因此，可設為與半導體基板即矽(Si)同程度之線膨脹係數。然而，於該情形時，由於與包含金屬材料之源極電極墊SE之線膨脹係數之差較大，故仍容易產生剝離。 即使源極電極墊SE與密封體40剝離，亦不會立即有損半導體裝置PKG1(參照圖6)之功能。然而，若考量半導體裝置PKG1之製品壽命等長期之製品品質，則較佳為能夠抑制源極電極墊SE與密封體40之剝離。 如上所述，相較於金屬膜即源極電極墊SE與密封體40之接合界面，絕緣膜13與密封體40之接合界面較不易產生剝離。例如，於絕緣膜13包含有機材料即聚醯亞胺之情形時，與密封體40之密接性較高，從而可使接合強度提高。又，作為變化例，即使於絕緣膜13包含二氧化矽或氮化矽等無機絕緣材料之情形時，與金屬膜相比，亦可提高與密封體40之密接性。又，於絕緣膜13之材料為二氧化矽或氮化矽等無機絕緣膜之情形時，由於可降低與密封體40之線膨脹係數差，故不易產生剝離。 根據以上，基於抑制源極電極墊SE與密封體40之剝離之觀點，較佳減小源極電極墊SE自絕緣膜13露出之部分之面積。 又，根據本案發明者之探討得知，如圖7所示，以高密度配置複數條導線12之情形時，於相鄰之導線12間容易產生剝離。於本實施形態中，基於提高電性連接於源極電極墊SE之傳送路徑之電氣特性之觀點，高密度地將線徑粗於導線12G之複數條導線12S連接於源極電極墊SE。由於可藉由連接複數條線形較粗之導線12S，增大電性連接於源極電極墊SE之傳送路徑之剖面積，故可降低阻抗成分。 例如，於圖5所示之例中，顯示根據與半導體晶片10之表面10t之面積之關係而連接4條導線12S之例。然而，導線12S之條數不限定於4條，亦可未達4條、或為5條以上。又，於圖7所示之例之情形時，導線12S1、12S2之線徑為500 μm。又，於X方向上彼此相鄰之導線12S1、12S2之中心間距離為850 μm。又，環部12L1之導線12S1、12S2之寬度(X方向之導線12之長度)WW2與導線12S1、12S2之線徑相等，分別為500 μm。接合部12B1、12B2之導線12S1、12S2之寬度(X方向之導線12之長度)WW1(參照圖10)分別為600 μm左右。因此，彼此相鄰之導線12S1與導線12S2之分隔距離為150 μm(相鄰之接合部12B1間之距離WS1)～350 μm(相鄰之環部12L1間之距離WS2)左右。換言之，導線12S1與導線12S2之分隔距離小於導線12S1之線徑。 藉由供給經軟化之樹脂材料，將半導體晶片10、導線12及引腳30之一部分(內部30M)密封後使樹脂材料硬化，而形成圖6所示之密封體40。此時，如圖7所示，於以窄間距配置複數條導線12之情形時，於供給密封體40之原料樹脂時，施加於相鄰之導線12間之力小於施加於其他部分(例如半導體晶片10之表面10t之中未以導線12覆蓋之部分)之力。因此，於相鄰之導線12間之區域中，與其他區域相比，密封體40與半導體晶片10之接著強度較弱。因此，於相鄰之導線12之間之區域，與其他區域相比特別容易發生剝離。 根據本案發明者之探討得知，於相鄰之導線12間，於源極電極墊SE自絕緣膜13露出之部分之X方向長度(寬度)為150 μm以上之情形時，特別容易發生密封體40(參照圖6)與接合面SEt1之剝離。因此，本案發明者進行了使相鄰之導線12間之接合面之露出面積減低之技術之探討。另，「於相鄰之導線12間，源極電極墊SE自絕緣膜13露出之部分之X方向之長度(寬度)」指圖7所示之位於相鄰之導線12S間之區域之中未由絕緣膜13覆蓋之部分之X方向之長度。例如，於圖10所示之開口部13H1中，導線12S1之接合部12B1至開口部13H1之邊HS1之部分HSP1的長度WR1，相當於「於相鄰之導線12之間，源極電極墊SE自絕緣膜13露出之部分之X方向之長度(寬度)」。又，於開口部13H2(參照圖7)中，導線12S2(參照圖7)之接合部12B1至開口部13H2之邊HS2之一部分HSP21的長度WR2，相當於「於相鄰之導線12之間，源極電極墊SE自絕緣膜13露出之部分之X方向之長度(寬度)」。 首先，作為探討例如圖12所示，針對於具有長方形開口形狀之接合面SEtH中，減小X方向之寬度之情形進行探討。於圖10及圖12中，導線12S1之尺寸相同。即，X方向之環部12L1之導線12S1之寬度(X方向之導線12S1之長度)WW2為500 μm。又，接合部12B1及接合部12B2之導線12S1之寬度(X方向之導線12S1之長度)WW1分別為600 μm左右。又，X方向之接合面SEtH之寬度WH1(換言之，開口部13H1之開口寬度)為700 μm。 於俯視時，圖12所示之接合面SEtH之周緣部具有於X方向上位於開口部13H1之一端部之邊(部分)HS1、及邊HS1之位於相反側端部之邊(部分)HS2。如圖12所示之例，於將接合部12B1於X方向上接合於接合面SEtH之中心之情形時，邊HS1與接合部12B1間之寬度(X方向之接合面SEtH之露出面之長度)WR1及邊HS2與接合部12B1間之寬度(X方向之接合面SEtH之露出面之長度)WR2分別為50 μm。雖省略反復之說明，但於圖12中接合部12B2與邊HS1、HS2之關係亦與上述同樣。又，於圖12所示之例之情形時，邊HS1與環部12L1間之寬度(X方向之接合面SEtH之露出面之長度)WR3及邊HS2與環部12L1間之寬度(X方向之接合面SEtH之露出面之長度)WR4分別為100 μm。 如圖12所示，若可於X方向上將導線12S1接合於接合面SEtH之中心，則X方向上接合面SEtH自絕緣膜13及導線12S1露出之部分之寬度均未達150 μm。因此，不易產生上述之密封體40(參照圖6)與接合面SEtH之剝離。然而，於將導線12S1接合於接合面SEtH時，有時會產生位置偏移。因此，基於穩定地接合導線12S1之觀點，必須有50 μm左右之位置偏移之裕度(容許範圍)。 於圖12所示之例中，於導線12S1之連接位置朝邊HS1側或邊HS2側偏移50 μm之情形時，寬度WR3及寬度WR4中之任一者均為150 μm。於該情形時，得知於相鄰之導線12間，密封體40(參照圖6)與接合面SEtH之剝離明顯化。另一方面，於為了減小寬度WR3及寬度WR4而將接合面SEtH之寬度WH1設為小於700 μm之情形時，打線接合時之裕度減小。其結果，有可能因打線接合時之位置偏移之程度而導致接合部12B1或接合部12B2之一部分與絕緣膜13(參照圖7)重合。若導線12S1之一部分與絕緣膜13重合，將引起傳送路徑之電氣特性降低。 於本實施形態之情形，如圖9所示，接合面SEt1之平面形狀，換言之，開口部13H1之開口形狀非四角形。接合面SEt1於俯視時，於區域SER1與區域SER2之間具有收縮部(區域SER3)。 圖9所示之接合面SEt1(換言之為開口部13H1)之形狀可如下表現。於俯視時，X方向之區域SER1之寬度WH1及X方向之區域SER2之寬度WH2，大於X方向之區域SER3的寬度WH3。又，於俯視時，接合面SEt1(開口部13H1)具有於X方向上位於開口部13H1之一端部之邊(部分)HS1、及邊HS1之位於相反側端部之邊(部分)HS2。又，接合面SEt1(開口部13H1)具有於與X方向交叉(於圖9中為正交)之Y方向上位於開口部13H1之一端部之邊(部分)HS3、及邊HS3之位於相反側端部之邊(部分)HS4。邊HS3及邊HS4各者沿著X方向延伸。又，邊HS1及邊HS2各者沿著Y方向延伸，但於區域SER1與區域SER3之間及區域SER2於區域SER3之間彎曲，而非直線。換言之，接合面SEt1於邊HS1及邊HS2兩側具有收縮部。 於圖9所示之例中，區域SER1之寬度WH1及X方向之區域SER2之寬度WH2各自為700 μm。另一方面，區域SER3之寬度WH3為500 μm。 又，圖9所示之接合面SEt1(開口部13H1)之形狀可如下表現。於俯視時，接合面SEt1(開口部13H1)之邊HS1具有：沿著Y方向延伸之部分HSP1，沿著Y方向延伸之部分HSP2，及位於部分HSP1與部分HSP2之間且沿著Y方向延伸之部分HSP3。又，如圖10所示，於俯視時，接合部12B1位於邊HS1之部分HSP1與邊HS2之X方向之間。於俯視時，接合部12B2位於邊HS1之部分HSP2與邊HS2之X方向之間。又，如圖10所示，於俯視時，環部12L1位於邊HS1之部分HSP3與邊HS2之X方向之間。又，於俯視時，邊HS1之部分HSP1至邊HS2之X方向之長度(寬度WH1)、及邊HS1之部分HSP2至邊HS2之X方向之長度(寬度WH2)各者，皆大於部分HSP3至邊HS2之X方向之長度(寬度WH3)。 又，於圖10所示之例中，於俯視時，邊HS1之部分HSP1與部分HSP2位於相同之延長線VL1上。換言之，邊HS1之部分HSP2位於部分HSP1之延長線VL1上。又，邊HS1之部分HSP3位於部分HSP1之延長線VL1與邊HS2之間。又，於俯視時，邊HS2之部分HSP21與部分HSP22位於相同之延長線VL2上。換言之，邊HS2之部分HSP22位於部分HSP21之延長線VL2上。又，邊HS2之部分HSP23位於部分HSP21之延長線VL2與邊HS1之間。 如圖10所示，於接合部12B1於X方向上接合於接合面SEt1之中心之情形時，邊HS1與接合部12B1間之寬度(X方向之接合面SEt1之露出面之長度)WR1及邊HS1與接合部12B1間之寬度(X方向之接合面SEt1之露出面之長度)WR2分別為50 μm。雖省略反復之說明，但於圖10中，接合部12B2與邊HS1、HS2之關係亦與上述同樣。又，於圖10所示之例之情形時，邊HS1與環部12L1間之寬度(X方向之接合面SEt1之露出面之長度)及邊HS2與環部12L1間之寬度(X方向之接合面SEt1之露出面之長度)分別為0 μm。 因此，於圖10所示之例中，假定於導線12S1之連接位置朝邊HS1側偏移50 μm之情形時，X方向之邊HS2與環部12L1間之寬度(X方向之接合面SEt1之露出面之長度)為50 μm。又，於導線12S1之連接位置朝邊HS2側偏移50 μm之情形時，X方向之邊HS1與環部12L1間之寬度(X方向之接合面SEt1之露出面之長度)為50 μm。即，於將X方向之打線接合之位置精度之裕度設為50 μm之情形時，由於X方向之接合面SEt1之露出面之長度為50 μm以下，故可抑制密封體40(參照圖6)與接合面SEt1剝離。又，於將X方向之打線接合之位置精度之裕度設為50 μm之情形時，可抑制導線12S1之接合部12B1、12B2之一部分與絕緣膜13(參照圖7)重合。 另，於圖9所示之例中，接合面SEt1(開口部13H1)於區域SER3與區域SER1之間具有區域SER4。又，接合面SEt1(開口部13H1)於區域SER3與區域SER2之間具有區域SER5。於區域SER4與區域SER5中，X方向之寬度(長度)WH4、WH5非固定。於區域SER4中，寬度WH4之值係越接近區域SER3則越小，越接近區域SER1則越大。又，於區域SER5中，寬度WH4之值係越接近區域SER3則越小，越接近區域SER2則越大。 又，於圖9所示之例中，邊HS1具有位於部分HSP3與部分HSP1之間、且俯視時沿著與Y方向及X方向交叉之方向(第3方向)延伸之部分HSP5。又，邊HS1具有位於部分HSP3與部分HSP2之間、且沿著與Y方向及X方向交叉之方向(第4方向)延伸之部分HSP4。又，於俯視時，接合面SEt1(開口部13H1)之邊HS2具有：沿著Y方向延伸之部分HSP21，沿著Y方向延伸之部分HSP22，及位於部分HSP21與部分HSP22之間且沿著Y方向延伸之部分HSP23。又，邊HS2具有位於部分HSP23與部分HSP21之間，且俯視時沿著與Y方向及X方向交叉之方向(第5方向)延伸之部分HSP24。又，邊HS2具有位於部分HSP23與部分HSP22之間、且沿著與Y方向及X方向交叉之方向(第6方向)延伸之部分HSP25。 惟作為變化例，亦有無區域SER4及區域SER5之情形。於該情形時，圖9所示之邊HS1之部分HSP4、HSP5、及邊HS2之部分HSP24、HSP25各者沿著X方向延伸。 又，於圖9所示之例中，區域SER3之X方向之寬度WH3設為500 μm。如上所述，於圖7所示之相鄰之導線12之間，源極電極墊SE自絕緣膜13露出之部分之X方向之長度(寬度)為150 μm以上之情形時，特別容易發生密封體40(參照圖6)與接合面SEt1之剝離。因此，於將X方向之打線接合之位置精度之裕度設為50 μm之情形時，若寬度WH3未達700 μm，則即使考慮到位置偏移，接合面SEt1露出之部分之X方向之寬度亦未達150 μm。 惟基於確實地抑制圖9之區域SER3發生剝離之觀點，寬度WH3之值較佳為較小。例如，如圖13所示，考慮導線12S1之接合位置靠向開口部13H1之邊HS2側之情形。於圖13所示之例中，導線12S1之接合位置於X方向上偏向邊HS2側約40 μm左右。於該情形時，接合面SEt1之中應考量上述剝離之影響之部分，為接合面SEt1之中夾於開口部13H1之邊HS1與導線12S1之間之部分。邊HS1之部分HSP1與導線12S1之接合部12B1(參照圖10)間之寬度WR1為大約90 μm。又，於圖13所示之例之情形時，部分HSP1之延長線VL1與部分HSP3間之寬度(長度)WC1為100 μm。因此，邊HS1之部分HSP3與導線12S1之環部12L1之間之寬度(長度)WR3為大約40 μm。於該情形時，於區域SER3中，與圖9所示之區域SER1或區域SER2相比，不易發生上述剝離。 如此，基於抑制區域SER3之剝離之發生概率之觀點，部分HSP1之延長線VL1與部分HSP3間之寬度WC1較佳大於邊HS1之部分HSP3與導線12S1之環部12L1間之寬度WR3。同樣地，基於抑制區域SER3之剝離之發生概率之觀點，邊HS2之部分HSP21之延長線VL2與部分HSP23間之寬度WC2較佳大於邊HS2之部分HSP23與導線12S1之環部12L1間之寬度WR4。 另，於圖10所示之例之情形時，由於俯視時環部12L1之一邊與開口部13H1之部分HSP3之位置重合，故圖13所示之寬度WR3之值為0 μm。 又，如上所述，於相鄰之導線12之間容易發生圖6所示之密封體40與接合面SEt1之剝離。因此，於圖10所示之導線12S1與開口部13H1之邊HS3之間，即使於接合面SEt1之露出面積增大之情形時，亦不易發生上述之剝離。因此，於圖10所示之例中，Y方向之邊HS3與接合部12B1間之寬度(Y方向之接合面SEtH之露出面之長度)WR5，大於X方向之邊HS1與接合部12B1間之寬度(X方向之接合面SEtH之露出面之長度)WR1。寬度WR5大於X方向之邊HS2與接合部12B1間之寬度(X方向之接合面SEtH之露出面之長度)WR2。另，於圖10所示之例中，X方向之邊HS1與接合部12B1間之寬度WR1為50 μm。又，於圖13所示之例中，寬度WR1為大約90 μm。相對於此，圖10所示之寬度WR5之值為150 μm～200 μm左右。如圖10所示，於不易產生剝離之部分，可藉由增大寬度WR5之值而擴大打線接合時之位置偏移之裕度，因而可放寬打線接合步驟之製造條件。 又，基於使源極電極墊SE之露出面積減少之觀點，亦考量如圖14所示之探討例之構造。圖14係顯示相對於圖11之探討例之放大剖視圖。於圖14所示之探討例之情形時，與圖11所示之實施態樣之不同點在於：將一條導線12S接合於隔著絕緣膜13而分隔之接合面SEt3及接合面SEt4。換言之，於圖14所示之例中，於半導體晶片10之表面10t，導線12S於兩個部位接合於源極電極墊SE，且接合導線12S之接合面SEt3及接合面SEt4分隔。另一方面，於圖11所示之例中，導線12S1之接合部12B1與接合部12B2接合於未隔著絕緣膜13分隔之一個接合面SEt1。進而換言之，於圖14所示之例中，導線12S之環部12L1於源極電極墊SE之上方跨越絕緣膜13。另一方面，於圖11所示之例中，導線12S1之環部12L1於源極電極墊SE之上方未跨越絕緣膜13。於圖14所示之例之情形時，於表面10t，由於接合面SEt3、SEt4隔著絕緣膜13分隔，故與圖11所示之本實施形態之例相比，可進一步減低源極電極墊SE之露出面積。 然而，就比較圖11與圖14而得知之以下之點，以圖11所示之例者較佳。即，於圖14所示之例之情形時，導線12S之環部12L1必須為不與絕緣膜13接觸之形狀。因此，若將環部12L1之中與源極電極墊SE之露出面距離最遠之位置之距離規定為環部高度HT1，則可使圖11所示之例之環部高度HT1低於圖14所示之例之環部高度HT1。又，若將環部12L1之Y方向長度(換言之為接合部12B1與接合部12B2之分隔距離)定義為環部長度LE1，則可使圖11所示之例之環部長度LE1短於圖14所示之例之環部長度LE1。此係藉由能使圖11所示之例之環部高度HT1較為降低而實現。又，若能縮短環部長度LE1，則可縮短Y方向之源極電極墊SE之長度LE2(亦包含由絕緣膜13覆蓋之部分)。 因此，根據圖11所示之例，與圖14所示之例相比，由於可縮小源極電極墊SE之大小，故可減少半導體晶片10之平面面積(表面10t之面積)。若可縮小半導體晶片10之平面面積，則可獲得各種優點。例如，可縮小供搭載半導體晶片10之半導體裝置PKG1(參照圖5)之平面面積。又，例如，於製造半導體晶片時，可自一片半導體晶圓取得之半導體晶片之數量(取得效率)提高，因而半導體晶片之製造效率提高。 又，基於以下之點，較佳縮短源極電極墊SE之Y方向長度LE2。即，因源極電極墊SE與密封體40之線膨脹係數差而產生之應力係與源極電極墊SE之長度成比例地增大。因此，如圖11所示，根據本實施形態，由於可縮短Y方向之源極電極墊SE之長度LE2，故可降低因源極電極墊SE與密封體40之線膨脹係數差而產生之應力。其結果，可抑制因該應力產生之源極電極墊SE與密封體40之剝離。 又，圖6所示之密封體40係以與圖7所示之閘極電極墊GE之露出面即接合面GEt相接之方式形成。因此，基於抑制接合面GEt與密封體40之剝離之觀點，較佳縮小接合面GEt中之不與導線12G重合之區域之面積。惟於本實施形態之情形，導線12G之線徑(直徑)細於導線12S1、12S2之線徑，為例如125～150 μm左右。又，於閘極電極墊GE，於一個部位接合導線12G，於其他之部位則未接合。因此，閘極電極墊GE之接合面GEt之面積小於源極電極墊SE之接合面SEt1、SEt2各者之面積。例如，於圖7所示之例中，閘極電極墊GE之接合面GEt之面積相對於源極電極墊SE之接合面SEt1、SEt2各者之面積為1/4以下。換言之，接合面SEt1、SEt2各者之面積為接合面GEt之面積之4倍以上。如此，由於接合面GEt與源極電極墊SE之接合面SEt1、SEt2相比面積足夠小，故藉由接合面SEt1、SEt2而不易與密封體40剝離。因此，於半導體晶片10之表面10t，進行與密封體40之剝離對策之部位係源極電極墊SE之接合面SEt1、SEt2之優先順序高於閘極電極墊GE之接合面GEt。 ＜半導體裝置之製造方法＞ 接著，對使用圖1～圖11說明之半導體裝置PKG1之製造步驟進行說明。半導體裝置PKG1係按照圖15所示之流程製造。圖15係顯示使用圖1～圖11說明之半導體裝置之製造步驟之概要的說明圖。於以下之說明中，於說明半導體裝置PKG1之構成零件時，有時視需要參照已說明之圖1～圖14而進行說明。 ＜半導體晶片準備步驟＞ 於圖15所示之半導體晶片準備步驟中，準備圖16所示之半導體晶片10。圖16係以圖15所示之半導體晶片準備步驟中準備之半導體晶片之表面(電極露出面)側的俯視圖。 本步驟中準備之半導體晶片10如圖6所示具有表面10t與位於表面10t相反側之背面10b。又，如圖16所示，半導體晶片10之表面10t包含：絕緣膜13之上表面及自絕緣膜13露出之源極電極墊(電極)SE之接合面(露出面)SEt1、SEt2、SEt3、及SEt4。源極電極墊SE具有：於形成於絕緣膜13之開口部13H1中自絕緣膜13露出之接合面SEt1、及於形成於絕緣膜13之開口部13H2中自絕緣膜13露出之接合面SEt2。又，於圖16所示之例中，源極電極墊SE具有：於形成於絕緣膜13之開口部13H4中自絕緣膜13露出之接合面SEt3、及於形成於絕緣膜13之開口部13H5中自絕緣膜13露出之接合面SEt4。接合面SEt1、SEt2、SEt3、及SEt4各者係於Y方向延伸，且以於與Y方向交叉之X方向彼此相鄰之方式排列。 又，於半導體晶片10之表面10t形成有閘極電極墊(電極)GE。閘極電極墊GE具有於形成於絕緣膜13之開口部13H3中自絕緣膜13露出之接合面GEt。又，如圖6所示，於半導體晶片10之背面10b形成有與汲極D(參照圖1)電性連接之汲極電極(電極)DE。於圖6所示之例中，半導體晶片10之背面10b整體均為汲極電極DE。 由於已使用圖9說明接合面SEt1、SEt2、SEt3、及SEt4之形狀及構造，故省略重複之說明。 圖16所示之半導體晶片10例如以如下方式製造。於包含n型單晶矽之半導體基板WH(參照圖2)之主面WHt(參照圖2)上，準備形成有n- 型磊晶層EP之半導體晶圓(省略圖示)，如圖8所示，於磊晶層EP上形成複數個電晶體Q1。於半導體晶圓包含多個晶片區域，且對複數個晶片區域各者形成複數個電晶體Q1。又，於電晶體Q1上形成源極電極墊SE及閘極電極墊GE。源極電極墊SE連接於複數個源極區域SR，閘極電極墊GE連接於複數個閘極電極G。於圖8所示之例中，顯示將源極區域SR與源極電極墊SE直接連接之例，但作為變化例，可於源極區域與源極電極墊SE之間介置引出配線(源極配線)。又，於圖8中省略圖示，但閘極電極墊GE與閘極電極G經由未圖示之引出配線(閘極配線)連接。接著，以覆蓋源極電極墊SE及閘極電極墊GE整體之方式形成絕緣膜13。其後，於絕緣膜13形成圖16所示之開口部13H1、13H2、13H3、13H4、及13H5，使源極電極墊SE之一部分(接合面SEt1、SEt2、SEt3、SEt4)及閘極電極墊GE之一部分(接合面GEt)自絕緣膜13露出。其後，對電路進行電性測試等必要之測試(晶圓測試)後，將晶圓分割成複數個半導體晶片10。另，於背面10b形成金屬膜作為圖6所示之汲極電極DE之情形時，作為汲極電極DE使用之金屬膜係於準備半導體晶圓之步驟至分割半導體晶圓之步驟之間之任意時序形成。例如，於形成開口部13H1、13H2、13H3、13H4、13H5後且晶圓測試之前，研磨半導體晶圓之背面而將半導體晶片10之厚度薄化之情形時，於研磨背面後，於背面10b(參照圖6)形成汲極電極DE即金屬膜。於未使用金屬膜作為汲極電極DE之情形時可省略該步驟。 又，於半導體晶片準備步驟中，於分割半導體晶圓而取得複數個半導體晶片10之前，實施晶圓測試。該晶圓測試包含確認形成於半導體晶片10之電路之電氣特性之電性測試。於該電性測試中，例如使未圖示之測試用端子(探針)接觸於源極電極墊SE。此時，當測試用之端子咬入源極電極墊SE時，會於源極電極墊SE留下測試用之端子咬入之痕跡(圖16所示之探針痕跡PRM)。 接合面SEt1、SEt2、SEt3、及SEt4各者如上所述具有區域SER1、SER2、及SER3。其中，區域SER1及區域SER2為接合導線12(參照圖7)之區域。若考慮導線12之連接穩定性，則接合導線12之區域最好無如探針痕跡PRM之凹凸。因此，如圖16所示，探針痕跡PRM形成於區域SER3而非導線連接之預定區域。 另，於圖16所示之例中，由於接合面SEt1、SEt2、SEt3、及SEt4各者彼此電性連接，故代表性顯示使測試用之端子接觸於接合面SEt4之例。然而，亦有於接合面SEt1、SEt2、SEt3、及SEt4全數形成探針痕跡PRM之情形。於該情形時，會於接合面SEt1、SEt2、SEt3、及SEt4各者所具備之區域SER3形成探針痕跡PRM。 ＜引腳框架準備步驟＞ 又，於圖15所示之引腳框架準備步驟中，準備圖17所示之引腳框架LF。又，圖17係顯示圖15所示之引腳框架準備步驟中準備之引腳框架之一部分的放大俯視圖。 如圖17所示，本步驟中準備之引腳框架LF具備連接於框部(框架部)LFf之器件形成部LFd。一個器件形成部LFd相當於圖5所示之一個半導體裝置PKG1。於圖17中，圖示一個之器件形成部LFd，但引腳框架LF具備經由框部LFf連結之複數個器件形成部LFd。如此，由於可藉由使用具備複數個器件形成部LFd之引腳框架LF而一次製造複數個半導體裝置PKG1(參照圖3)，故可提高製造效率。 引腳框架LF包含例如以銅(Cu)為主成分之金屬材料，且厚度為例如125 μm～400 μm左右。又，複數個器件形成部LFd各者連接於框部LFf。框部LFf為截至圖15所示之引腳分離步驟為止之期間支持形成於器件形成部LFd內之各構件的支持部。 又，如圖17所示，於器件形成部LFd形成有晶片焊墊20及複數條引腳30。晶片焊墊20經由複數條引腳30中之一條(引腳30D)與框部LFf連結，且被支持於框部LFf。又，晶片焊墊20具備晶片搭載面即上表面20t。 又，複數條引腳30各自連結於框部LFf，且被支持於框部LFf。複數條引腳30各者以沿著Y方向延伸，且於X方向上彼此相鄰之方式並排排列。複數條引腳30各者經由連接條LFt而彼此連結。 複數條引腳30包含源極用引腳即複數條引腳30S。複數條引腳30S各者以於X方向上彼此相鄰地並排之方式排列，且連結於導線接合部(引腳柱、焊墊、接合墊、導線連接部、接合部)30W。又，複數條引腳30包含閘極用之引腳即引腳30G。於引腳30G之晶片焊墊20側之前端部分設置有導線接合部30W。又，複數條引腳30包含汲極用之引腳即引腳30D。引腳30D於X方向上配置於引腳30G與引腳30S之間，其於Y方向上晶片焊墊20側之前端連結於晶片焊墊20。 於本實施形態中，晶片焊墊20之上表面20t配置於與引腳30之導線接合部30W之上表面30t不同之高度。對支持晶片焊墊20之引腳30D、及連接晶片焊墊20與框部LFf之部分實施彎曲加工，使晶片焊墊20偏移。於本實施形態中，晶片焊墊20相對於引腳框架LF之其他構件下沈配置。因此，如圖6所示，晶片焊墊20之上表面20t配置於較引腳30之上表面30t更下方。如此，藉由將晶片焊墊20下沈配置，如圖6所示般晶片焊墊20之下表面20b自密封體40露出。 ＜半導體晶片搭載步驟＞ 接著，於圖15所示之半導體晶片搭載步驟中，如圖5所示，將半導體晶片10搭載於引腳框架LF之晶片墊20。 於本步驟中，將半導體晶片10經由固晶材11而搭載(接著固定)於與汲極端子即引腳30D一體形成之晶片焊墊20之上表面20t。又，半導體晶片10係以形成有汲極電極DE(參照圖6)之背面10b(參照圖6)與晶片焊墊20之晶片搭載面即上表面20t對向之方式，經由固晶材11接著固定。藉此，半導體晶片10之汲極電極DE經由導電性之連接材料即固晶材11與晶片焊墊20電性連接。 於本步驟中，於將固晶材11塗布於晶片焊墊20之上表面20t上後，將半導體晶片10配置於固晶材11上。且，藉由使固晶材硬化而固定半導體晶片10與晶片焊墊20。 固晶材11可使用例如焊料材料。或，固晶材11可為含複數個銀(Ag)粒子(Ag填料)之所謂稱為銀(Ag)膏之導電性樹脂接著材。於固晶材11為焊料材料之情形時，作為使固晶材硬化之方法，進行回焊處理。又，於固晶材11為導電性之樹脂接著材之情形時，將固晶材11中所含之熱硬化性樹脂成分加熱而使其硬化。 ＜打線接合步驟＞ 接著，於圖15所示之打線接合步驟中，如圖5所示，將半導體晶片10之複數個電極墊(閘極電極墊GE及源極電極墊SE)與複數條引腳30各者經由導線(金屬線)12電性連接。 如圖5所示，於本步驟中，將半導體晶片10之閘極電極墊GE與引腳30G經由導線12G電性連接。又，於本步驟中，將半導體晶片10之源極電極墊SE與引腳30S經由導線12S電性連接。詳細而言，於閘極電極墊GE之一部分即接合面GEt(參照圖7)接合導線12G之接合部12B2(參照圖7)，於引腳30G之導線連接部30W之上表面(接合面)30t接合導線12G之接合部12B3。又，於源極電極墊SE之一部分即接合面SEt1(參照圖7)接合導線12S1(參照圖7)之接合部12B1及接合部12B2，於引腳30S之導線連接部30W之上表面(接合面)30t接合導線12S1之接合部12B3。與接合面SEt1同樣地，於圖16所示之接合面SEt2、SEt3、及SE4各者接合導線12(參照圖5)。 可對導線12之連接方法應用各種變化例，於本實施形態中，使用未圖示之稱為楔形工具之接合工具接合鋁製之導線12。於以下，作為使用楔形接合方法之打線接合步驟之例，採用經由圖10所示之導電12S1將源極電極墊SE與圖5所示之引腳30S電性連接之方法進行說明。 首先，打線接合步驟使用楔形工具，接合圖10及圖11所示之導線12S1之接合部12B1與源極電極墊SE之中於開口部13H1露出之接合面SEt1的區域SER1(參照圖10)(第1接合步驟)。於楔形接合方法之情形時，於楔形工具之前端面與接合面SEt1之間夾著導線12S1，並自前端面施加壓力及熱，藉此將導線12S1熱壓接於接合面SEt1。又，此時，藉由自前端面施加超音波而使導線12S1易於接合。被楔形工具按壓之導線12S1變形，形成接合部12B1。如此，藉由使具有圓形剖面之狀態之導線變形而形成之接合部12B1稱為針腳部。 接著，打線接合步驟係於使楔形工具自圖10及圖11所示之接合面SEt1遠離後，使其沿著Y方向移動，藉此形成環部12L1(第1環形成步驟)。於本步驟中，楔形工具一面抽出導線12S1一面上升至引腳框架LF之上方，藉此將楔形工具與半導體晶片10之距離拉遠。其後，使楔形工具朝進行第2接合之區域沿著Y方向移動後再次下降。藉此，形成圖11所示之環部12L1。此時，如使用圖11說明般，於本實施形態之情形時，於導線12之環部12L1與源極電極墊SE之間未介置絕緣膜13。因此，使楔形工具WT上升之高度可降低。藉此，可縮短圖11所示之環部長度LE1。 接著，打線接合步驟使用楔形工具，接合圖10及圖11所示之導線12S1之接合部12B2與源極電極墊SE之中於開口部13H1露出之接合面SEt1的區域SER2(參照圖10)(第2接合步驟)。於第2接合步驟中，與第1接合步驟同樣地，使導線12S1熱壓接於接合面SEt1。此時，可施加超音波。 接著，打線接合步驟係於使楔形工具自圖10及圖11所示之接合面SEt1遠離後，使其朝引腳30S(參照圖5)之導線接合部30W(參照圖5)移動，藉此形成環部12L2(參照圖11)(第2環形成步驟)。環部12L2自半導體晶片10朝引腳30延伸。因此，於第2環形成步驟之後，如圖7所示，於俯視時環部12L2與開口部13H1所具有之複數條邊中之任一條交叉。於圖7所示之例中，導線12S1之環部12L2與開口部13H1之邊HS4(參照圖9)交叉。 接著，打線接合步驟使用楔形工具，接合導線12S1(參照圖10)之接合部12B3(參照圖5)與引腳30S(參照圖5)之導線接合部30W(參照圖5)之接合面即上表面30t(參照圖5)(第3接合步驟)。 接著，打線接合步驟使用楔形工具所具備之線鉗切斷導線12S1(導線切割步驟)。 藉由以上之各步驟，經由圖5所示之導線12S將半導體晶片10之源極電極墊SE與引腳30S電性連接。 又，於本實施形態之情形時，相對於導線12S之接合位置之位置偏移之裕度較小。因此，於打線接合步驟中，較佳於接合第1條導線12S後，確認導線12S之接合位置之位置偏移之程度，基於該確認結果調整打線接合位置(根據需要而變更)。位置偏移之確認至少於接合圖10所示之導線12S1之接合部12B1後實施。然而，亦可於將導線12S1接合於圖5所示之引腳30S後實施。藉此，可提高第2條以後之導線12S之位置精度。又，於一個引腳框架LF(參照圖17)形成有複數個器件形成部LFd之情形時，於複數個器件形成部LFd之中最先實施打線接合步驟之器件形成部LFd進行位置偏移之確認及調整。藉此，可不用對第2次以後實施打線接合步驟之器件形成部LFd實施位置偏移確認。 ＜密封步驟＞ 接著，於圖15所示之密封步驟中，以絕緣樹脂密封圖5所示之半導體晶片10、晶片焊墊20之一部分、複數條引腳30各者之一部分(圖19所示之內部30M)、及複數條導線12，形成圖18所示之密封體40。圖18係顯示圖15所示之密封步驟中形成密封半導體晶片及導線之密封體之狀態的放大俯視圖。又，圖19係顯示於沿著圖18之A-A線之剖面中，於成形模具內配置有引腳框架之狀態的放大剖視圖。又，圖20係顯示於密封步驟中，由樹脂密封之導線之周邊的放大剖視圖。 於本步驟中，例如，如圖19所示使用具備上模(第1模具)62T、下模(第2模具)62B之成形模具62，藉由所謂之轉注成形法而形成密封體40。 於圖19所示之例中，以器件形成部LFd之晶片焊墊20及複數條引腳30各者之一部分位於由上模62T及下模62B形成之腔室62C內之方式配置引腳框架LF。接著，以上模62T與下模62B夾固(夾入)引腳框架LF。於該狀態下，將包含經軟化(可塑化)之熱硬化性樹脂(絕緣樹脂)之密封體之原料壓入成形模具62之腔室62C時，則絕緣樹脂被供給至以腔室62C與下模62B形成之空間內，仿照腔室62C之形狀成形。 此時，如圖19所示，晶片焊墊20之上表面20t之中與偏移之部分相連且配置於相對較高位置之前端側之一部分被上模62T按壓。又，晶片焊墊20之下表面20b被下模62B按壓。於圖19所示之例中，晶片焊墊20之中偏移之部分之下表面20b與下模62B密接。因此，如圖18所示，於本步驟之後，晶片焊墊20之下表面20b中之一部分自密封體40露出。 又，如圖20所示，於本步驟中，以使構成密封體40之樹脂與接合面SEt1接觸之方式形成密封體40。又，於本步驟中，樹脂亦滲入至導線12之環部12L1與接合面SEt1、SEt2之間，成為於導線12之環部12L1與接合面SEt1、SEt2之間介置有密封體40之狀態。 然而，於俯視下，於導線12S1之環部12L1與接合面SEt1重合之區域，如圖20所示，接合面SEt1自絕緣膜13及導線12S1露出，且密接於密封體40。其中，於導線12S1之環部12L1與接合面SEt1重合之區域，由於密封體40因導線12S1之環部12L1而被夾於接合面SEt1，故於該區域中不易產生接合面SEt1與密封體40之剝離。因此，於考量密封體40與接合面SEt1之剝離之情形時，如圖10所示，重要的是使俯視時接合面SEt1之中不與導線12S1重合之區域之露出面之面積減少。又，接合面SEt1中不與導線12S1重合之區域之中如圖7所示配置於相鄰之導線12之間之區域，較佳為接合面SEt1之露出面積特別小。 如上所述，於密封體40與包含金屬材料之接合面SEt1之接觸面積較大之情形時，於本步驟之後，會有於密封體40與接合面SEt1之接合界面產生剝離之情形。尤其如圖7所示，於相鄰之導線12之分隔距離較小之情形時，於相鄰之導線12之間容易產生剝離。然而，根據本實施形態，如上所述，由於可減少密封體40與接合面SEt1之接觸界面之中容易產生剝離之部分之面積，故可抑制剝離。 於密封體40成形後，加熱至密封體40中所含之熱硬化性樹脂之一部分硬化(稱為預硬化)。若藉由該預硬化而能夠將引腳框架LF自成形模具62取出時，將引腳框架LF自成形模具62取出。然後，搬送至加熱爐，進而進行加熱處理(固化烘焙)。藉此，將熱硬化性樹脂之剩餘部分硬化而獲得圖18所示之密封體40。 又，密封體40構成為以絕緣性之樹脂為主體，但亦可藉由將例如Silica(二氧化矽，SiO2 )粒子等填料粒子混合於熱硬化性樹脂而提高密封體40之功能(例如抗翹曲變形性)。 ＜鍍覆步驟＞ 接著，於圖15所示之鍍覆步驟中，將圖18所示之引腳框架LF浸於未圖示之鍍覆溶液，而於自密封體40露出之金屬部分(外部)之表面形成金屬膜(圖6所示之金屬膜22及金屬膜32)。 於本步驟中，藉由電解鍍覆法，於自樹脂露出之金屬構件之表面，形成包含例如焊料之金屬膜22、32(參照圖6)。雖省略圖示，但於電解鍍覆法中，將被鍍覆加工物即引腳框架LF(參照圖18)配置於放有鍍覆液之鍍覆槽內。此時，將被加工物連接於鍍覆槽內之陰極。例如，將引腳框架LF之框部LFf(參照圖18)與陰極電性連接。然後，對該陰極、與配置於相同之鍍覆槽內之陽極之間施加例如直流電壓，藉此於與引腳框架LF之框部LFf連接之金屬構件之露出面形成金屬膜22、32。於本實施形態中，藉由所謂之電解鍍覆法形成金屬膜22、32。 另，於圖15中，雖省略圖示，但於鍍覆步驟中，於將引腳框架LF浸於鍍覆液之前，作為前處理，可對圖18所示之晶片焊墊20或引腳30之表面實施化學研磨。藉由於將引腳框架LF浸於鍍覆液之前實施前處理，可去除例如自密封體40(參照圖8)露出之引腳框架LF之表面之氧化膜或微小之毛刺。 本實施形態之金屬膜22、32如上所述包含實質上不含鉛(Pb)之所謂之無鉛焊料，而為例如僅錫(Sn)、錫-鉍(Sn-Bi)、或錫-銅-銀(Sn-Cu-Ag)等。因此，於本鍍覆步驟中使用之鍍覆液為包含例如Sn2+ 、或Bi3+ 等金屬鹽之電解鍍覆液。另，於以下之說明中，作為無鉛焊料鍍覆之例，對Sn-Bi之合金化金屬鍍覆進行說明，但亦可將鉍(Bi)置換為銅(Cu)或銀(Ag)等金屬，或置換為不僅包含鉍(Bi)並添加有銅(Cu)或銀(Ag)之電解鍍覆液 於本實施形態中，於將圖18所示之晶片焊墊20(參照圖6)經由引腳30與框部LFf電性連接之狀態進行鍍覆步驟。於將引腳框架LF浸於鍍覆液之狀態，當對陽極與陰極間施加電壓時，連接於陰極之引腳30及晶片焊墊20與陽極之間經由鍍覆液而通電。此時，將鍍覆液中之Sn2+ 、及Bi3+ 以特定之比例析出於引腳30及晶片焊墊20中之自密封體40之露出面，而形成圖6所示之金屬膜22、32。 ＜單片化步驟＞ 接著，於圖15所示之單片化步驟中，將相當於圖3所示之半導體裝置PKG1(參照圖3)之組裝體自圖18所示之引腳框架LF之框部LFf及連接條LFt分離而單片化。 於本步驟中，切斷連結於晶片焊墊20(參照圖6)之框部LFf(參照圖18)，且分別分割經由框部LFf連結之複數個晶片焊墊20。又，於本步驟中，切斷連接條LFt(參照圖18)，且切斷複數條引腳30與框部LFf之交界，藉此使複數條引腳30各者分離。 對於連接條LFt、框部LFf、及引腳30之切斷方法，可使用藉由將切斷夾具按壓於被切斷部位而切斷之加工方法(壓製加工)。由於本步驟係於鍍覆步驟之後進行，故於本步驟中被切斷而新形成之側面自鍍覆膜(圖6所示之金屬膜22、32)露出。 於本步驟之後，進行外觀檢查、電性測試等必要之檢查、測試，合格者成為圖3所示之完成品之半導體裝置PKG1。且，將半導體裝置PKG1出貨，或安裝於未圖示之安裝基板。 以上，基於實施形態具體地說明了由本發明者完成之發明，但本發明並非僅限定於上述實施形態或上述實施形態中說明之變化例者，於不脫離其主旨之範圍內當得進行各種變更。以下對代表性之變化例進行說明。 ＜變化例1＞ 如使用圖9及圖10說明般，若將接合面SEt1之露出面積縮小，於接合步驟中相對於導線之接合位置之位置偏移之裕度減小。因此，於打線接合步驟中，較佳為目測或使用影像感測器等確認導線12S1之接合部12B1、12B2與接合面SEt1之位置關係，基於確認結果進行打線接合位置之微調整。又，於確認導線12S1之接合部12B1、12B2與接合面SEt1之位置關係之情形時，若於接合部12B1、12B2附近有可掌握位置偏移程度之標記，則可容易地實施微調整。於本變化例中，對於圖9所示之接合面SEt1之一部分形成可掌握位置偏移程度之標記之構造例進行說明。圖21係顯示相對於圖9之變化例之放大俯視圖。又，圖22及圖23係顯示將導線接合於圖21所示之接合面之狀態例的放大俯視圖。 於圖21所示之變化例之情形，接合面SEt1之區域SER1具有：於開口部13H1之邊HS1上沿著X方向突出之突出部HSM1、及於開口部13H1之邊HS2上沿著X方向突出之突出部HSM2。又，接合面SEt1之區域SER2具有：於開口部13H1之邊HS1上沿著X方向突出之突出部HSM3、與於開口部13H1之邊HS2上沿著X方向突出之突出部HSM4。 突出部HSM1、HSM2、HSM3、及HSM4各者自接合面SEt1之面內朝向絕緣膜13(參照圖7)突出。又，突出部HSM1、HSM2、HSM3、及HSM4各者為上述之打線接合步驟中，於確認導線12S1之接合位置之位置偏移之程度時所參照的標記。詳細而言，於打線接合步驟中，參照X方向之突出部HSM1、HSM2、HSM3、或HSM4之長度(寬度)WRP，確認圖10所示之導線12S1之接合部12B1或12B2之位置之偏移量。圖21所示之突出部HSM1、HSM2、HSM3、或HSM4之X方向之長度(寬度)WRP之值彼此相等，為例如50 μm。該50 μm之值係打線接合步驟中容許之位置偏移量之上限值。 又，於俯視時，Y方向之突出部HSM1之長度LM1及Y方向之突出部HSM2之長度LM2各者，短於Y方向之區域SER1之長度。換言之，突出部HSM1形成於區域SER1之邊HS1之一部分。又，突出部HSM2形成於區域SER1之邊HS2之一部分。又，Y方向之突出部HSM3之長度LM3及Y方向之突出部HSM4之長度LM4各者，短於Y方向之區域SER2之長度。由於突出部HSM1形成於區域SER1之一部分，故如圖22及圖23所示，可比較邊HS1與接合部12B1之分隔距離GP1與突出部HSM1之X方向之長度WRP。關於突出部HSM2、HSM3、及HSM4亦同樣。 如本變化例般，若於接合面SEt1之區域SER1形成有成為位置偏移量之基準之標記，如圖22及圖23所示，於接合部12B1之位置相對於接合面SEt1之區域SER1之特定位置偏移之情形時，可容易地確認偏移量。例如，如圖22所示，於接合部12B1靠向開口部13H1之邊HS1側之情形時，若比較邊HS1與接合部12B1之分隔距離GP1、與突出部HSM1之X方向之長度WRP，則可容易地確認相對於容許值之偏移量之程度。 又，如圖23所示，於接合部12B1靠向開口部13H1之邊HS2側之情形時，若比較邊HS2與接合部12B1之分隔距離GP2、與突出部HSM2之X方向之長度WRP，則可容易地確認相對於容許值之偏移量之程度。如圖21所示，若於邊HS1與邊HS2之兩側形成有突出部HSM1、HSM2，可高精度地掌握偏移量。 惟如圖23所示，即使於接合部12B1靠向開口部13H1之邊HS2側之情形時，亦可比較邊HS1與接合部12B1之分隔距離GP1、與突出部HSM1之X方向之長度WRP。於該情形時，亦可掌握接合部12B1之位置偏移之程度。 又，於圖21所示之例中，於接合面SEt1之區域SER2形成有突出部HSM3及突出部HSM4。如圖10所示，導線12S1之接合部12B1、環部12L1、及接合部12B2各自沿著Y方向直線地配置。因此，只要形成圖21所示之突出部HSM1、HSM2、HSM3、及HSM4中之至少任一者，則可掌握偏移量。然而，如圖21所示，若於區域SER1與區域SER2各者均形成有突出部，則於圖10所示之導線12S1之延伸方向之角度相對於Y方向傾斜之情形時，易於掌握該傾斜角度。 又，圖21所示之突出部HSM1、HSM2、HSM3、及HSM4之長度WRP，可根據打線接合步驟之容許範圍之設定值而變更，但若該值極端地增大，則突出部HSM1、HSM2、HSM3、或HSM4有可能成為上述之剝離之起點。因此，較佳為長度WRP小至不會發生剝離之程度。於圖21所示之例中，長度WRP為50 μm，短於長度LM1、LM2、LM3及LM4各者。長度LM1、LM2、LM3及LM4為例如200 μm左右。又，較佳為長度WRP小於圖22及圖23所示之分隔距離GP1及分隔距離GP2中之任一較大者之值。例如，於圖22及圖23所示之情形，由於分隔距離GP1與分隔距離GP2之合計值為100 μm，故只要長度WRP為50 μm，則除了分隔距離GP1為50 μm之情形以外，均滿足上述之條件。 又，於圖21～圖23中，對於導線12S1(參照圖22)之接合部12B1附近配置用以掌握位置偏移量之標記之例進行了說明，但標記亦可形成於圖9所示之區域SER3。圖24係顯示相對於圖21之變化例之放大俯視圖。圖25係顯示將導線接合於圖24所示之接合面之狀態例的放大俯視圖。 於圖24所示之變化例之情形時，接合面SEt1之區域SER3具有：於開口部13H1之邊HS1上沿著X方向朝區域SER3凹陷之凹部HSM5，及於開口部13H1之邊HS2上沿著X方向朝區域SER3凹陷之凹部HSM6。 凹部HSM5及HSM6各者以咬入接合面SEt1之區域SER3之方式凹陷。又，凹部HSM5及HSM6各者為上述之打線接合步驟中，確認導線12S1之接合位置之位置偏移程度時所參照時標記。詳細而言，於打線接合步驟中，確認X方向之凹部HSM5及HSM6之長度(寬度)WRP、與圖10所示之導線12S1之環部12L1之位置關係，藉此確認位置之偏移量。圖21所示之凹部HSM5及HSM6之X方向之長度(寬度)WRP之值彼此相等，為例如50 μm。該50 μm之值如上所述為打線接合步驟中容許之位置偏移量之上限值。 又，於俯視時，Y方向之凹部HSM5之長度LM5及凹部HSM6之長度LM6各者短於X方向之區域SER3之長度。換言之，凹部HSM5形成於區域SER3之邊HS1之一部分。又，凹部HSM6形成於區域SER3之邊HS2之一部分。又，由於凹部HSM5形成於區域SER3之一部分，故如圖25所示，於俯視時，可容易地掌握凹部HSM5中之自環部12L1露出之部分之X方向之長度GP3。 如變化例般，若於接合面SEt1之區域SER3形成有成為位置偏移量之基準之標記，如圖25所示，於環部12L1之位置相對於接合面SEt1之區域SER3之特定位置偏移之情形時，可容易地確認偏移量。又，如上所述，圖10所示之導線12S1之接合部12B1、環部12L1、及接合部12B2各者沿著Y方向直線地配置。因此，只要可掌握偏移量，則可推測接合部12B1、12B2之偏移量。 又，於圖21所示之例中，與未形成突出部HSM1、HSM2、HSM3、及HSM4之情形相比，開口部13H1之開口面積增大。因此，例如，如圖7所示，於彼此相鄰之開口部13H1與開口部13H2之分隔距離較小之情形時，必須以形成於開口部13H1與開口部13H2各者之突出部HSM1、HSM2、HSM3、及HSM4彼此不連通之方式考量佈局。 另一方面，於圖24所示之例之情形時，與未形成凹部HSM5及HSM6之例相比，開口部13H1之開口面積減小。因此，如圖7所示，即使於開口部13H1與開口部13H2之分隔距離較小之情形時，佈局之自由度仍高。 另，如圖25所示，於導線12S1之位置靠向開口部13H1之邊HS2側之情形時，無法視認到設置於邊HS2之凹部HSM6。相反的，於導線12S1之位置靠向開口部13H1之邊HS1側之情形時，無法視認設置於邊HS1之凹部HSM5。因此，於導線12S1之位置靠向邊HS1及HS2中之任一側之情形時，基於掌握偏移量之觀點，如圖24所示，較佳於邊HS1及邊HS2之兩者均形成凹部。 又，於圖24所示之例中，未形成使用圖21說明之突出部HSM1、HSM2、HSM3、及HSM4。然而，作為變化例，可在圖25所示之凹部HSM5、HSM6之外，並形成圖21所示之突出部HSM1、HSM2、HSM3、及HSM4中之一個以上。 ＜變化例2＞ 又，於上述實施形態中，如圖9所示，採用於開口部13H1之邊HS1及邊HS2之兩者形成收縮部之實施態樣進行說明。然而，作為變化例，可如圖26所示，於邊HS1及邊HS2中之任一者形成收縮部。圖26係顯示相對於圖13之變化例之放大俯視圖。 圖26所示之接合面SEt1與圖13所示之接合面SEt1之不同點在於：於開口部13H1之邊HS2側無圖13所示之部分HSP23，故邊HS2直線地延伸。 圖26所示之變化例之情形亦可為，於導線12S1之接合位置靠向邊HS2側之情形時，邊HS2與導線12S1之環部12L1間之寬度WR4之值未達100 μm。另一方面，雖省略圖示，但於導線12S1之接合位置靠向邊HS1側之情形時，有寬度WR4之值為150 μm之情形。 然而，如圖5所示，複數條導線12S彼此相鄰地排列，但如圖7所示，導線12S1配置於排列之端部。又，於開口部13H1之邊HS2側未配置導線12S。因此，於圖26所示之例中，與於圖12所示之探討例中寬度WR3之值為150 μm之情形相比，於寬度WR3之值為150 μm之情形時不易發生剝離。 如此，若接合面(開口部)以彼此相鄰之方式排列，且為配置於排列之端部之接合面，亦有於邊HS1及邊HS2中之一者設置收縮部之情形。 ＜變化例3＞ 又，於上述實施形態中，例如如圖8所示，已針對將一個源極電極墊SE之複數個部分於設置於絕緣膜13之複數個開口部13H1中露出之實施態樣進行了說明。然而亦可為，圖8所示之接合面SEt1為由絕緣膜13覆蓋之第1源極電極墊(電極、源極電極)SE1之一部分，接合面SEt2為由絕緣膜13覆蓋之第2源極電極墊(電極、源極電極)SE2之一部分。 ＜變化例4＞ 又，於上述實施形態中，例如如圖7所示，對接合面SEt1與接合面SEt2之形狀為長方形之情形進行了說明。然而，接合面SEt1與接合面SEt2之形狀不限定於長方形，而有例如多角形或圓形(包含橢圓形)等各種變化例。 ＜變化例5＞ 又，雖省略圖示，但作為相對於圖7之另一變化例，可將導線12S1於三個部位以上接合於一個接合面SEt1。於該情形時，由於導線12S1與接合面SEt1之接合面積增加，故可降低經由導線12S1之導電路徑之阻抗。關於導線12S2亦同樣。 惟於導線12S1與接合面SEt1之接合部位數量較多之情形時，接合面SEt1之Y方向之長度(例如於圖7所示之例中為邊HS1及邊HS2之長度)變長。於該情形時，由密封體40(參照圖20)與源極電極墊SE之線膨脹係數差而引起之應力，於接合面SEt1中之Y方向之兩端部(圖7所示之邊HS3之附近及邊HS4之附近)上尤其變大。因此，基於縮短Y方向之源極電極墊SE之長度之觀點，如圖7所示，尤佳為將導線12S1於二個部位接合於一個接合面SEt1的態樣。 ＜變化例6＞ 又，於上述實施形態中，作為功率半導體裝置所具備之功率電晶體之例，例示MOSFET，但可應用各種變化例。例如，可具備IGBT而取代MOSFET。於該情形時，可將上述實施形態中說明之MOSFET之汲極換成IGBT之集極，將MOSFET之源極換成IGBT之射極。又，於使用IGBT之情形時，大多將控制負載電流之流通方向之二極體(FWD：Free Wheeling Diode，飛輪二極體)晶片與IGBT晶片分隔搭載。因此，於圖5所示之晶片焊墊20上搭載IGBT晶片及FWD晶片。 又，於上述之實施形態中，作為容易對環境溫度或耐溫度循環負載要求嚴酷之條件之半導體裝置之例，採用功率半導體裝置進行了說明。然而，於功率半導體裝置以外之半導體裝置(例如，控制系統之半導體裝置或通信系統之半導體裝置)等之情形時，於環境溫度或耐溫度循環負載相關之要求規格較高之情形時，亦可藉由應用上述實施形態或變化例中說明之技術，使該等相關之性能提高。又，於功率半導體裝置以外之半導體裝置中，大多使用金(Au)導線作為導線，且使用球接合方式作為打線接合方式。 ＜變化例7＞ 又，於上述實施形態中，已說明例如如圖7所示之半導體晶片10般，接合面SEt1及接合面SEt2之排列方向即X方向、與接合面SEt1及接合面SEt2之延伸方向即Y方向沿著半導體晶片10之表面10t之外緣之各邊延伸的實施態樣。然而，上述之各構成亦可應用於X方向及Y方向各者相對於半導體晶片10之表面10t之外緣之各邊以正交以外之角度交叉之情形。 ＜變化例8＞ 又，已對例如如上所述之各種變化例進行了說明，但亦可將上述說明之各變化例彼此組合而應用。又，亦可擷取各變化例之一部分加以組合。
10‧‧‧半導體晶片10b‧‧‧背面(面、主面、下表面)10s‧‧‧側面(面)10t‧‧‧表面(面、主面、上表面)11‧‧‧固晶材(接著材)12‧‧‧導線(金屬導線、導線性構件、金屬線)12B1‧‧‧接合部(連接部、針腳部)12B2‧‧‧接合部(連接部、針腳部)12B3‧‧‧接合部(連接部、針腳部)12G‧‧‧導線(金屬導線、導線性構件、金屬線)12L1‧‧‧環部(中間部、延伸部)12L2‧‧‧環部(中間部、延伸部)12S‧‧‧導線(金屬導線、導線性構件、金屬線)12S1‧‧‧導線(金屬導線、導線性構件、金屬線)12S2‧‧‧導線(金屬導線、導線性構件、金屬線)13‧‧‧絕緣膜(保護膜)13H1～13H5‧‧‧開口部20‧‧‧晶片焊墊(金屬板、晶片搭載部、散熱板)20b‧‧‧下表面(面、主面、背面、露出面、安裝面)20s‧‧‧側面20s1‧‧‧側面20s2‧‧‧側面20t‧‧‧上表面(面、主面、表面、晶片搭載面)21‧‧‧基材22‧‧‧金屬膜(鍍覆膜)30‧‧‧引腳(端子)30b‧‧‧下表面(面)30D‧‧‧引腳(端子)30G‧‧‧引腳(端子)30M‧‧‧內部(內引腳部、被密封部)30s‧‧‧側面30S‧‧‧引腳(端子)30t‧‧‧上表面(面、打線接合面)30W‧‧‧導線接合部(引腳柱、焊墊、接合墊、導線連接部、接合部)30X‧‧‧外部(外引腳部、露出部)31‧‧‧基材32‧‧‧金屬膜(鍍覆膜)40‧‧‧密封體(樹脂密封體、樹脂體、模塑樹脂)40b‧‧‧下表面(安裝面)40s‧‧‧側面40t‧‧‧上表面62‧‧‧成形模具62B‧‧‧下模(第2模具)62C‧‧‧腔室62T‧‧‧上模(第1模具)A-A‧‧‧線CH‧‧‧通道形成區域D‧‧‧汲極DE‧‧‧汲極電極(電極)EP‧‧‧磊晶層G‧‧‧閘極電極GE‧‧‧閘極電極墊(電極、閘極電極)GEt‧‧‧接合面(露出面、接合部)GI‧‧‧閘極絕緣膜GP1‧‧‧分隔距離GP2‧‧‧分隔距離GP3‧‧‧長度GW‧‧‧配線(閘極配線)HS1～HS4‧‧‧邊(部分)HSM1～HSM4‧‧‧突出部HSM5‧‧‧凹部HSM6‧‧‧凹部HSP1～HSP5‧‧‧部分HSP21～HSP25‧‧‧部分HT1‧‧‧環部高度LE1‧‧‧環部長度LE2‧‧‧長度LF‧‧‧引腳框架LFd‧‧‧框部(框架部)LFt‧‧‧連接條LM1～LM6‧‧‧長度PKG1‧‧‧半導體裝置PRM‧‧‧探針痕跡Q1‧‧‧電晶體S‧‧‧源極SE‧‧‧源極電極墊(電極、源極電極)SER1～SER5‧‧‧區域SEt1～SEt4‧‧‧接合面(露出面、接合部)SEtH‧‧‧接合面(露出面、接合部)SR‧‧‧源極區域SW‧‧‧配線(源極配線)TR1‧‧‧溝槽(開口部、溝槽)VL1‧‧‧延長線(假想線)VL2‧‧‧延長線(假想線)WC1‧‧‧寬度(長度、粗度)WC2‧‧‧寬度(長度、粗度)WH‧‧‧半導體基板WH1～WH5‧‧‧寬度(長度、粗度)WHt‧‧‧主面WR1～WR6‧‧‧寬度(長度、粗度)WRP‧‧‧寬度(長度、粗度)WW1‧‧‧寬度(長度、粗度)WW2‧‧‧寬度(長度、粗度)WS1‧‧‧距離WS2‧‧‧距離X‧‧‧方向Y‧‧‧方向Z‧‧‧方向
圖1係模式性顯示一實施形態之半導體裝置所具備之電路之一例的說明圖。 圖2係顯示圖1所示之場效電晶體之元件構造例之要部剖視圖。 圖3係圖1所示之半導體裝置之俯視圖。 圖4係圖3所示之半導體裝置之仰視圖。 圖5係以去除圖3所示之密封體之狀態顯示半導體裝置之內部構造之透視俯視圖。 圖6係沿著圖5之A-A線之剖視圖。 圖7係將圖5所示之半導體晶片之上表面周邊放大顯示之放大俯視圖。 圖8係沿著圖7之A-A線之放大剖視圖。 圖9係圖7所示之源極電極墊用之開口部之放大俯視圖。 圖10係顯示將源極導線接合於圖9所示之接合面之狀態的放大俯視圖。 圖11係沿著圖10之A-A線之放大剖視圖。 圖12係相對於圖10之探討例之接合面之放大俯視圖。 圖13係將圖10所示之導線之接合位置偏移的情形之環部之周邊放大顯示之放大俯視圖。 圖14係顯示相對於圖11之探討例之放大剖視圖。 圖15係顯示使用圖1～圖11說明之半導體裝置之製造步驟之概要的說明圖。 圖16係圖15所示之半導體晶片準備步驟中準備之半導體晶片之表面(電極露出面)側的俯視圖。 圖17係顯示圖15所示之引腳框架準備步驟中準備之引腳框架之一部分的放大俯視圖。 圖18係顯示形成圖15所示之密封步驟中密封半導體晶片及導線之密封體之狀態的放大俯視圖。 圖19係顯示於沿著圖18之A-A線之剖面上，將引腳框架配置於成形模具內之狀態的放大剖視圖。 圖20係顯示密封步驟中由樹脂密封之導線之周邊的放大剖視圖。 圖21係顯示相對於圖9之變化例之放大俯視圖。 圖22係顯示將導線接合於圖21所示之接合面之狀態例的放大俯視圖。 圖23係顯示將導線接合於圖21所示之接合面之另一狀態例的放大俯視圖。 圖24係顯示相對於圖21之變化例之放大俯視圖。 圖25係顯示將導線接合於圖24所示之接合面之狀態例的放大俯視圖。 圖26係顯示相對於圖13之變化例之放大俯視圖。
12‧‧‧導線
12B1‧‧‧接合部
12B2‧‧‧接合部
12L1‧‧‧環部
12S1‧‧‧導線(金屬導線、導線性構件、金屬線)
13H1‧‧‧開口部
HS1~HS3‧‧‧邊
HSP1~HSP3‧‧‧部分
HSP23‧‧‧部分
SE‧‧‧源極電極墊
SER1~SER3‧‧‧區域
SEt1‧‧‧接合面
VL1‧‧‧延長線
VL2‧‧‧延長線
WH1‧‧‧寬度
WH2‧‧‧寬度
WH3‧‧‧寬度
WR1‧‧‧寬度
WR2‧‧‧寬度
WR5‧‧‧寬度
WW1‧‧‧寬度
WW2‧‧‧寬度
X‧‧‧方向
Y‧‧‧方向

Claims (20)

  1. 一種半導體裝置，其具有：半導體晶片，其包含具有第1接合面之電極墊、及具備將上述電極墊之上述第1接合面露出之第1開口部之絕緣膜；第1導線，其與上述電極墊之上述第1接合面接合；及密封體，其以與上述電極墊之上述第1接合面接觸之方式密封上述半導體晶片與上述第1導線；且上述第1接合面包含金屬，上述密封體包含絕緣材料，於俯視時，上述第1接合面具有第1區域、第2區域、及位於上述第1區域與上述第2區域間之第3區域，上述第1導線具有：第1接合部，其與上述第1接合面之上述第1區域接合；第2接合部，其與上述第1接合面之上述第2區域接合；及第1中間部，其位於上述第1接合部與上述第2接合部之間；於俯視時，上述第1中間部沿著第1方向延伸，且上述第1中間部與上述第3區域分隔，於俯視時，與上述第1方向正交之第2方向之上述第1區域之寬度、與上述第2方向之上述第2區域之寬度，寬於上述第2方向之上述第3區域的寬度。
  2. 如請求項1之半導體裝置，其中上述第1開口部具有：第1邊，其於上述第2方向上位於上述第1開口 部之一端部，且於上述第1方向延伸；及第2邊，其位於上述第1邊之相反側之端部，且於上述第1方向延伸；上述第1邊分別於上述第1區域與上述第3區域間、及上述第2區域與上述第3區域之間彎曲，上述第2邊分別於上述第1區域與上述第3區域間、及上述第2區域與上述第3區域之間彎曲。
  3. 如請求項1之半導體裝置，其中於俯視時，上述第2方向之上述第3區域之寬度為上述第2方向之上述第1導線之上述第1中間部的寬度以下。
  4. 如請求項1之半導體裝置，其中於上述第2方向上，於上述第1導線之旁配置第2導線，且上述第2方向之上述第1導線與上述第2導線之分隔距離，小於上述第1導線之線徑。
  5. 如請求項1之半導體裝置，其中於俯視時，上述第1開口部具有沿著上述第1方向延伸之第1邊、及上述第1邊之相反側之第2邊，上述第1邊具有俯視時沿著上述第1區域延伸之第1部分、沿著上述第2區域延伸之第2部分、及位於上述第1部分與上述第2部分之間且沿著上述第3區域延伸之第3部分，且上述第1邊之上述第1部分之延長線與上述第3部分間之寬度，大於上 述第1邊之上述第3部分與上述第1導線之上述第1中間部之間的寬度。
  6. 如請求項1之半導體裝置，其中於俯視時，上述第1開口部具有沿著上述第1方向延伸之第1邊、及上述第1邊之相反側之第2邊，上述第1邊具有俯視時沿著上述第1區域延伸之第1部分、沿著上述第2區域延伸之第2部分、及位於上述第1部分與上述第2部分之間且沿著上述第3區域延伸之第3部分，上述第2邊具有俯視時沿著上述第1區域延伸之第4部分、沿著上述第2區域延伸之第5部分、及位於上述第4部分與上述第5部分之間且沿著上述第3區域延伸之第6部分，且上述第1邊之上述第3部分位於上述第1部分之延長線與上述第2邊之間，上述第2邊之上述第6部分位於上述第4部分之延長線與上述第1邊之間。
  7. 如請求項1之半導體裝置，其中上述第1接合面之上述第1區域具有沿著上述第2方向突出之第1突出部，於俯視時，上述第1方向之上述第1突出部之長度短於上述第1方向之上述第1區域之長度。
  8. 如請求項7之半導體裝置，其中 於俯視時，上述第2方向之上述第1突出部之長度短於上述第1方向之上述第1突出部之長度。
  9. 如請求項1之半導體裝置，其中於俯視時，上述第1開口部具有沿著上述第1方向延伸之第1邊、及上述第1邊之相反側之第2邊，上述第1接合面之上述第1區域具有：於上述第1開口部之上述第1邊上沿著上述第2方向突出之第1突出部，及於上述第1開口部之上述第2邊上沿著上述第2方向突出之第2突出部，於俯視時，上述第1方向之上述第1突出部之長度及上述第1方向之上述第2突出部之長度各者，短於上述第1方向之上述第1區域的長度。
  10. 如請求項9之半導體裝置，其中上述第1接合面之上述第2區域具有：於上述第1開口部之上述第1邊上沿著上述第2方向突出之第3突出部，及於上述第1開口部之上述第2邊上沿著上述第2方向突出之第4突出部，於俯視時，上述第1方向之上述第3突出部之長度及上述第1方向之上述第4突出部之長度各者，短於上述第1方向之上述第2區域的長度。
  11. 如請求項1之半導體裝置，其中上述第1接合面之上述第3區域具有沿著上述第2方向朝上述第3區域凹陷之第1凹部，且於俯視時，上述第1方向之上述第1凹部之長度短於上述第1方向之上 述第3區域的長度。
  12. 如請求項1之半導體裝置，其中於俯視時，上述第1開口部具有沿著上述第1方向延伸之第1邊、及上述第1邊之相反側之第2邊，上述第1接合面之上述第3區域具有：第1凹部，其於上述第1開口部之上述第1邊上沿著上述第2方向朝上述第2邊凹陷；及第2凹部，其於上述第1開口部之上述第2邊上沿著上述第2方向朝上述第1邊凹陷；且於俯視時，上述第1方向之上述第1凹部之長度及上述第2凹部之長度各者，短於上述第1方向之上述第3區域的長度。
  13. 如請求項1之半導體裝置，其中上述第3區域具有測試用端子咬入之痕跡。
  14. 一種半導體裝置，其具有：半導體晶片，其包含具有第1接合面之電極墊、及具備將上述電極墊之上述第1接合面露出之第1開口部之絕緣膜；第1導線，其與上述電極墊之上述第1接合面接合；及密封體，其以與上述電極墊之上述第1接合面接觸之方式密封上述半導體晶片與上述第1導線；且上述第1接合面包含金屬，上述密封體包含絕緣材料，上述第1導線具有：第1接合部，其與上述第1接合面接合；第2接合 部，其與上述第1接合面接合；及第1中間部，其位於上述第1接合部與上述第2接合部之間；於俯視時，上述第1中間部沿著第1方向延伸，且上述第1中間部與上述第1接合面分隔，於俯視時，上述第1開口部具有沿著上述第1方向延伸之第1邊、上述第1邊之相反側之第2邊、沿著與上述第1方向正交之第2方向延伸之第3邊、及上述第3邊之相反側之第4邊，且上述第1邊具有俯視時沿著上述第1方向延伸之第1部分、沿著上述第1方向延伸之第2部分、及位於上述第1部分與上述第2部分之間且沿著上述第1方向延伸之第3部分，於俯視時之上述第2方向上，上述第1接合部位於上述第1邊之上述第1部分與上述第2邊之間，於俯視時之上述第2方向上，上述第2接合部位於上述第1邊之上述第2部分與上述第2邊之間，於俯視時之上述第2方向上，上述第1中間部位於上述第1邊之上述第3部分與上述第2邊之間，於俯視時，上述第1邊之上述第1部分至上述第2邊之上述第2方向之長度、及上述第1邊之上述第2部分至上述第2邊之上述第2方向之長度各者，大於上述第3部分至上述第2邊之上述第2方向的長度。
  15. 如請求項14之半導體裝置，其中上述第2邊具有俯視時沿著上述第1方向延伸之第4部分、沿著上述第1方向延伸之第5部分、及位於上述第1部分與上述第2部分之間且沿著上 述第1方向延伸之第6部分，上述第1邊之上述第3部分位於上述第1部分之延長線與上述第2邊之間，上述第2邊之上述第6部分位於上述第4部分之延長線與上述第1邊之間。
  16. 如請求項14之半導體裝置，其中上述第1接合面之中與上述第1導線之上述第1中間部重合之區域，具有測試用之端子咬入的痕跡。
  17. 一種半導體裝置之製造方法，其具有以下步驟：(a)準備半導體晶片，該半導體晶片具有第1表面、上述第1表面相反側之第1背面、具有第1接合面之電極墊、及具有上述第1表面且具備將上述電極墊之上述第1接合面露出之第1開口部的絕緣膜；(b)準備引腳框架，該引腳框架具有供固定上述半導體晶片之晶片搭載部、及與上述晶片搭載部分隔之第1引腳；(c)於上述(a)步驟、上述(b)步驟之後，以上述半導體晶片之上述第1背面與上述晶片搭載部相向之方式，將上述半導體晶片搭載於上述晶片搭載部；(d)於上述(c)步驟之後，將第1導線接合於上述半導體晶片之上述第1接合面；及(e)於上述(d)步驟之後，以與上述電極墊之上述第1接合面接觸之方式，以絕緣材料密封上述半導體晶片與上述第1導線；且 上述第1接合面包含金屬，於俯視時，上述第1接合面具有第1區域、第2區域、及位於上述第1區域與上述第2區域之間的第3區域，上述(d)步驟包含以下步驟：(d1)將上述第1導線之上述第1接合部接合於上述第1接合面之上述第1區域；(d2)於上述(d1)步驟之後，將連結於上述第1接合部、且沿著第1方向延伸之上述第1導線之第1中間部以跨越上述第1接合面之上述第3區域之方式成形；及(d3)於上述(d2)步驟之後，將連結於上述第1導線之上述第1中間部之上述第1導線之第2接合部接合於上述第1接合面的上述第2區域；且上述第1導線之上述第1中間部與上述第3區域分隔，於俯視時，與上述第1方向正交之第2方向之上述第1區域之寬度、與上述第2方向之上述第2區域之寬度，大於上述第2方向之上述第3區域的寬度。
  18. 如請求項17之半導體裝置之製造方法，其中上述第1接合面之上述第1區域具有沿著上述第2方向突出之第1突出部，於俯視時，上述第1方向之上述第1突出部之長度短於上述第1方向之上述第1區域的長度，上述(d)步驟包含以下步驟：(d4)於上述(d1)步驟之後，確認上述第1導線與上述第1接合面之位置 關係，基於上述確認之結果調整打線接合位置，且於上述(d4)步驟中，參照上述第2方向之上述第1突出部之長度，確認上述第1導線之上述第1接合部之位置偏移量。
  19. 如請求項17之半導體裝置之製造方法，其中上述第1接合面之上述第3區域具有沿著上述第2方向朝上述第3區域凹陷之第1凹部，且於俯視時，上述第1方向之上述第1凹部之長度短於上述第1方向之上述第3區域的長度，上述(d)步驟包含以下步驟：(d4)於上述(d1)步驟之後，確認上述第1導線與上述第1接合面之位置關係，基於上述確認之結果調整打線接合位置，且於上述(d4)步驟中，確認上述第2方向之上述第1凹部之長度與上述第1導線之上述第1中間部的位置關係。
  20. 如請求項17之半導體裝置之製造方法，其中上述(a)步驟包含使測試用之端子與上述第3區域接觸之步驟。
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