TW200933851A - COL semiconductor package - Google Patents

COL semiconductor package Download PDF

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Publication number
TW200933851A
TW200933851A TW097103600A TW97103600A TW200933851A TW 200933851 A TW200933851 A TW 200933851A TW 097103600 A TW097103600 A TW 097103600A TW 97103600 A TW97103600 A TW 97103600A TW 200933851 A TW200933851 A TW 200933851A
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TW
Taiwan
Prior art keywords
wafer
semiconductor package
lead
wire
package structure
Prior art date
Application number
TW097103600A
Other languages
Chinese (zh)
Inventor
Wan-Jung Hsieh
Chin-Fa Wang
Chin-Ti Chen
Original Assignee
Powertech Technology Inc
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Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW097103600A priority Critical patent/TW200933851A/en
Publication of TW200933851A publication Critical patent/TW200933851A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Disclosed is a COL (Chip-On-Lead) semiconductor package. A plurality of leadframe's leads have a plurality of carrying bars, a plurality of bonding fingers, and a plurality of connecting lines connecting the bars and the fingers. The chip has a backside attached to the bars and is electrically connected to the fingers by a plurality of bonding wires. At least one of the bonding wires overpasses at least one of the connecting lines with the relationship of non-electrical connection. An insulation tape is attached to the connecting lines to prevent short of wire-bonding in the COL package. Accordingly, it is very flexible to arrange the connecting lines of the leads under the chip, this can further save conventional die pad or reduce the dimensions of the die pad.

Description

200933851 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置’特別係有關於〆 種晶片在引腳上（Chip-〇n_Lead，c〇L)之半導體封裝構造。 【先前技術】 在已知的半導體封裝構造中，導線架引腳係可作為 ❹BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device', particularly to a semiconductor package structure in which a wafer is on a pin (Chip-〇n_Lead, c〇L). [Prior Art] In the known semiconductor package construction, the lead frame pin system can be used as a

晶片載體與電性轉接，封裝型態主要可分為兩類：引腳 在晶片上（Lead-On-Chip，LOC)或是晶片在引腳上 (Clnp-On-Lead，COL)，其中所謂的「引腳在晶片上」係將引 腳黏附在晶片形成有積體電路之主動面上；所謂的「晶片在 引腳上」則將晶片之背面黏附於引腳之一區段。並藉由打 線形成之複數個銲線電性連接晶片與導線架引腳。通常 晶片在引腳上」COL封裝内之銲線會相對於「引腳在晶 片上」LOC封裝内之銲線在長度上會更*，故銲線受到 模流產生的也移量會更大。此外，⑽封裝所使用之導 線架引腳，易有支撐性不足的問題，故目前仍需藉由兩 側晶片承座以辅助對晶片之支撐性’進而影響了導線架 引腳在晶片下的配置空間。 請參閱第1及2圖所示’習知c〇L半導體封裝構造 1〇〇係包含複數個導線架引腳11〇、一晶片12〇、複數 個銲線130以及一封膠體15〇。該些導線架引腳11〇係 分別由該封穋體150之兩相對側邊往内延伸，並且該些 導線架引腳110之長度係為非對稱，其中較長一侧之導 線架引腳110係用以貼設該晶片120。該些導線架引腳 200933851 1 1 〇係具有複數個打線指1 1 2以及複數個外引腳1丨4， 該些外引腳11 4係穿出該封膠體1 5 0之側邊並往外延伸 彎折’以供對外接合^該晶片120係具有一主動面121 以及一相對之背面122’該主動面121係設有複數個銲 塾123。該晶片120係利用一黏晶膠帶160之黏貼，使 得該晶片120之該背面122可設置在該些導線架引腳 110上。該些銲線130係電性連接該些銲墊123至該些 打線指11 2。該模封膠體1 5 〇係用以密封該晶片1 2 〇、 〇 該些打線指112以及該些銲線130，但顯露該些導線架 引腳110之該些外引腳114。請參閱第1及2圖所示， 由於該些設有該晶片1 20之導線架引腳丨丨〇係為懸空 狀’缺乏足夠的支撐，故需增設複數個晶片承座17〇以 提升對該晶片1 20之支撐性’避免該晶片1 2〇在後續製 程中產生位移或傾斜之問題’相對使得該些導線架引腳 110在該晶片120下的配置空間縮小。此外，請再參閱 第2圖所示，該晶片120之該些銲塾123須與該些導線 ® 架引腳11 0的排列位置對應排列，以確保該些銲線1 3 〇 之打線方向係與該些導線架引腳110的延伸方向大致 對齊，故習知COL半導體封裝構造1〇〇不但該些導線 架引腳11 0在該晶片1 20下的配置空間縮小並且其内端 必須延伸對齊至晶片之銲墊。當晶片之銲墊位置改變 時’銲線之打線方向會與導線架引腳的延伸方向產生傾 斜角度，使得在打線與模封過程中銲線易於誤觸鄰近無 電性連接之導線架引腳而導致電氣短路。 200933851 【發明内容】 本發明之主I目的係在於提供一種晶片 (C〇L)之半導體封裝構造，可避免COL封裝 路’方便COL封裝中引腳在晶片下之承栽條 而能省略晶片承座或是縮小晶片承座之尺寸、。 本發明之次一目的係在於提供一種晶片在 半導體封裝構造，可阻擋黏晶膠以避免污染至 線架引腳之打線指，故可採用低成本之黏晶材 © 低封裝成本。 本發明的目的及解決其技術問題是採用以 案來實現的。依據本發明所揭示之一種晶片在 半導體封裝構造，主要包含複數個導線架引 片、複數個銲線、一絕緣膠帶以及一封膠體。 架引腳係具有複數個承載條、複數個打線指、 接該些承載條與該些打線指之連接線。該晶片 〇主動面以及-背面’該主動面係設有複數個銲 面係貼設於該些導線架引腳之該些承栽條。該 連接該些銲墊與該些打線指，其中一銲線係跨 個無電性連接關係之連接線。該絕緣膠帶係貼 連接線上。該封膠體係密封該晶片、該些銲線 膠帶以及該些導線架引腳之該些打線指與該些 本發明的目的及解決其技術問題還可採用 措施進一步實現。 在刚述之半導體封裝構造中，該絕緣膠帶 在卩丨腳上 之打線短 配置，進 腳上之 -C〇L 導 料，以降 下技術方 引腳上之 卿、一晶 該些導線 複數個連 係具有一 墊，該背 些銲線係 過至少一 覆於該些 、該絕緣 ，連接線。 以下技術 係可切齊 7 膠體250。 200933851 於該些打線指並與該晶片鄰近於該些銲墊之一侧 平行。 在則述之半導體封裝構造中，可另包含一黏晶 以黏著該晶片之該背面至該些承載條。 在前述之半導體封裝構造中，該絕緣膠帶係可 於該晶片。 在前述之半導體封裝構造中，該些導線架引腳 更具有複數個外引腳，其係連接該些承載條並由該 ❹ 通過該封膠體往外延伸。 在前述之半導體封裝構造中，可另包含有複數 接端子，其係設置於該些承載條之下。 在前述之半導體封裝構造中，該晶片係可為一未 之晶片組。 在前述之半導體封裝構造中，該絕緣膠帶係可 狀並具有單面黏性。 【實施方式】 依據本發明之第一具體實施例，揭示一種晶片 腳上（chip on lead，COL)之半導體封裝構造。其中 此所指「晶片在引腳上」係指晶片的背面（即相街 片主動面之一表面）貼附於導線架的引腳，以達到 之固定。請參閱第3圖所示，一種晶片在引腳上之 體封裝構造200,主要包含複數個導線架引腳2邝 晶片220、複數個知線230、一絕緣膠帶24〇以 及 邊為 膠， 不Γ% 係可 晶片 個外 切割 為條 在引 ，在 於晶 晶片 半導 > —— 一封 8 200933851 請參閱第4圖所示， 該些導線架引腳The wafer carrier and the electrical transfer, the package type can be mainly divided into two types: lead on the wafer (Lead-On-Chip, LOC) or on the chip on the pin (Clnp-On-Lead, COL), wherein The so-called "pin on the wafer" sticks the pin to the active surface of the chip on which the integrated circuit is formed; the so-called "wafer on the pin" sticks the back side of the wafer to one of the pins. The chip and the lead frame pins are electrically connected by a plurality of bonding wires formed by wire bonding. Usually the wafer is on the lead. The bond wire in the COL package will be more * in length than the bond on the "on-wafer" LOC package, so the wire will be transferred more by the die flow. . In addition, (10) the lead frame pins used in the package are prone to insufficient support. Therefore, it is still necessary to support the support of the wafer by the two-sided wafer holders, thereby affecting the lead frame pins under the wafer. Configuration space. Referring to Figures 1 and 2, the conventional semiconductor package structure includes a plurality of lead frame pins 11 〇, a wafer 12 〇, a plurality of bonding wires 130, and a colloid 15 〇. The lead frame pins 11 are respectively extended inwardly from opposite sides of the sealing body 150, and the lengths of the lead frame pins 110 are asymmetrical, wherein the longer side of the lead frame pins The 110 series is used to attach the wafer 120. The lead frame pins 200933851 1 1 have a plurality of wire fingers 1 1 2 and a plurality of outer pins 1丨4, and the outer pins 11 4 pass through the side of the seal body 150 and go out The extension is bent for external bonding. The wafer 120 has an active surface 121 and an opposite back surface 122. The active surface 121 is provided with a plurality of solder pads 123. The wafer 120 is adhered by a die attach tape 160 such that the back side 122 of the wafer 120 can be disposed on the leadframe pins 110. The bonding wires 130 electrically connect the pads 123 to the wire fingers 11 2 . The molding compound 15 is used to seal the wafers 1, 2, and 112, but to expose the outer leads 114 of the lead pins 110. Referring to Figures 1 and 2, since the lead frame of the lead frame provided with the wafer 120 is suspended, it lacks sufficient support, so a plurality of wafer holders 17 are required to enhance the pair. The support of the wafer 1200 'avoids the problem of displacement or tilt of the wafer 1 〇 in subsequent processes' is such that the layout space of the leadframe pins 110 under the wafer 120 is reduced. In addition, please refer to FIG. 2 again, the soldering pads 123 of the wafer 120 are arranged corresponding to the arrangement positions of the lead wires 110 of the wire holders to ensure that the bonding wires of the bonding wires 1 3 The alignment of the lead frame pins 110 is substantially aligned, so that the conventional COL semiconductor package structure 1 not only has a reduced layout space of the lead frame pins 110 under the wafers 1 20 but also has an inner end extending and aligned. Solder pads to the wafer. When the position of the pad of the wafer is changed, the direction of the bonding wire will be inclined at an oblique angle to the extending direction of the lead of the lead frame, so that the bonding wire is easily mistakenly touched by the lead frame pin adjacent to the non-electrical connection during the wire bonding and molding process. Causes an electrical short circuit. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a semiconductor package structure of a wafer (C〇L), which can avoid the COL package path's facilitating the pin under the wafer in the COL package and omitting the wafer carrier. Block or reduce the size of the wafer holder. A second object of the present invention is to provide a wafer in a semiconductor package structure that blocks the adhesive to prevent contamination of the wire fingers of the wire frame pins, so that a low cost adhesive crystal can be used. The object of the present invention and solving the technical problems thereof are achieved by the use of the present invention. A wafer disclosed in the present invention comprises a plurality of lead frame tabs, a plurality of bonding wires, an insulating tape, and a gel. The rack pin has a plurality of carrier strips, a plurality of wire fingers, and a connecting wire connecting the carrier bars and the wire fingers. The active surface of the wafer and the back surface of the active surface are provided with a plurality of soldering surfaces attached to the lead pins of the lead frames. The connecting pads and the wire fingers are connected, and one of the bonding wires is connected to the connecting line of the non-electrical connection relationship. The insulating tape is attached to the connecting line. The sealing system sealing the wafer, the wire bonding tapes, and the wire fingers of the lead frame pins and the objects of the present invention and solving the technical problems thereof can be further implemented by measures. In the semiconductor package structure just described, the insulating tape is shortly arranged on the foot of the foot, and the -C〇L guide material on the foot is used to lower the number of the wires on the technical side pins and the plurality of wires. The connection has a pad, and the back bonding wires are overlaid on at least one of the insulation and the connecting wires. The following techniques are available for the 7 colloid 250. 200933851 refers to the wire fingers and is parallel to the side of the wafer adjacent to one of the pads. In the semiconductor package structure described above, a die bond may be further included to adhere the back surface of the wafer to the carrier strips. In the aforementioned semiconductor package construction, the insulating tape is available for the wafer. In the foregoing semiconductor package construction, the leadframe pins further have a plurality of outer leads that connect the carrier strips and extend outwardly through the sealant. In the foregoing semiconductor package structure, a plurality of terminals may be further included under the carrier strips. In the aforementioned semiconductor package construction, the wafer system can be a non-wafer group. In the foregoing semiconductor package structure, the insulating tape is configurable and has a single-sided adhesiveness. [Embodiment] According to a first embodiment of the present invention, a semiconductor package structure of a chip on lead (COL) is disclosed. The term "wafer on the pin" means that the back side of the wafer (i.e., one surface of the active surface of the phase plate) is attached to the lead of the lead frame to be fixed. Referring to FIG. 3, a wafer package structure 200 on a lead mainly includes a plurality of lead frame pins 2 邝 wafer 220, a plurality of wires 230, an insulating tape 24 〇, and a side glue, Γ% can be externally cut into strips, in the crystal wafer semi-conducting> —— an 8 200933851 See Figure 4, the leadframe pins

架引腳210係取自於 I承載條211、複數個打線指 乞條211與該些打線指212之 2 11係指該些導線架引腳2 1 0 段’由該封膠體250之同一侧 ’以供承載該晶片220。並且 片220之内引腳係包含該些連 接線213與該些打線指212。請參閱第4圖所示，該些 © 承載條211之寬度係可大於該些打線指212之寬度，以 提供該晶片220較佳的支撐面積，並可增加該晶片22〇 在後續之打線步驟及/或封膠步驟等製程步驟中之晶片 穩固性，增加產品良率。在本實施例中，該些導線架引 聊210係可更具有複數個外引腳214，其係連接該些承 載條211穿出該封膠體2 5 0(如第3圖所示）之側邊並往 外延伸彎折，以供接合至一外部印刷電路板（圖中未繪 出）。該些外引腳214係可彎折成海鷗腳（gull lead)，或 可彎折成其他形狀，如I形或J形。 請參閱第3圖所示，該晶片220係具有一主動面221 以及一背面222,該主動面221係設有複數個銲墊22 3, 該背面222係貼設於該些導線架引腳210之該些承載條 2 1 1。該些銲墊2 2 3係排列於該晶片2 2 0之單一侧邊， 而該些打線指212係鄰近於該些錄墊223 ’藉以縮短該 些銲線230之打線長度。具體而言，該半導體封裝構造 2〇〇係可另包含一黏晶膠260，以黏著該晶片220之該 200933851 背面222至該此承 一栽條211。較佳地，如第7圖所示， 藉由該絕緣膠帶24〇 _ a ^ 之阻播’該黏日日膠260係可選自於 B階膠體與液態脒 日於 膠之其中之一，以降低封裝成本。因 此’不需要使用習知晶片承座便可提供較佳的支撐性， 更能使該些導線架引腳21〇在該晶片220之下方配置空 間更，’該些承栽冑211之設計更有廣泛的選擇與變 化月參閱第5及6圖所示，該些銲、線230之第一端 2 3 1係連接該也録執 ❹ t 一知塾223並且第二端232係連接於該些 其中一銲線230A係跨過至少一個無電性 連接關係之連接線213A。請參閱第5圖所示，每—銲 線230之第一端231係可為起始端，而該第二端232則 為、舳即為由該晶片220至該些打線指212(導線架 引腳:的正向打線。但不受限制地’該些銲線230亦可 ,'、 S _打線指2 1 2(導線架引腳）連接至該晶片220的 逆向打線。 請參閲筮 < 弟6及7圖所示，該絕緣膠帶240係貼覆於 該些連接線 21 1 L L χ _ 上，能防止上述跨過引腳之銲線23 〇 a 因受到模流J ^ γ t 度生位移或下垂而導致與位於其下方且無 電佳連接關係之連接線213Α發生短路的問題。在本實 施例中仁不雙限制地，該絕緣膠帶240係為條狀並具有 單面黏陡即可，以黏附於該些連接線213。具體而言， 〜絕緣膠帶2 4 0係可切齊於該些打線指2 1 2並與該晶片 2 2 0鄰近於兮 <銲墊223之一側邊為平行，可阻擋該黏 曰曰移 '亏染至該些打線指2 1 2。較佳地，該絕緣膠帶 200933851 240係可略高於該黏晶膠260，達到更佳的防止溢膠效 果。請參閱第7圖所示，該絕緣膠帶24〇係可不高於該 晶片220，以不影響該些銲線230之弧高。請參閱第3 圖所示，該封膠體250係密封該晶片220、該些鋒線 230、該絕緣膠帶240以及該些導線架引腳21〇之該些 打線指2 1 2與該些連接線2 1 3，以避免上述元件受到外 界污染物的污染。 因此’該導線架引腳210之該些承載條211能依需 0 求適當加寬以增加該晶片220的支撐面積，且該導線架 引腳2 1 〇之該些連接線2 1 3能依照不同銲墊配置之晶片 之需求做適當的彎折或傾斜，方便COL封裝之該些導 線架引腳2 1 0之該些承載條2丨丨之配置以省略晶片承座 或縮小晶片承座之尺寸。此外’藉由該絕緣膠帶240之 設計能有效防止該鲜線230A誤觸鄰近無電性連接關係 之連接線213A，以避免COL封裝之打線短路。另，可 選用液態或膠稠態之黏晶膠260以降低封裝成本而不 ® 會有該黏晶膠26〇污染至該些打線指2 1 2之問題。 在本發明之第二具體實施例中，揭示另一種晶片在 引腳上之半導體封裝構造，請參閱第8圖所示，該半導 體封裝構造3 00主要包含複數個導線架引腳31〇、一 日曰 片320、複數個銲線330、至少一絕緣膠帶34〇以及一 封膠體350。請參閱第9圖所示，該些導線架引腳31〇 係具有複數個承載條311、複數個打線指312、複數個 連接該些承載條311與該些打線指312之連接線313。 200933851 該些導線架引腳310之内端係分別由該封膠體350之兩 相對侧邊往該晶片3 2 0之背面3 2 2之中心線延伸’而該 些打線指312係遠離該些導線架引腳“ο之内端。該些 導線架引腳310更可具有複數個外接墊3 14(如第9圖所 示），其係形成於該些承載條311之非承載面。在此所 指「非承載面」係指該些承載條3丨丨用以貼附該晶片 320之另一相對表面。請參閱第8圖所示，該晶月32〇 係具有一主動面321以及一背面322，該主動面321係 ❹設有複數個銲墊3 23，該背面322係貼設於該些導線架 引腳310之該些承載條311。請參閱第1〇圖所示，在 本實施例中’該些銲墊3 2 3係分別排列於該晶片3 2 0之 兩相對側邊。較佳地’該晶片3 2〇係可為一未切割之晶 片組，包含了兩個或以上但未切割之積體電路晶片（如 第1 0圖所示該晶片3 2 0之中間虛線即為未切割之晶圓 切割道）。該晶片320係可利用一黏晶膠36〇之黏著使 該晶片320之該背面322黏貼至該些承載條311。該黏 ® 晶膠360係可預先形成於該晶片320之該背面322，例 如半固化之晶背黏貼膠材（Die Attach Material， DAM)，該黏晶膠360在加熱時會產生黏著力。在適當 之壓合壓力與加熱溫度下’該黏晶膠360能黏接至該些 承載條311’以使該晶片320係貼設於該些承载條311。 請參閱第10圖所示，該些銲線330係連接該歧鲜塾 323與該些打線指312,其中一銲線330Α係跨過至少一 個無電性速接關係之連接線313Α。該絕緣膠帶34〇係 12 200933851 貼覆於該些連接線313上，以避免該銲線33〇A誤觸鄰 近且無電性連接關係之連接線313A而造成短路。請參 閱第8圖所示，該封膠體35〇係密封該晶片32〇、該些 銲線330、該絕緣膠帶34〇以及該些導線架引腳3ι〇之 該些打線指312與該些連接線313。請參閱第8及9圖 所示，該半導體封裝構造3〇〇係可另包含有複數個外接 端子370，其係設置於該些承載條3ιι之該些外接墊 3 14。因此，本發明能方便c〇L封裝之引腳承載條3ιι 〇之配置’以電性連接不同銲墊排列之晶片之功效，並可 避免COL封裝之打線短路。 述’僅是本發明的較佳實施例而已，並非 本發明作任何形式上的限制，本發明技術方案範圍當 所附申請專利範圍為準。任何熟悉本專業的技術人員 :用上述揭示的技術内容作出些許更動或修飾為等 :化的等效實施例，但凡是未脫離本發明技術方案的 ❹The rack pin 210 is taken from the I carrier bar 211, the plurality of wire finger bars 211 and the wire fingers 212 are referred to as the lead pins 2 1 0 segment 'by the same side of the sealant 250 'For carrying the wafer 220. And the pins in the chip 220 include the connecting wires 213 and the wire fingers 212. Referring to FIG. 4, the width of the © carrier strips 211 may be greater than the width of the wire fingers 212 to provide a better support area for the wafer 220, and the wafer 22 may be added to the subsequent wire bonding step. And the stability of the wafer in the process steps such as the sealing step, and the product yield is increased. In this embodiment, the lead frame reference 210 may further have a plurality of outer pins 214 connected to the side of the carrier strip 211 to pass through the sealant 250 (shown in FIG. 3). The edges are extended outwardly and bent for bonding to an external printed circuit board (not shown). The outer leads 214 can be bent into a gull lead or can be bent into other shapes, such as an I or J shape. As shown in FIG. 3 , the wafer 220 has an active surface 221 and a back surface 222 . The active surface 221 is provided with a plurality of pads 22 3 . The back surface 222 is attached to the lead pins 210 . The carrier strips 2 1 1 . The pads 2 2 3 are arranged on a single side of the wafer 210 , and the wire fingers 212 are adjacent to the pads 223 ′ to shorten the wire length of the wires 230 . Specifically, the semiconductor package structure 2 may further comprise an adhesive 260 for adhering the back surface 222 of the 200933851 of the wafer 220 to the substrate 211. Preferably, as shown in FIG. 7, the adhesive tape 24 可 a ^ can be selected from the B-stage colloid and the liquid one-day glue. To reduce packaging costs. Therefore, 'the use of the conventional wafer holder can provide better support, and the lead frame pins 21 can be disposed under the wafer 220, and the designs of the trays 211 are further improved. There are a wide selection and change month. Referring to Figures 5 and 6, the first end of the soldering wire 230 is connected to the second end, and the second end 232 is connected to the second end 232. One of the bonding wires 230A spans at least one connection line 213A having no electrical connection relationship. Referring to FIG. 5, each of the first ends 231 of the bonding wires 230 may be a starting end, and the second end 232 is a turn, that is, from the wafer 220 to the wire fingers 212 (lead frame lead) The forward line of the foot: but unrestricted 'the wire 230 can also be, ', S _ wire finger 2 1 2 (lead frame pin) is connected to the reverse wire of the wafer 220. See 筮&lt As shown in the figures 6 and 7, the insulating tape 240 is attached to the connecting wires 21 1 LL χ _ to prevent the above-mentioned lead wire bonding wire 23 〇a from being subjected to the mold flow J ^ γ t degree. The problem that the displacement or sagging causes a short circuit with the connection line 213 位于 which is located underneath and has no electrical connection relationship. In the present embodiment, the insulating tape 240 is strip-shaped and has a single-sided adhesion steepness. The bonding tape 213 may be adhered to the connecting wires 213. Specifically, the insulating tape 240 may be aligned with the wire fingers 2 1 2 and adjacent to the wafer 2 2 0 adjacent to the 兮 < solder pad 223 The side edges are parallel, which can block the adhesive from shifting to the wire fingers 2 1 2 . Preferably, the insulating tape 200933851 240 can be slightly higher than the die bond Glue 260, to achieve better anti-overflow effect. Please refer to Figure 7, the insulating tape 24 can be no higher than the wafer 220, so as not to affect the arc height of the bonding wires 230. Please refer to Figure 3. As shown, the encapsulant 250 seals the wafer 220, the front wires 230, the insulating tape 240, and the wire fingers 2 1 2 of the lead frame pins 21 and the connecting wires 2 1 3 to avoid The above components are contaminated by external contaminants. Therefore, the carrier strips 211 of the lead frame pins 210 can be appropriately widened according to the requirements of 0 to increase the support area of the wafer 220, and the lead frame pins 2 1 The connecting wires 2 1 3 can be appropriately bent or tilted according to the requirements of the different pad configuration wafers, so as to facilitate the configuration of the carrier strips 2 of the lead frame pins 210 of the COL package to omit The wafer holder or the size of the wafer holder is reduced. In addition, the design of the insulating tape 240 can effectively prevent the fresh wire 230A from accidentally touching the connection line 213A adjacent to the non-electrical connection relationship, thereby avoiding the short circuit of the COL package. Liquid or gel-bonded viscous gel 260 can be used to reduce The cost of the package is not affected by the problem that the adhesive is contaminated to the wire fingers 2 1 2. In the second embodiment of the present invention, another semiconductor package structure on the lead is disclosed. Referring to FIG. 8, the semiconductor package structure 300 mainly includes a plurality of lead frame pins 31, a one-day chip 320, a plurality of bonding wires 330, at least one insulating tape 34, and a gel 350. As shown in FIG. 9, the lead frame pins 31 have a plurality of carrier strips 311, a plurality of wire fingers 312, and a plurality of connecting wires 313 connecting the carrier bars 311 and the wire fingers 312. 200933851 The inner ends of the leadframe pins 310 extend from the opposite sides of the sealant 350 to the center line of the back surface 32 2 of the wafer 300, and the wire fingers 312 are away from the wires. The lead pins of the rack pins ο. The lead frame pins 310 may further have a plurality of external pads 3 14 (as shown in FIG. 9 ) formed on the non-load bearing surfaces of the carrier strips 311 . By "non-load bearing surface" is meant the other opposing surface of the carrier strips 3 for attaching the wafer 320. As shown in FIG. 8, the crystal moon 32 has an active surface 321 and a back surface 322. The active surface 321 is provided with a plurality of pads 323 attached to the lead frames. The carrier strips 311 of the pins 310. Referring to Fig. 1, in the present embodiment, the pads 3 2 3 are respectively arranged on opposite sides of the wafer 3 2 0 . Preferably, the wafer 32 can be an uncut wafer set comprising two or more but uncut integrated circuit wafers (as shown in FIG. 10, the middle dashed line of the wafer 300 is Cut the etched wafers). The wafer 320 is adhered to the carrier strips 311 by adhesion of a die bond 36. The adhesive 360 can be preformed on the back side 322 of the wafer 320, such as a semi-cured Die Attach Material (DAM), which will create adhesion when heated. The adhesive glue 360 can be adhered to the carrier strips 311' at a suitable press pressure and heating temperature to cause the wafers 320 to be attached to the carrier strips 311. Referring to FIG. 10, the bonding wires 330 are connected to the squeegee 323 and the wire fingers 312, and one of the bonding wires 330 is traversed by at least one connection line 313 无 of the non-electricity quick-connecting relationship. The insulating tape 34 is attached to the connecting wires 313 to prevent the wire 33A from being inadvertently contacted by the connecting wire 313A in the vicinity of the electrical connection. Referring to FIG. 8 , the sealing body 35 seals the wafer 32 , the bonding wires 330 , the insulating tape 34 , and the wire fingers 312 of the lead pins 3 . Line 313. Referring to Figures 8 and 9, the semiconductor package structure 3 can further include a plurality of external terminals 370 disposed on the plurality of external pads 3 14 of the carrier strips 3 ι. Therefore, the present invention can facilitate the configuration of the pin carrier strips of the c〇L package to electrically connect the wafers of different pads, and can avoid short-circuiting of the COL package. The present invention is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art: using the technical content disclosed above to make some modifications or modifications to equivalent embodiments, but without departing from the technical solution of the present invention

::依據本發明的技術實質對以上實施例所作的任何 單修改、等同變介I 範圍内。 …飾’均仍屬於本發明技術方案 圖式簡單說明】 第1圖 第2圖 第3圖 1知半導體封裝搂4+ 可装構造之截面不意圖。 習头〇半導體封裝 I構造在封膠前導線架引腳之 視示意圖。 依據本發明之第一 乐具體實施例’一種晶片在 聊上之半導髏封裝構造之截面示意圖。 13 200933851 第4圖.依據本發明之第_具體實施例，該半導體封裝 構造在封膠前導線架引腳之俯視示意圖。 第5圖.依據本發明之第一具體實施例，該半導體封裝 構造在封膠前導綠架引腳之局部立體示意圖。Any single modification or equivalent variation of the above embodiments in accordance with the technical essence of the present invention. The decoration of the present invention still belongs to the technical solution of the present invention. FIG. 1 is a schematic diagram of the present invention. FIG. 1 is a schematic view of the semiconductor package 搂4+. Xitou Semiconductor Package I is a schematic view of the lead of the lead frame before sealing. A cross-sectional view of a semi-conductive package structure of a wafer in accordance with a first embodiment of the present invention. 13 200933851 Figure 4. In accordance with a first embodiment of the present invention, the semiconductor package is constructed in a top view of the leads of the leadframe prior to encapsulation. Fig. 5 is a partial perspective view showing the semiconductor package in the green lead of the green lead frame in accordance with the first embodiment of the present invention.

第6圖：依據本發明S Θ ML 义第—具體實施例，該半導體封裝 構2^在封膠則導線架引腳之局部俯視示意圖。 第7圖·依據本發明之第—具體實施例，該半導體封裝 構造在封膠前之局部截面示意圖。 ❹ ❹ 第8圖：依據本發明之第二具體實施例，另一種晶片在 引腳上之半導體封裝構造之截面示意圖。 第9圖：依據本發明之第二具體實施例，該半導體封裝 構造中導線架弓丨聊之俯視示意圖。 第10圖：依據本發明夕哲 像不贊月之第二具體實施例，該半導體封 裝構造在封膠前導線架引腳之俯視示意圖 【主要元件符號說明】 100半導體封裝構造 114外引腳 122背面 150封膠體 110導線架引腳112打線指 120晶片 121主動面 123銲墊 130銲線 160黏晶膠帶 170晶片承座 200半導體封裝構造 210導線架引腳211承載條 212打線指 213連接線 213A無電性連接關係之連接線 214外引腳 14 200933851 220 晶片 221 主動面 222 背面 223 銲塾 230 銲線 230A銲線 231 第一端 232 第二端 240 絕緣膠帶 250 封膠體 260 黏晶膠 300 半導體封裝構造 310 導線架引腳 311 承載條 312 打線指 313 連接線 313A無電性連接關係之連接線 314 外接墊 320 晶片 321 主動面 322 背面 323 銲墊 330 銲線 330A銲線 340 絕緣膠帶 350 封膠體 360 黏晶膠 370 外接端子 ❹ 15Figure 6 is a partial top plan view of the lead frame pins of the semiconductor package in accordance with the present invention, in accordance with the present invention. Figure 7 is a partial cross-sectional view of the semiconductor package structure prior to encapsulation in accordance with a first embodiment of the present invention. ❹ ❹ FIG. 8 is a cross-sectional view showing another semiconductor package structure on a lead according to a second embodiment of the present invention. Figure 9 is a top plan view of a lead frame in a semiconductor package structure in accordance with a second embodiment of the present invention. FIG. 10 is a top plan view showing the lead of the lead frame of the semiconductor package before sealing according to the second embodiment of the present invention. [Main component symbol description] 100 semiconductor package structure 114 outer pin 122 Back 150 sealant 110 lead frame pin 112 wire finger 120 wafer 121 active surface 123 pad 130 wire 160 adhesive tape 170 wafer holder 200 semiconductor package structure 210 lead frame pin 211 carrier bar 212 wire finger 213 cable 213A Connection line 214 with no electrical connection 141 Outer pin 14 200933851 220 Wafer 221 Active surface 222 Back 223 Soldering wire 230 Wire bonding wire 230A Bonding wire 231 First end 232 Second end 240 Insulating tape 250 Sealing body 260 Adhesive plastic 300 Semiconductor package Structure 310 Lead frame lead 311 Carrier strip 312 Wire finger 313 Connection line 313A Electrical connection relationship 314 External pad 320 Wafer 321 Active surface 322 Back 323 Pad 330 Solder wire 330A Solder wire 340 Insulation tape 350 Sealing body 360 Adhesive Crystal glue 370 external terminal ❹ 15

Claims (1)

200933851 十、申請專利範園： 1、一種晶片在引腳上之半導體封裝構造，包含： 複數個導線架引腳，係具有複數個承載條、複數個打線 指以及複數個連接該些承載條與該些打線指之連接線； 一晶片，係具有一主動面以及一背面，該主動面係設有 複數個銲墊，該背面係貼設於該些導線架引腳之該些承 載條； 複數個#線，係連接該些銲墊與該些打線指，其中一銲 Ο 線係跨過至少一個無電性連接關係之連接線； 一絕緣膠帶，係貼覆於該些連接線上；以及 一封膠體，係密封該晶片、該些銲線、該絕緣膠帶以及 該些導線架引腳之該些打線指與該些連接線。 2、 如申請專利範圍第丨項所述之晶片在引腳上之半導體封 裝構造，其中該絕緣膠帶係切齊於該些打線指並與該晶 片鄰近於該些銲墊之一側邊為平行。 3、 如申請專利範圍第項所述之晶片在引腳上之半導 體封裝構造’另包含一黏晶膠，以黏著該晶片之該背面 至該些承載條。 4、 如申請專利範圍第3項所述之晶片在引腳上之半導體封 裝構造，其中該黏晶膠係可選自於3階膠體與液態膠 之其中之一。 5、 如申請專利範圍第3項所述之晶片在引腳上之半導體封 裝構造，其中該黏晶膠係為晶背黏貼膠材（Die Auach Material, DAM)。 200933851 6、 如申請專利範圍第i項所述之晶片在引腳上之半導體封 裝構造，其中該絕緣膠帶係不高於該晶片。 7、 如申請專利範圍第！項所述之晶片在引腳上之半導體封 裝構造，其中該些導線架引腳係更具有複數個外引腳， 其係連接該些承載條並由該晶片通過該封膠體往外延 伸。 8、 如申請專利範圍第i項所述之晶片在引腳上之半導體封 裝構造’另包含有複數個外接端子，其係設置於該些承 栽條之下。 9、 如申請專利範圍帛i項所述之晶片在引腳上之半導體封 裝構造，其中該晶片係為一未切割之晶片組。 10、 如申請專利範圍第！項所述之晶片在引腳上之半導體 封裝構造，其中該絕緣膠帶係為條狀並具有單面黏 性。 ❹ 17200933851 X. Application for Patent Park: 1. A semiconductor package structure on a pin, comprising: a plurality of lead frame pins, having a plurality of carrier strips, a plurality of wire fingers, and a plurality of connecting the carrier bars and The wire is a connecting wire; a chip having an active surface and a back surface, the active surface is provided with a plurality of solder pads, the back surface is attached to the carrier strips of the lead pins; a #线, connecting the pads and the wire fingers, wherein one of the wire bonds spans at least one connection line having no electrical connection; an insulating tape is attached to the wires; and a wire The colloid seals the wafer, the bonding wires, the insulating tape, and the wire fingers of the lead frame pins and the connecting wires. 2. The semiconductor package structure of the wafer on the lead according to claim 2, wherein the insulating tape is aligned with the wire fingers and is parallel to a side of the wafer adjacent to one of the pads. . 3. The semiconductor package structure on the lead of the wafer of claim 1 further comprises a die attach adhesive to adhere the back side of the wafer to the carrier strips. 4. The semiconductor package structure of the wafer on the lead according to claim 3, wherein the adhesive layer is selected from one of a third-order colloid and a liquid glue. 5. The semiconductor package structure of the wafer on the lead according to claim 3, wherein the adhesive is a Die Auach Material (DAM). 200933851 6. The semiconductor package structure of the wafer on the lead according to claim i, wherein the insulating tape is not higher than the wafer. 7, such as the scope of patent application! The semiconductor package structure of the wafer on the lead, wherein the leadframe pins further comprise a plurality of outer leads which are connected to the carrier strips and extend from the wafer through the encapsulant. 8. The semiconductor package structure of the wafer on the pin as described in claim i further includes a plurality of external terminals disposed under the plurality of carriers. 9. A semiconductor package structure on a lead of a wafer as claimed in claim ii, wherein the wafer is an uncut wafer set. 10. If you apply for a patent scope! The semiconductor package structure of the wafer on the lead, wherein the insulating tape is strip-shaped and has a single-sided adhesive. ❹ 17
TW097103600A 2008-01-30 2008-01-30 COL semiconductor package TW200933851A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI503905B (en) * 2013-05-09 2015-10-11 矽品精密工業股份有限公司 Wire-bonding structure
TWI728983B (en) * 2015-08-13 2021-06-01 美商賽普拉斯半導體公司 Tape chip on lead using paste die attach material and method of packaging a semiconductor device
TWI745516B (en) * 2017-04-27 2021-11-11 日商瑞薩電子股份有限公司 Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI503905B (en) * 2013-05-09 2015-10-11 矽品精密工業股份有限公司 Wire-bonding structure
TWI728983B (en) * 2015-08-13 2021-06-01 美商賽普拉斯半導體公司 Tape chip on lead using paste die attach material and method of packaging a semiconductor device
TWI745516B (en) * 2017-04-27 2021-11-11 日商瑞薩電子股份有限公司 Semiconductor device and manufacturing method thereof

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