503541 A7 B7 五、發明說明（1 ) 發明領域： 本發明係關於用於降低導通電阻，提高導通電流及增力口 散熱效率之半導體功率元件之封裝方法及其裝置，尤指一 種利用兩個汲極接點分別固接在第一、第二金屬導線架上 的第一、第二兩個垂直式功率元件，相互疊接構成並聯結 構，並使該第一、第二導線架搭接成上、下雙金屬板，利 用上層金屬板擴大散熱的封裝表面。 發明背景： 查，習知半導體功率元件裝置，諸如使用於高速切換開 關元件之功率金氧半場效電晶體（M0SFET )，使用於電力 切換開關之絕緣閘極雙極性電晶體（IGBT )，雙載子接面 電晶體（B】T )，功率二極體（DIODE )，或整流器 (RECTIFIER)等，傳統單一功率元件裝置，汲極/源極 (或集極/射極）之導通電阻（即，RDS-0N )大，相對地功 率損耗也大，並且伴隨產生較大熱量，進而影響其產品使 用壽命。故而，如何降低導通電阻，提高導通電流及增加 散熱效率，提昇產品特性，爲高功率半導體業者所急欲解 決之課題。惟，若從傳統電路設計方面著手改善，不但增 加功率元件電路及結構的複雜性，且硏發時間長、成本非 常高。因此，發明人等朝向將實質上兩個功率元件結合成 一個並聯結構之方向思考，發現以此結構方式不但製程簡 單，且該半導體功率元件裝置之導通電阻値可降低二分之 一，其電流値流經兩並聯路徑耐流可加倍，並且由兩個導 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閱讀背面之注音？事項再填寫本頁) ▼裝·----- -- 訂- -------II 線· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 503541 A7 ___B7 五、發明說明（2 ) 線架構成上、下雙金屬板之擴大散熱的封裝表面，經由上 層金屬板藉外部空氣散熱效率可達加倍效果，並且節省封 裝空間，遽爾完成本發明。 先前技術: 中華民國發明專利公告第426850號，揭示一種「瀑布 堆疊式晶片模組」，其主要包括：一積層板，該積層板上 至少具有複數個接點；複數個晶片，配置於此積層板上， 其中每一晶片包括有複數個焊墊；一重配置層，配置並電 連接於該些焊墊上；一第一絕緣層，配置於上述重配置層 與焊墊之間’且藉由複數個插塞使重配置層與焊墊成電氣 性連接。複數個凸塊接點，分別配置於重配置層上之第一 、第二區域，其中第一、第二區域中的凸塊接點以鏡像方 式配置，且每二對應之凸塊接點均藉由重配層電連接；其 中上述晶片分爲第一、二列交錯疊合，第一列晶片的第一 區域，面對第二列晶片的第二區域，而第一列晶片的第二 區域，面對第二列晶片的第一區域，且面對面之第二區域 與第一區域對應之凸塊接點，分別以一導電凸塊連接。另 外，二軟片式承載器，分別將該二列晶片之二端的晶片電 連接至積層板之接點。 另外，中華民國發明專利公告第423082號，揭示一種 「高積體的晶片疊上晶片封裝」，其主要包括：一晶片疊 上晶片模組，該模組設有至少兩個在電氣上連接在一起的 作用區之獨立晶片，其中該兩個晶片之作用區係相互面對 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —I------------------------線· (請先閱讀背面之注音？事項再填寫本頁) 503541 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（3 ) ;以及一晶片疊上晶片組件連接裝置，用以在電氣上將該 等晶片連接到外部電路。 發明槪沭： 本發明之主要目的在於提供一種用於降低導通電阻，，提 升導通電流及增加散熱效率，並且節省封裝體積之半導體 功率元件裝置，其係將汲極接點分別固接在第一、第二金 屬導線架上的第一、第二兩個垂直式功率元件相互疊接， 使實質上兩個功率元件結合成一個並聯結構；因此，該半 導體功率元件裝置之導通電阻値（rds.qn )可降低二分之 一％其電流値流經兩並聯路徑使耐流可加倍，並且由兩個 導線架構成上、下雙金屬板之擴大散熱的封裝表面，藉由 上金屬板散熱，散熱效率可達加乘效果。 本發明之另一目的在於提供一種用於降低導通電阻，提 升導通電流及增加散熱效率，並且節省封裝體積之半導體 功率元件之封裝方法，其步驟包括：首先，將第一與第二 兩個垂直式功率元件對稱地固設在第一與第二兩導線架上 ’汲極接點分別與導線架成電氣性連接；其中第一導線架 之一端延伸有一接腳’及包含兩分離的個別接腳；第二導 線架之一端包含有垂直延伸的側壁與搭接面。其次，將第 一功率兀件之閘極與源極接點打金屬線，分別與個別接腳 成電氣性連接；通過錫爐，經錫球移載裝置將錫球移植在 第一、第二功率元件之閘極與源極接點，及第一與第二導 線架之搭接面上。然後將第二導線架覆接在第一導線架上 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---------^ —Aew— (請先閱讀背面之注意事項再填寫本頁) 503541 經濟部智慧財產局員工消費合作社印製 A7 B7 1、發明說明（4) ’並使第二功率元件與第一功率元件之閘極與閘極、源極 與源極接點相對疊接。再通過烤箱，加熱並加壓使錫球熔 融，而使第一、第二功率元件及第一、第二導線架相對焊 接在一起。最後經塑膠鑄模材料封裝，使第一及第二導線 架在半導體功率元件裝置表面形成三維空間擴大散熱的裸 表面。 圖式簡單說明= 對於本發明上述目的及其他目的，特點及功效進一步的 實質瞭解，謹配合附圖所示實施例說明如下·· 第1圖爲本發明之半導體功率元件裝置之立體圖，其中 (A)圖爲上視立體圖；（B)圖爲底視立體圖；圖 爲封裝前之分解狀態立體圖。 第2圖爲本發明半導體功率元件裝置封裝之中間步驟側 視圖，其中塑膠模鑄材料以假想線表示。 第3圖爲本發明半導體功率兀件裝置的封裝步驟示意圖 〇 第4圖爲本發明半導體功率元件裝置之電子電路圖。 第5圖爲本發明半導體功率元件裝置之等效電路圖。 第6圖爲本發明半導體功率元件另一種實施型態示意圖 〇 第7圖爲本發明半導體功率兀件另一種封裝型態示意圖 〇 第8圖爲本發明實施在平面式佈局之半導體功率元件之 $紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------1 裝------丨訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 503541 A7 B7___ 五、發明說明（5 ) 實施型態示意圖。 發明之詳細說明： 首先說明’本發明所涉及之半導體功率元件，諸如使用 於電子電路元件之功率金氧半場效電晶體（M0SFET )，或 者絕緣閘極雙極性電晶體（I GBT )等，上述之半導體功率 元件爲垂直式佈局，即汲極（Drain) /或集極（Collector )在下面，而源極（Source) /或射極（Emitter)及閘極 (Gate)在上面的佈局方式，其中該功率元件亦可包含二 極體（DIODE)，及整流器（RECTIFIER)，以及雙載子接 面電晶體（B] T )。以下將配合附圖實施例說明本發明應 用於降低導通電阻，提高導通電流及增加散熱效率，並且 節省封裝空間之半導體功率元件裝置及其封裝方法。 請參考第1圖並對照第2圖，本發明之半導體功率元件 裝置1，其包括：第一功率元件Q1與第二兩個功率元件 Q2，該等功率元件Qi，Q2之閘極區G1與閘極區G2，源極 區S 1與源極區S2相對應地疊接在一起，並接引出有個別 接腳G，S ;上述功率元件Ql，Q2之汲極Dl，D2，分別連 接在第一金屬導線架10與第二兩金屬導線架20上。其中 第一導線架1 0之一端包含有一接腳D，另一端朝外延伸有 一固定裝著的設接面1 1，並設有固定孔1 2 ;第二導線架 2◦之一端包含有垂直延伸的側壁2 1與搭接面22，搭接在 第一導線架1 〇之設接面U上，另一端伸設有一接腳D，搭 接在第一導線架1 〇之接腳D上。如此，由實質上兩個功 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------·裝--------訂-------- (請先閱讀背面之注意事項再填寫本頁) 503541 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6 ) 率兀件Q1，Q 2結合成一個並聯結構，並且該第一導線架 1 〇及第二導線架20，兩者搭接成上、下雙金屬板，利用 上層金屬板擴大散熱的封裝表面。 請再參考第3圖，上述半導體功率元件裝置1之封裝方 法，其步驟包括： ’ 步驟一：先將第一功率元件Q1與第二功率元件Q2對稱 地固設在第一導線架1 0與第二兩導線架2 0上，汲極接點 Dl’ D2分別與導線架10，20成電氣性連接；其中第一導 線架1 0之一端延伸有一接腳D，及包含兩分離的個別接腳 G，S ;第二導線架20之一端包含有垂直延伸的側壁2 1與 搭接面22，另一端延伸有一接腳D’。 ^ 步驟二：將第一功率元件Q1之閘極G1與源極S1接點 打金屬線，分別與個別接腳G，S成電氣性連接。 步驟三：通過錫爐，經錫球移載裝置（圖中未示出）將 錫球30分別移植在第一、第二功率元件qi，q2之閘極G1 ，G2與源極SI ’ S2接點，及第一與第二導線架1〇，2〇之 搭接面D，2 2上。 步驟四：將第二導線架20覆接在第一導線架1 〇上，並 使第二功率元件Q2與第一功率元件qi之閘極區^2與閘 極區G1，源極區S 2與源極區S 1接點相對疊接；再通過烤 箱（圖中未示出）’加熱並加壓使錫球30熔融，而使第 一、第二功率元件Ql，Q2及第一、第二導線架1〇，2〇相 對焊接在一起。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — 1!! i i· — !— --I I--^ Aw 「靖先閱磧背¾vii意事項再填寫本頁) 503541 經濟部智慧財產局員工消費合作社印製 A7 _B7____ 五、發明說明（7 ) 步驟五：最後，經塑膠鑄模材料40封裝，使第一及第 二導線架1 0，20在半導體功率元件裝置1表面形成上、 下雙金屬板，利用上層金屬板擴大散熱的封裝表面。 如上述，利用本發明之半導體功率元件裝置及其封裝方 法，實質上由兩個功率元件經由金屬焊接材料來焊接結合 成一個並聯結構，因此可產生如下的功效： (1 )電流從汲極端D流至源極端S時，流經兩並聯路徑 故耐電流：I D可加倍（如第4圖所示）。 (2 )源極與汲極間之導通電阻値RDS ( ON )變小，約爲原 來二分之一（如第5圖所示），即該兩功率元件之導通電 阻値Rds丨【其係VG丨之函數，Rds】会f ( VG】））】，及rds2 【其係VG2之函數’ RDS20f (vc}2))】之並聯電阻値。 (3 )崩潰電壓不變。 (4 )封裝後體積不變。 (5)弟一及第一導線架在半導體功率元件裝置表面形 成上、下雙金屬板利用上層金屬板擴大散熱的封裝表面（ 成如第1 A及1 B圖所示），散熱效率可達加乘效果。 另外’又如第6圖所示，因應半導體功率元件裝置微小 化’在細微加工製程中實際上可應用的空間極其有限，爲 避免打線時閘極G 1與接腳G連接的金屬線跨越源極s 1區 ，容易造成短路不良率，因此功率元件q 1，Q2之排列， 可將閘極G 1區以與接腳G相同方向及相對於最短距離而 設置。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） - - -----I -----------^---------^ (請先閲讀背面之注意事項再填寫本頁) 503541 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（8 ) 第7圖所示，爲本發明半導體功率元件裝置丨另一種封 裝型態’此實施例不同之處在於，封裝時係將第二導線架 20 (上層金屬板）表面予以塑膠鑄模材料4〇絕緣，避免 該上層金屬板被誤觸，並且可利用該表面標示型號等。 此外’如第8圖所示，本發明同樣地可實施在平面式佈 局之半導體功率元件裝置1之封裝型態上。本實施例之構 造及封裝方法如同上述實施例，因此不再贅述，本實施例 不同之處在於，將第一導線架1 〇上之第一功率元件Q1之 閘極G 1、汲極D1與源極S 1接點分別打上金屬線，與個別 接腳G ’ D，S成電氣性連接；將第二導線架20上之第二 功率元件Q2之閘極G2、汲極D2與源極S2接點，對應疊 接在第一導線架10上第一功率元件Q1之閘極G1、汲極 D1與源極S1接點上。如此，同樣地可達到本發明之目的 與功效。 以上’僅爲本發明的較佳實施例，並不侷限本發明的封 裝型式及其實施範圍，即不偏離本發明申請專利範圍所作 之均等變化與修飾，應仍屬本發明之涵蓋範圍。 綜上所述，利用本發明用於降低導通電阻，提高導通電 流及增加散熱效率，並且節省封裝空間之半導體功率元件 裝置及其封裝方法，不但可大幅縮短硏發時間，降低生產 成本外，更可使半導體功率元件裝置之導通電阻値降低二 分之一，其電流値流經兩並聯路徑耐流可加倍，並且由兩 個導線架構成上、下雙金屬板，利用上層金屬板擴大散熱 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —---------------^ (請先閱讀背面之注意事項再填寫本頁) 503541 A7 _B7_ 五、發明說明（9 ) 的封裝表面，散熱效率可達加乘效果，並可節省封裝空間 ，實爲一新穎、進步且具產業利用性之發明。 元件符號對照表： 1 ...半導體功率元件 10…導線架 11…設接面 12…固定孔 20…導線架 21 ...側壁 22…搭接面 30 ...錫球 40…塑膠鑄模材料503541 A7 B7 V. Description of the invention (1) Field of the invention: The present invention relates to a method and a device for packaging a semiconductor power device for reducing on-resistance, improving on-current and increasing heat dissipation efficiency of a power port, especially a method using two sinks. The pole contacts are respectively fixed to the first and second vertical power elements on the first and second metal lead frames, which are superimposed on each other to form a parallel structure, and the first and second lead frames are overlapped to form a parallel structure. The lower double metal plate uses the upper metal plate to enlarge the heat dissipation packaging surface. BACKGROUND OF THE INVENTION: It is known that semiconductor power element devices, such as power metal-oxide-semiconductor field-effect transistors (MOSSFETs) used in high-speed switching switches, insulated gate bipolar transistors (IGBTs) used in power switching switches, dual-load Sub-junction transistor (B) T, power diode (DIODE), or rectifier (RECTIFIER), etc., traditional single power element device, drain / source (or collector / emitter) on-resistance (ie , RDS-0N) is large, the relative power loss is also large, and accompanied by a large amount of heat, and then affect its product life. Therefore, how to reduce the on-resistance, increase the on-current, increase the heat dissipation efficiency, and improve product characteristics is an issue that high-power semiconductor industry is eager to solve. However, if we start to improve from the traditional circuit design, it will not only increase the complexity of the circuit and structure of the power components, but also have a long development time and a very high cost. Therefore, the inventors have considered the direction of combining substantially two power elements into a parallel structure, and found that not only the manufacturing process is simple with this structure, but also the on-resistance of the semiconductor power element device can be reduced by half and the current値 Flow resistance can be doubled when flowing through two parallel paths, and the paper size of the two guides is applicable to China National Standard (CNS) A4 (210 X 297 mm) < Please read the note on the back first? Please fill in this page again for the items) ▼ Packing --------- Order -------- II line · Printed by the Employee Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Consumption Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 503541 A7 ___B7 V. Description of the invention (2) The wire frame constitutes an upper and lower double metal plate for enlarging the heat dissipation packaging surface. The upper metal plate can double the effect of heat dissipation by external air, and save packaging space. Prior art: Republic of China Invention Patent Bulletin No. 426850, which discloses a "waterfall stacked chip module", which mainly includes: a laminated board having at least a plurality of contacts; a plurality of wafers arranged in the laminated layer On the board, each of the chips includes a plurality of solder pads; a reconfiguration layer configured and electrically connected to the pads; a first insulating layer disposed between the reconfiguration layer and the pads; A plug electrically connects the reconfiguration layer to the solder pad. A plurality of bump contacts are respectively arranged in the first and second regions on the reconfiguration layer, wherein the bump contacts in the first and second regions are configured in a mirror image manner, and every two corresponding bump contacts are It is electrically connected through a reconfiguration layer; wherein the above-mentioned wafers are divided into first and second rows staggeredly stacked, a first region of the first row of wafers, a second region facing the second row of wafers, and a second region of the first row of wafers. Area, the first area facing the second row of wafers, and the bump contacts corresponding to the second area facing the first area are connected by a conductive bump, respectively. In addition, the two flexible chip carriers electrically connect the wafers at the two ends of the two rows of wafers to the contacts of the laminated board, respectively. In addition, the Republic of China Invention Patent Publication No. 423082 discloses a "high-wafer wafer-on-wafer package", which mainly includes: a wafer-on-wafer module, the module is provided with at least two electrically connected to Independent wafers with the same active area, in which the active areas of the two wafers face each other. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) —I --------- --------------- Line · (Please read the note on the back? Matters before filling out this page) 503541 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (3 ); And a chip-on-chip assembly connection device for electrically connecting the chips to an external circuit. Invention 槪 沭: The main purpose of the present invention is to provide a semiconductor power component device for reducing the on-resistance, increasing the on-current and increasing the heat dissipation efficiency, and saving the package volume. The drain contacts are fixed to the first The first and second vertical power elements on the second metal lead frame are overlapped with each other, so that essentially two power elements are combined into a parallel structure; therefore, the on-resistance of the semiconductor power element device 値 (rds. qn) can reduce one-half percent of its current through the two parallel paths to double the current resistance, and it consists of two lead frames to form the upper and lower double metal plates to expand the heat dissipation package surface, and heat is dissipated through the upper metal plate. The heat dissipation efficiency can reach the multiplication effect. Another object of the present invention is to provide a packaging method of a semiconductor power device for reducing on-resistance, improving on-current and increasing heat dissipation efficiency, and saving packaging volume. The steps include: first, firstly and secondly vertical Type power components are symmetrically fixed on the first and second lead frames, and the 'drain contacts are electrically connected to the lead frames respectively; wherein one end of the first lead frame extends with a pin' and includes two separate individual connections. One end of the second lead frame includes a vertically extending side wall and an overlapping surface. Secondly, the gate and source contacts of the first power element are wired with metal wires to be electrically connected to the individual pins respectively; the solder balls are transplanted to the first and second through the solder furnace through the solder ball transfer device. The gate and source contacts of the power component and the overlapping surfaces of the first and second lead frames. Then cover the second lead frame on the first lead frame. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------------- --- Order --------- ^ —Aew— (Please read the notes on the back before filling out this page) 503541 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 1. Description of Invention (4) 'The gate and gate, the source and source contacts of the second power element and the first power element are relatively overlapped. Then, the solder balls are heated and pressurized by the oven to melt the solder balls, so that the first and second power components and the first and second lead frames are relatively welded together. Finally, it is encapsulated with plastic mold material, so that the first and second lead frames form a three-dimensional bare surface on the surface of the semiconductor power component device to expand heat dissipation. Brief description of the drawings = For a further substantial understanding of the above and other objects, features and effects of the present invention, please refer to the embodiments shown in the accompanying drawings as follows. Figure 1 is a perspective view of a semiconductor power element device of the present invention, where ( A) is a top perspective view; (B) is a bottom perspective view; the figure is an exploded perspective view before packaging. Fig. 2 is a side view of an intermediate step of packaging a semiconductor power device device according to the present invention, in which a plastic molding material is indicated by an imaginary line. Figure 3 is a schematic diagram of the packaging steps of a semiconductor power element device of the present invention. Figure 4 is an electronic circuit diagram of a semiconductor power element device of the present invention. FIG. 5 is an equivalent circuit diagram of the semiconductor power element device of the present invention. Fig. 6 is a schematic diagram of another embodiment of a semiconductor power element according to the present invention. Fig. 7 is a schematic diagram of another package type of a semiconductor power element according to the present invention. Paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --------- 1 Packing ------ 丨 Order --------- Line (please first Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 503541 A7 B7___ V. Description of Invention (5) Schematic diagram of the implementation. Detailed description of the invention: First, the semiconductor power devices according to the present invention, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) used for electronic circuit elements, or insulated gate bipolar transistors (I GBT), etc., are described above. The semiconductor power components have a vertical layout, that is, the drain / collector is below, and the source / emitter and gate are above. The power element may also include a diode (DIODE), a rectifier (RECTIFIER), and a bipolar junction transistor (B) T). Hereinafter, the semiconductor power element device and the packaging method thereof for reducing the on-resistance, increasing the on-current and increasing the heat dissipation efficiency, and saving the packaging space will be described with reference to the embodiments of the accompanying drawings. Please refer to FIG. 1 and compare with FIG. 2. The semiconductor power element device 1 of the present invention includes: a first power element Q1 and a second two power element Q2, and gate regions G1 and Q2 of the power elements Qi and Q2. The gate region G2, the source region S1 and the source region S2 are overlapped correspondingly, and individual pins G and S are led out; the drain electrodes D1 and D2 of the power elements Q1 and Q2 are connected respectively. The first metal lead frame 10 and the second two metal lead frames 20. One end of the first lead frame 10 includes a pin D, and the other end extends outwardly with a fixed mounting surface 11 and a fixing hole 12; one end of the second lead frame 2 includes a vertical The extended side wall 21 and the bonding surface 22 are overlapped on the connection surface U of the first lead frame 10, and the other end is provided with a pin D, which is overlapped on the pin D of the first lead frame 10. . In this way, essentially two functional paper sizes apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- · Installation -------- Order- ------- (Please read the notes on the back before filling out this page) 503541 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (6) The rate components Q1 and Q 2 are combined into one A parallel structure, and the first lead frame 10 and the second lead frame 20 are overlapped to form an upper and lower bimetal plate, and the upper surface metal plate is used to enlarge the heat dissipation packaging surface. Please refer to FIG. 3 again. The steps of the above-mentioned packaging method of the semiconductor power element device 1 include the following steps: 'Step one: firstly fix the first power element Q1 and the second power element Q2 symmetrically on the first lead frame 10 and On the second two lead frames 20, the drain contacts Dl 'D2 are electrically connected to the lead frames 10, 20 respectively; one end of the first lead frame 10 extends with a pin D, and includes two separate individual connections. Feet G, S; one end of the second lead frame 20 includes a vertically extending side wall 21 and a bonding surface 22, and the other end has a pin D '. ^ Step 2: Metallize the contact between the gate G1 and the source S1 of the first power component Q1 and connect them to the individual pins G and S respectively. Step 3: Through a solder furnace, solder balls 30 are transplanted to the gate electrodes G1 and G2 of the first and second power components qi and q2 respectively through a solder ball transfer device (not shown in the figure). Point, and the overlapping surfaces D, 22 of the first and second lead frames 10, 20. Step 4: overlay the second lead frame 20 on the first lead frame 10, and make the second power element Q2 and the gate region ^ 2 and the gate region G1 of the first power element qi and the source region S 2 And the source region S 1 are relatively overlapped with each other; and then, the solder ball 30 is melted by heating and pressing in an oven (not shown), so that the first and second power elements Q1 and Q2 and the first and second power elements Q1 and Q2 The two lead frames 10 and 20 are relatively welded together. This paper size is in accordance with China National Standard (CNS) A4 specification (210 X 297 mm) — 1 !! ii · —! — --I I-^ Aw "Please read this page first before filling in this page before filling in this page) 503541 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7____ 5. Description of the invention (7) Step 5: Finally, it is encapsulated by plastic mold material 40, so that the first and second lead frames 10, 20 are in the semiconductor power component device 1 The upper and lower bimetal plates are formed on the surface, and the heat dissipation package surface is enlarged by using the upper metal plate. As described above, the semiconductor power element device and the packaging method thereof of the present invention are substantially welded and combined by the two power elements through a metal welding material. A parallel structure can therefore produce the following effects: (1) When the current flows from the drain terminal D to the source terminal S, it flows through two parallel paths so that the current can withstand: ID can be doubled (as shown in Figure 4). (2) The on-resistance 値 RDS (ON) between the source and the drain becomes smaller, which is about one-half of the original (as shown in Figure 5), that is, the on-resistance dRds 丨 [which is VG 丨 of the two power components] Function, Rds] will f (VG)))] And rds2 [which is a function of VG2 'RDS20f (vc} 2))] shunt resistance 値. (3) The breakdown voltage is unchanged. (4) The volume is not changed after packaging. (5) Diyi and the first lead frame are in The upper and lower bimetal plates are formed on the surface of the semiconductor power element device. The upper metal plate is used to expand the heat dissipation package surface (as shown in Figures 1A and 1B), and the heat dissipation efficiency can be multiplied. In addition, as shown in Figure 6 As shown, in response to the miniaturization of semiconductor power device devices, the space actually applicable in the microfabrication process is extremely limited. In order to avoid that the metal wire connected to the gate G1 and the pin G crosses the source s1 region during wiring, it is easy to cause Short circuit defect rate, so the arrangement of power components q 1, Q2 can set the gate G 1 area in the same direction as the pin G and relative to the shortest distance. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm)------- I ----------- ^ --------- ^ (Please read the notes on the back before filling this page) 503541 Economy Printed by the Intellectual Property Bureau Employee Consumer Cooperative A7 B7 V. Description of Invention (8) Figure 7 shows the semiconductor of the invention Rate component device 丨 Another package type 'This embodiment is different in that the surface of the second lead frame 20 (the upper metal plate) is insulated with a plastic molding material 40 during packaging to prevent the upper metal plate from being touched by mistake. In addition, the surface can be used to indicate the type, etc. In addition, as shown in FIG. 8, the present invention can be similarly implemented in the package type of the semiconductor power element device 1 in a planar layout. The structure and packaging method of this embodiment are as described above. The embodiment is not repeated here. The difference in this embodiment is that the contacts of the gate G1, the drain D1, and the source S1 of the first power element Q1 on the first lead frame 10 are respectively covered with metal wires. Is electrically connected to the individual pins G'D, S; the gate G2, the drain D2 and the source S2 of the second power element Q2 on the second lead frame 20 are connected to the first wire correspondingly The gate G1, the drain D1 and the source S1 of the first power element Q1 on the rack 10 are connected to each other. In this way, the objects and effects of the present invention can be achieved in the same way. The above is only a preferred embodiment of the present invention, and does not limit the package type of the present invention and its implementation scope, that is, equivalent changes and modifications made without departing from the scope of the patent application for the present invention should still fall within the scope of the present invention. In summary, the semiconductor power element device and its packaging method for reducing the on-resistance, improving the on-current and increasing the heat dissipation efficiency and saving the packaging space by using the present invention can not only shorten the bursting time, reduce the production cost, but also It can reduce the on-resistance 半导体 of the semiconductor power element device by half, its current 値 flowing through the two parallel paths can be doubled, and the upper and lower double metal plates are composed of two lead frames. The upper metal plate is used to expand heat dissipation- 10- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) —--------------- ^ (Please read the precautions on the back before filling this page ) 503541 A7 _B7_ V. The package surface of the invention description (9), the heat dissipation efficiency can be multiplied, and the packaging space can be saved. It is a novel, progressive and industrially usable invention. Component symbol comparison table: 1 ... semiconductor power component 10 ... lead frame 11 ... set surface 12 ... fixing hole 20 ... lead frame 21 ... side wall 22 ... lap surface 30 ... tin ball 40 ... plastic mold material
Ql，Q2 ...功率元件Ql, Q2 ... power components
Dl，D2…汲極 D，D，…接腳Dl, D2 ... Drain D, D, ...
Gl，G2…閘極 SI，S2…源極 G，S ...接腳 I----------裝--------訂—-------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Gl, G2 ... gate SI, S2 ... source G, S ... pin I ---------- install -------- order --------- line (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -11- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)