TW504816B - Semiconductor device and the packaging method without bonding wire - Google Patents

Semiconductor device and the packaging method without bonding wire Download PDF

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Publication number
TW504816B
TW504816B TW090128579A TW90128579A TW504816B TW 504816 B TW504816 B TW 504816B TW 090128579 A TW090128579 A TW 090128579A TW 90128579 A TW90128579 A TW 90128579A TW 504816 B TW504816 B TW 504816B
Authority
TW
Taiwan
Prior art keywords
lead frame
semiconductor device
connection
contact
semiconductor wafer
Prior art date
Application number
TW090128579A
Other languages
Chinese (zh)
Inventor
Jeng-Huei Dung
You-Ren Li
Gau-Wei Tu
Feng-Tzuo Jian
Original Assignee
Chino Excel Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chino Excel Technology Corp filed Critical Chino Excel Technology Corp
Priority to TW090128579A priority Critical patent/TW504816B/en
Application granted granted Critical
Publication of TW504816B publication Critical patent/TW504816B/en
Priority to US10/298,978 priority patent/US20030094678A1/en
Priority to US10/892,582 priority patent/US20040256703A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Wire Bonding (AREA)

Abstract

A semiconductor device without bonding wire is disclosed, which comprises a lead frame with one end having an expanded connection surface, the other expanding to form a stacked layer opposed to the connection surface, and a pin terminal extended from it; and a semiconductor chip adhered to the connection surface of the lead frame. The bottom surface of the chip has at least a contact electrically connected to the lead frame. The surface of the chip comprises at least a contact with individual pin terminal extended there from. There is no metal bonding wire connecting the surface contact of semiconductor chip and the individual pin terminal. The substrate of the stacked layer is extended for a predetermined length to be pressed into the individual pin terminal which is directly bonded to the surface contact of the semiconductor chip. The packaging method of said semiconductor chip comprises: compressing the metal substrate to have an extended surface, an integrated pin terminal extended with a predetermined length, and a lead frame with plural individual pin terminals; fixing the semiconductor chip on the connection surface of the lead frame, so that the contact of bottom surface is electrically connected to the lead frame, and coating a layer of insulation adhesive on the surface; mounting the solder ball on the surface contact of the semiconductor chip in the rotary soldering furnace, and then folding and overlapping one end of the extended surface toward the connection surface, so that plural individual pins are connected to the surface contact of the semiconductor chip respectively; and baking by oven to melt the solder ball and electrically connect the same to the individual pin terminal.

Description

504816 五、 發明說明 ( 1 ) 發 明 領 域 : 本 發 明 係 關 於 無焊線 式 半 導 體 裝置 及 其 封 裝 方 法 ( _- ) 尤 指 一 種 半 導 體裝置 之 製 程 中 免焊金 屬 線 ， 而 藉 由 引 線 架 延 展 之 叠 層 基 材，以 預 定 長 度 延伸 軋 壓 成 個 別 接 腳 端 子 而 直 接 焊 接 在 半導體 晶 片 表 面 之接 點 上 〇 發 明 背 景 : 查 > 習 知 半 導 體裝置 ， 諸 如 TO封 裝 之功 金 氧 半 場 效 電 晶 體 ( Powe r M0SFET) 絕 緣 閘極 雙 極 性 電 晶 體 ( IGBT ) 雙 載子接ΐ S電晶 體 ( BJT )、 功 率 二 極 丨體< 〔Power Di od e ) 或整流器（Rec t i f i e r )等 之 高 電 流 功 率 電 晶 體 ， 在 傳 統 製 程 中 ，晶片 接 點 與 接 腳端 子 間 皆 需 要 經 由 焊 接 金 屬 線 而 電 連 接 之。由 於此 細 微 加工 m 程 造 成 導 通 電 流 較 易 侷 限 在焊 接 點 附近， 而 使 封 裝 後之 元 件 可 靠 度 較 差 並 且 金 屬 線 之 截 面 極細小 金 屬 線 本身之 電 阻 値 大 > 因 此 汲 極 /源極 (或集極/射極 !) 之導通電阻（ :即， RDS- ON ) 變 大 致 導 通 電 流 小 。故傳 統 半 導 體 裝置 功 率 損 耗 大 且 伴 隨 產 生 較 大 熱 量 j 進而影 響 其 產 品使用 壽 命 f 故而 如何 降 低 導 通 電 阻 以 增加導 通 電 流 > 提昇 產 品 特性 > 爲 高 功 半 導 體 業 者 所 急 欲解決之 Ξ田 m 題 〇 因此 ， 發 明 人 等 朝 向 利 用 引 線 架 延 展 之 疊 層基材 ， 以 預 定 長度 延伸軋 壓 成 個 別 接 腳 丄山 贿 子 而 直 接 焊 接在半 導 am 體 晶 片 表面 接 點 上 之 方 向 思 考 發 現以 此 方 式 不但可免 除 金 屬 焊 線， 並 且 可 降 低 導 通 電 阻 j 提 高 導 通 電 流 外，更 減 少 其 3. 發 熱量 同 時 使 製 程 單 純 化 504816 五、發明說明（2) 並fee向良率及降低封裝成本’遽爾完成本發明。 兔前技術： 中華民國發明專利公告第40403 1號，揭示一種「連接 半導體晶片至引線框架之系統與方法及引線框架之接合支 撐裝置」，系統主要包括： 一立體引線框架，其包含：一第一引線，具有第一基座 J份’弟一引線尖端’及第一徑向軸線；一第二引線，具 有第二基座部份，第二引線尖端，及第二徑向軸線；第一 及第二引線形成爲實際彼此相鄰，並且第二引線有一階梯 形部份’致使第一及第二引線之引線尖端在Z -方向及在 γ-方向分開（其中Y-方向平行於引線之徑向軸線及X-方 向與相鄰引線相交）。及，一接合支撐裝置，供接合時固 持上述立體引線框架，該支撐裝置包含：一支撐體，形成 有一槽，該槽具有第一表面在第一高度，第一表面供支撐 第二引線尖端；一第二表面在支撐體上形成第二高度，並 實際靠近第一表面，第二表面供支撐第一引線尖端；其中 ’桌_1局度及第一局度彼此移位。 從上述專利範圍及圖式中顯示，第一引線尖端較第二引 線尖端具有突伸部分，唯該設計爲因應晶片單位面積內能 夠容納更多的引線，因此第一引線與第二引線在水平方向 、及垂直方向彼此移位錯開，並且該引線與晶片接點間需 藉由焊金屬線連接。 發明槪述= 504816 五、 發明說明 ( 3 : ) 本 發 明 之 主 要 巨 的 在 於 提 供 一 種 Μ /\\\ 焊 線 式 半 導 體 裝 置 根 據 本 發 明 裝 置 ， 係利 用 較 大 表 面 積 的 接 腳 丄山 贿 子 延 伸 之 基 材 5 取代 半 導 體 晶 片 與 接 腳 上UU m 子 間 的 橋 接 金 屬 線 因 此 可 在 兩 者 間 形成加 大 的 接 著 面 > 如 此 不 僅 可 免 除 金 屬 焊 線 更 可 降 低 導 通 電 阻 提 高 導 通 電 流 減 少 發 熱 里 〇 爲 了 達 成 上 述 巨 的 及 其 他 巨 的 本 發 明 裝 置 主 要 包括有 —* 具 有 擴 大 設 接 面 的 引 線 架 該 引 線 架 之 基 材相 對 於此 設 接 面延 展 形 成有 —* 疊 層 並 以 預 定 長 度 延伸形成有 —* 一 體 的 接 腳 上M t 贿 子 及分 離 的 個 別 接 腳 端 子 一 半 導 體 晶 片 ， 附 著 在 引 線 架 的 設 接 面 上 底 面 接 點 與 引 線 架成 電 氣 性 連 接 > 該 晶 片 表 面包含 至 少 — 接 點 上 述 個 別 接 腳 丄山 m 子係 直 接 焊 接 在半 導 體 晶 片 表 面 接 點 上 〇 本 發 明 之 另 一 巨 的 在於 提 供 一 種 Μ y\s\ 焊 線 式半 導 體 裝 置 之 封 裝 方法 〇 根 據 本 發 明 方法包含下 列: 步! 驟 ： 先 將 金 屬 基 材軋 壓 出 具 有延 展 面 ， 及 預 定 長 度 延 伸 之 —* 體 接 腳 端 子 與 個 別 接 腳 端 子 的 導 線 架 9 再 將 半 導 體 晶 片 附 著 在 導 線 架 的 設 接 面 上 ， 使 底 面 接 點 與 導 線 架 成 電 氣 性 連 接 並 在 表 面 塗 佈 —* 層 絕 緣 膠 然 後 過 錫 爐 將 錫 球 移 植 在 半 導 體 晶 片 之 表 面 接 點 上 t 再 將 延 展 面 之 一 丄山 贿 朝 向 設 接 面 上 摺 壓 疊 覆 ， 使 個 別 接 腳 端 子分別 覆 接 在半 導 體 晶 片 之 表 面 接 點 上 y 再 通 過 烤 箱 使 錫 球 熔 融 而 與 個 別 接 腳 丄山 * 子 成 電 氣 性 連 接 t 最 後 ， 經 陶 瓷 或 塑 膠 鑄 模 材料封 裝 〇 上 述 之 製 程 中 ， 由 於可 省 略焊 金 屬 線 -5· ’ 因 此 可使 製 程 單 純 化 及 提 504816 五、 發明說明（4) 高 良 率’進而降低封裝成本。 圖 式 簡單說明： 對 於本發明上述目的及其他目的，特點及功效進一 步 的 實 質 瞭解，謹配合附圖所示實施例說明如下： 第 1圖爲本發明無線式半導體裝置構成之立體示意 圖 其 中 模鑄材料以假想線表示。 第 2圖爲本發明無線式半導體裝置的封裝步驟之立 體 示 niasi >琶、 圖 〇 第 3圖爲本發明無線式半導體裝置封裝之中間步驟 側 視 示 意 圖。 第 4圖爲本發明無線式半導體裝置完成封裝步驟之 側 視 示 =sin 圖，其中模鑄材料以假想線表示。 發 明 之詳細說明： 首 先說明，本發明所涉及之半導體裝置，諸如使用 於 電 子 電 路元件TO封裝之功率金氧半場效電晶體（powei· M0SFET )，或者絕緣閘極雙極性電晶體（IGBT )等之 局 電 流 功 率電晶體，上述之半導體裝置爲垂直式佈局，即 汲 極 ( Di •ain) /或集極（Collector)在下面，而源 極 ( So u r ce) /或射極（Emitter)及閘極（Gate) /基 極 ( Ba s e )在上面的佈局方式，其中該功率元件亦可包含功 率 二 極 體（Power Diode)、整流器（Rectifier)、及 雙 載 子 接 面電晶體（BJT)等。以下將配合附圖實施例說 明 本 發 明 應用於無焊線式半導體裝置及其封裝方法。 -6- 504816 五、 發明說明 ( 5) S主 m 參 考第 1 圖，本發明無焊線式半導體裝置1，其 基 本 構 社 具 備如 同 習知構造，包括一引線架2，其一端形成有 一 擴 大 的設 接 面20，並引出有一接腳端子23; —半 導 體 晶片 3 ，附; 著: 在引線架的設接面20上，底面至少有一 接 點 ( 如汲 極D ) ，與引線架2成電氣性連接，該半導體 晶 片 3 表 面包含 至 少一接點（如閘極G、源極S等），並 引 出 有 個 別 接腳 端 子 24 ， 25 。 本 發 明不 同 之處在於，引線架2另一端之基材向外 展 延 相 對 於擴 大 的設接面20形成有一疊層21，該疊層： 21 與 設 接 面 20 間 有一端連接著，並且於連接端界面之內 側 軋 壓 有 小於壁 厚 的凹槽22;該疊層21並以一預定長度 延伸 ， 軋 壓 有一 體 pisz. 之接腳端子23及個別之接腳端子24, 25 9 上 述 半 導體 晶 片3表面接點（閘極G/源極S)與個別 接 腳 端 子 24，25 間之連接並無金屬焊線，而直接將該個 別 接 腳 端 子 24， 2 5焊接在半導體晶片3表面接點（閘極 G/ 源 極 S ) 上。 如此，半導體晶片3表面接點（閘極G /源 極 S ) 與 個 別接 腳 端子24，25間，可免除焊金屬線，且 兩 者 間 之 附 著面 積 變大，及有增大體積之接腳端子，因此 可 降 低 導 通 電阻 > 增加導通電流及更減少發熱量。 以 下 謹參 考 第2圖並對照第3及4圖，說明上述本 發 明 Μ /\\\ 焊 線 式半 導 體裝置1之封裝方法，其包括下列步驟 : 步 驟 _.: 首先將導電性金屬基材軋壓出引線架雛型 2, > 該 引 線 架雛 型 2’一端包含有一擴大的設接面20，另 -7- 端 504816 五、發明說明（6) 延伸有一展開面2 Γ，及在兩者界面之間，軋壓至少有一 道凹槽22,較佳爲連續乳壓兩道三角形凹槽22;該展開 面21’外側端伸設有一接腳端子23,及在此接腳端子23 兩側經由支撐片26連接有複數分離的個別接腳端子24， 25，而該複數分離的個別接腳端子24，25之內側端朝內 側方向延伸有一預定長度。 步驟二：將上述引線架雛型2’軋壓成立體引線架2，使 接腳端子23，24，25與展開面21’及設接面20間，形成 有一非在相同平面上之高低落差，該高度落差約略大於半 導體晶片3之厚度。 步驟三··將半導體晶片3附著在引線架2的擴大設接面 20上，底面至少有一極接點（汲極D )與引線架2成電氣 性連接，及在半導體晶片3表面塗佈一層絕緣膠。 步驟四：通過錫爐，經錫球移載裝置（爲習知設備在圖 中未示）將錫球4移植在半導體晶片3表面之接點（閘極 G /源極S )上。 步驟五：將引線架2展開面21’之一端，朝向設接面2〇 之一端壓摺疊覆形成一密接的疊層21，並使分離的複數個 別接腳端子24，25分別覆接在半導體晶片3表面接點（ 閘極G /源極S)上，再通過烤箱加熱並加壓，使錫球4熔 融而與個別接腳端子24，25成電氣性連接，並裁斷支撐 片26使成分離的腳位。 步驟六：最後，經陶瓷、或塑膠鑄模材料5封裝。 504816 五、發明說明（7) 如上 述，本發明無 焊線式半導體裝置之封裝 方 法， 由 於 製程中 可省略焊金屬 線，因此可使製程單純化 及 提高 良 率 ，進而 降低封裝成本 〇 以上 ，僅爲本發明 的較佳實施例，並不侷限 本 發明 的 封 裝型式及其實施範圍 ，可以理解的是，上述封 裝 方法 不 僅 適用於 三支腳位的半 導體裝置，對於兩支腳位 的 半導 體 裝 置，例 |如功率二極 體（Power Diode)、或整流 器 ( Rectifier)等同樣適用；即，不偏離本發明 串 請專 利 範 圍所作之均等變化與 修飾，應仍屬本發明之涵: mi _ 〇 綜上 所述，利用本 發明無焊線式半導體裝置 及 其封 裝 方 法（二 )，可大大地 降低導通電阻，因而增加 導 通遺 流 外 ，及減 少發熱量；並 且，製程中可省略焊金屬 線 ，故可使 製程單 純化及提局良 率，進而降低封裝成本， 實 爲一 新 穎 、進步 且具產業利用 性之發明。 元件符 號對照表= 1… 本發明無焊線式半導體裝置 2 ... 引線架 2’…引線架雛型 20 .. .設接面 21 .· .疊層 21 ’…展開面 22 .. .凹槽 23 .. ，.接腳端子 24， 25 ...個別接 腳端子 26 .. .支撐片 冬 504816 五、發明說明（8) 3 .. .半導體晶片 4 ·· .錫球 5 ·· .鑄模材料 D ·· .汲極 G ·· .閘極 S ·· .源極504816 V. Description of the invention (1) Field of the invention: The present invention relates to a wireless semiconductor device and a method for packaging the same (_-), especially a solderless metal wire in the manufacturing process of a semiconductor device, and the stack is extended by a lead frame. Layer substrate, which is rolled and rolled into individual pin terminals with a predetermined length and directly soldered to the contacts on the surface of the semiconductor wafer. BACKGROUND OF THE INVENTION: A conventional semiconductor device, such as a TO-packaged metal-oxide-semiconductor field-effect transistor ( Powe r M0SFET) Insulated Gate Bipolar Transistor (IGBT) Double Carrier S-Transistor (BJT), Power Diodes < 〔Power Di od e) or Rectifier (Rec tifier) etc. In the traditional manufacturing process of transistors, the chip contacts and the pin terminals need to be electrically connected by soldering metal wires. Due to this micro-machining process, the on-current is easily confined near the solder joint, which makes the packaged components less reliable and the cross section of the metal wire is very small. The resistance of the metal wire itself is large> therefore the drain / source (or The on-resistance (: RDS-ON) of the collector / emitter! Therefore, the traditional semiconductor device has a large power loss and generates a large amount of heat j, which will affect its product life f. Therefore, how to reduce the on-resistance to increase the on-current > improve product characteristics > Question 〇 Therefore, the inventors and others are thinking about the direction of the laminated substrate using the lead frame to stretch and roll it into individual pins by a predetermined length and directly soldering it to the contacts on the surface of the semiconductor wafer. This method not only eliminates the metal bonding wire, but also reduces the on-resistance j and increases the on-current. It also reduces the amount of heat. 3. Simultaneously, the process is simplified. 504816 V. Description of the invention (2) The yield rate is reduced and the packaging cost is reduced. Müller completed the present invention. Pre-rabbit technology: Republic of China Invention Patent Bulletin No. 40403 1 discloses a "system and method for connecting a semiconductor wafer to a lead frame and a bonding support device for the lead frame". The system mainly includes: a three-dimensional lead frame, including: a first A lead having a first base J's lead tip and a first radial axis; a second lead having a second base portion, a second lead tip, and a second radial axis; a first And the second lead are formed to be practically adjacent to each other, and the second lead has a stepped portion, so that the lead tips of the first and second leads are separated in the Z-direction and in the γ-direction (where the Y-direction is parallel to the lead Radial axis and X-direction intersect adjacent leads). And, a bonding support device for holding the three-dimensional lead frame during bonding, the support device includes: a support body formed with a groove having a first surface at a first height and the first surface for supporting a second lead tip; A second surface forms a second height on the support body, and is actually close to the first surface, and the second surface is used to support the first lead tip; wherein the 'table_1 inclination' and the first inclination are shifted from each other. From the above patent scope and drawings, it is shown that the first lead tip has a protruding portion than the second lead tip, but the design should be able to accommodate more leads per unit area of the wafer, so the first lead and the second lead are horizontal. The direction and the vertical direction are shifted from each other, and the lead and the chip contact need to be connected by a solder wire. Description of the invention = 504816 V. Description of the invention (3:) The main advantage of the present invention is to provide a M / \ wire-bond semiconductor device. According to the device of the present invention, it is extended by using a large surface area. Substrate 5 replaces the bridge metal wire between the semiconductor chip and the UU m sub-pin on the pin, so an enlarged bonding surface can be formed between them.> This not only eliminates the metal bonding wire, but also reduces the on-resistance, increases the on-current and reduces heat generation. In order to achieve the above-mentioned giant and other giants, the device of the present invention mainly includes-* a lead frame with an enlarged connection surface, and the base material of the lead frame is extended with respect to this connection surface to form-* a stack and a predetermined length Extending the formation of-* integrated pins on Mt bridging and separate individual pin terminals-a semiconductor wafer, attached to the bottom surface contacts and leads of the mounting surface of the lead frame The wire frame is electrically connected. The surface of the wafer contains at least-the above-mentioned individual pins. The 丄 shan m sub-system is directly soldered to the surface of the semiconductor wafer. Another major aspect of the present invention is to provide a M y \ s \ Method for packaging wire-bond semiconductor devices. The method according to the present invention includes the following steps: Steps: Steps: First, a metal substrate is rolled out to have an extended surface and a predetermined length of extension— * a lead of a body pin terminal and an individual pin terminal The rack 9 then attaches the semiconductor wafer to the connection surface of the lead frame, so that the bottom contact is electrically connected to the lead frame and coated on the surface— * layer of insulating glue, and then the solder ball is transplanted on the surface of the semiconductor wafer through a tin furnace. On the surface contact point, one of the extended surfaces is folded and folded toward the connection surface, so that the individual pin terminals are respectively covered on the surface contact points of the semiconductor wafer. Then, the solder ball is melted in the oven to be electrically connected to the individual pins. * Finally, it is encapsulated by ceramic or plastic mold material. In the above process, the soldering wire can be omitted-so the process can be made. Simplification and extraction 504816 V. Description of the invention (4) High yields to reduce packaging costs. Brief description of the drawings: For a further substantial understanding of the above and other objects, features, and effects of the present invention, please refer to the embodiments shown in the accompanying drawings as follows: FIG. 1 is a three-dimensional schematic diagram of a wireless semiconductor device according to the present invention, in which the mold is cast The material is represented by imaginary lines. Fig. 2 is a perspective view showing the steps of packaging a wireless semiconductor device according to the present invention. Niasi > Pa. Fig. 3 is a schematic side view of the intermediate steps of packaging a wireless semiconductor device according to the present invention. Fig. 4 is a side view of a wireless semiconductor device in accordance with the present invention when the packaging step is completed; Detailed description of the invention: First of all, the semiconductor devices involved in the present invention, such as power metal-oxide-semiconductor field-effect transistors (powei · MOSFET) used for electronic circuit element TO packages, or insulated gate bipolar transistors (IGBT), etc. For a local current power transistor, the above-mentioned semiconductor device has a vertical layout, that is, a di / ain / collector is below, and a source / emitter and / or an emitter and Gate / Base layout on the top, where the power element can also include Power Diode, Rectifier, and BJT Wait. Hereinafter, the present invention will be described with reference to the embodiments of the accompanying drawings. The present invention is applied to a wireless semiconductor device and a packaging method thereof. -6- 504816 V. Description of the invention (5) Referring to the first figure, the wireless semiconductor device 1 of the present invention has a basic structure with a conventional structure, including a lead frame 2, and one end is formed with an enlargement. The connection surface 20 is provided, and a pin terminal 23 is drawn out;-the semiconductor wafer 3 is attached; at least: on the connection surface 20 of the lead frame, the bottom surface has at least one contact (such as the drain electrode D), which is equal to the lead frame 2 Electrically connected, the surface of the semiconductor wafer 3 includes at least one contact (such as a gate G, a source S, etc.), and individual pin terminals 24, 25 are led out. The present invention is different in that the base material at the other end of the lead frame 2 extends outward with respect to the enlarged connection surface 20 to form a stack 21, and the stack: 21 is connected to the connection surface 20 at one end, and A groove 22 with a thickness smaller than the wall thickness is rolled on the inner side of the connection end interface; the laminate 21 is extended with a predetermined length, and the pin terminal 23 and the individual pin terminals 24, 25 9 are integrally rolled. The connection between the surface contact (gate G / source S) of the semiconductor wafer 3 and the individual pin terminals 24, 25 has no metal bonding wire, and the individual pin terminals 24, 25 are directly soldered to the semiconductor wafer 3 table. Surface contact (gate G / source S). In this way, the surface contacts (gate G / source S) of the semiconductor wafer 3 and the individual pin terminals 24 and 25 can be eliminated, and the bonding area between the two becomes larger, and the connection with an increased volume Pin terminals, which can reduce on-resistance > increase on-current and reduce heat generation. Hereinafter, referring to FIG. 2 and comparing FIGS. 3 and 4, the above-mentioned packaging method of the M / \\ wire-bond semiconductor device 1 of the present invention will be described, which includes the following steps: Step _ .: First, a conductive metal substrate is rolled. Press out the lead frame prototype 2, > One end of the lead frame prototype 2 'includes an enlarged connecting surface 20, and the other -7- end 504816 V. Description of the invention (6) A spreading surface 2 Γ is extended, and Between the interfaces, at least one groove 22 is rolled, preferably two triangular grooves 22 in continuous milking; a pin terminal 23 is protruded from the outer end of the unfolding surface 21 ', and the pin terminal 23 two A plurality of separated individual pin terminals 24, 25 are connected to the side via the supporting piece 26, and the inner ends of the plurality of separated individual pin terminals 24, 25 extend a predetermined length toward the inside direction. Step 2: The above-mentioned lead frame prototype 2 'is rolled into a body lead frame 2 so that the height difference between the pin terminals 23, 24, 25 and the development surface 21' and the connection surface 20 is not on the same plane. The height difference is approximately larger than the thickness of the semiconductor wafer 3. Step Three ... Attach the semiconductor wafer 3 to the enlarged connection surface 20 of the lead frame 2. At least one pole contact (drain D) on the bottom surface is electrically connected to the lead frame 2, and a layer is coated on the surface of the semiconductor wafer 3. Insulating glue. Step 4: The solder ball 4 is transplanted to a contact (gate G / source S) on the surface of the semiconductor wafer 3 through a solder furnace through a solder ball transfer device (not shown in the figure for conventional equipment). Step 5: One end of the unfolded surface 21 'of the lead frame 2 is pressed and folded toward one end of the set contact surface 20 to form a tightly laminated stack 21, and the separated plural individual pin terminals 24 and 25 are respectively covered on the semiconductor. At the surface contact (gate G / source S) of the chip 3, it is heated and pressurized by the oven to melt the solder ball 4 and electrically connect with the individual pin terminals 24 and 25, and cut the support piece 26 to make Separated feet. Step 6: Finally, it is sealed with ceramic or plastic mold material 5. 504816 V. Description of the invention (7) As mentioned above, since the bonding method of the wireless semiconductor device of the present invention can be omitted in the manufacturing process, the manufacturing process can be simplified and the yield can be improved, thereby reducing the packaging cost by more than 0. It is only a preferred embodiment of the present invention, and does not limit the package type and implementation scope of the present invention. It can be understood that the above packaging method is not only applicable to a three-pin semiconductor device, but also to a two-pin semiconductor device. , For example | Power Diode, Rectifier, etc. are also applicable; that is, equivalent changes and modifications made without departing from the scope of the patents of the present invention should still be included in the present invention: mi _ 〇 In summary, the use of the wireless semiconductor device of the present invention and its packaging method (2) can greatly reduce the on-resistance, thereby increasing the conduction leakage current and reducing the amount of heat generation; and, the welding wire can be omitted in the manufacturing process. , So that the process can be purified and the yield can be improved, thereby reducing packaging costs, It is a new, progressive and industrially usable invention. Component symbol comparison table = 1 ... The wire-less semiconductor device 2 of the present invention 2 ... lead frame 2 '... lead frame prototype 20 ......... Grooves 23..., Pin terminals 24, 25 ... individual pin terminals 26... Support sheet winter 504816 5. Description of the invention (8) 3... Semiconductor wafer 4 ··. Solder ball 5 ·· .Molding material D ·· .Drain electrode G ·· .Gate S ·· .Source

-10--10-

Claims (1)

504816 六、申請專利範圍 i.一種無焊線式半導體裝置，包括一引線架，其一端形成 有一擴大的設接面，並引出有一接腳端子；一半導體晶 片，附著在引線架的設接面上，底面至少有一接點與引 線架成電氣性連接，該半導體晶片表面包含至少一接點 ，並引出有個別接腳端子；其特徵在於： 該半導體晶片表面接點與個別接腳端子間之連接，並 無金屬焊線；該連接係由引線架延展之基材相對於設接 面形成有一疊層，該疊層並以預定長度延伸軋壓成一體 之接腳端子及個別之接腳端子，並直接將該個別接腳端 子焊接在半導體晶片表面至少一接點上。 2 .如申請專利範圍第1項之無焊線式半導體裝置，其中引 線架之設接面與疊層間至少有一端連接著。 3 .如申請專利範圍第2項之無焊線式半導體裝置，其中引 線架設接面與疊層連接端界面之內側軋壓有小於壁厚的 凹槽。 4 .如申請專利範圍第1項之無焊線式半導體裝置，其中半 導體裝置包括··功率二極體（ Power Diode)，整流器 (Rectifier)，垂直式及平面式功率金氧半場效電晶 體（Power M0SFET)，雙載子接面電晶體（BJT)以及 絕緣閘極雙極性電晶體（IGBT)等。 5. —種無焊線式半導體裝置之封裝方法，其方法包括下列 步驟： 首先將導電性金屬基材軋壓出引線架雛型，該引線架 -11- 504816 六、申請專利範圍 雛型一端包含有一擴大的設接面，另一端延伸有一展開 面，及在兩者界面之間，軋壓至少有一道凹槽；該展開 面外側端伸設有一接腳端子，及在此接腳端子一側/或 兩側各經由支撐片連接一支/或兩支分離的個別接腳端 子，而該一支/或兩支分離的個別接腳端子之內側端朝 內側方向延伸有一預定長度； 將上述引線架雛型軋壓成立體引線架，使接腳端子與 展開面及設接面間，形成有一高低落差，非在相同平面 上； 將半導體晶片附著在引線架的擴大設接面上，底面至 少有一極接點與引線架成電氣性連接，及在半導體晶片 表面塗佈絕緣膠； 通過錫爐，經錫球移載裝置將錫球移植在半導體晶片 表面之另一極/或二極之接點上； 將引線架展開面之一端，朝向設接面之一端摺壓疊覆 ，並使一支/或兩支分離的個別接腳端子分別覆接在半 導體晶片表面之一極/或二極接點上，再通過烤箱加熱 並加壓，使錫球熔融而與個別接腳端子成電氣性連接， 並裁斷支撐片； 最後，經陶瓷、或塑膠鑄模材料封裝。 6 .如申請專利範圍第：項之無焊線式半導體裝置之封裝方 法，其中引線架設接面與展開面之界面間，較佳爲連續 軋壓兩道三角形凹槽。 -12- 504816 六、申請專利範圍 7 .如申請專利範圍第6項之無焊線式半導體裝置之封裝方 法，其中半導體裝置包括：功率二極體（Power Diode )，整流器（Rectifier)，垂直式及平面式功率金氧 半場效電晶體（Power M0SFET)，雙載子接面電晶體（ BJT)以及絕緣閘極雙極性電晶體（IGBT)等。 1504816 6. Scope of patent application i. A wireless semiconductor device includes a lead frame, one end of which is formed with an enlarged connection surface and leads out a pin terminal; a semiconductor wafer attached to the connection surface of the lead frame On the bottom surface, at least one contact point is electrically connected to the lead frame. The surface of the semiconductor wafer includes at least one contact point and leads to individual pin terminals. It is characterized in that: between the surface contacts of the semiconductor wafer and the individual pin terminals, The connection is made without a metal bonding wire; the connection is formed by a lead frame extending from the base material with respect to the connection surface, and the stack is extended and rolled into a unified pin terminal and individual pin terminals with a predetermined length. And directly solder the individual pin terminal to at least one contact on the surface of the semiconductor wafer. 2. The wireless semiconductor device according to item 1 of the scope of patent application, wherein at least one end is connected between the connection surface of the lead frame and the stack. 3. The wireless semiconductor device according to item 2 of the scope of the patent application, wherein the inner side of the lead-frame connection interface and the laminated connection end interface is rolled with a groove smaller than the wall thickness. 4. The wireless semiconductor device according to item 1 of the scope of the patent application, wherein the semiconductor device includes a power diode, a rectifier, a vertical and planar power metal-oxide half field effect transistor ( Power M0SFET), bipolar junction transistor (BJT) and insulated gate bipolar transistor (IGBT). 5. —A method for packaging a wireless semiconductor device, the method includes the following steps: First, a conductive metal substrate is rolled out of the lead frame prototype, the lead frame-11-504816 It includes an enlarged setting surface, the other end is extended with a development surface, and at least one groove is rolled between the two interfaces; the outer end of the development surface is provided with a pin terminal, and the pin terminal is One or two separate individual pin terminals are connected on one side or both sides via a support sheet, and the inner end of the one or two separate individual pin terminals extends a predetermined length toward the inner side; The prototype of the lead frame is rolled into a body lead frame, so that there is a height difference between the pin terminals and the developed surface and the connection surface, not on the same plane; the semiconductor wafer is attached to the enlarged connection surface of the lead frame, the bottom surface At least one pole contact is electrically connected to the lead frame, and an insulating glue is coated on the surface of the semiconductor wafer; the solder ball is transplanted to another surface of the semiconductor wafer through a solder furnace through a solder ball transfer device. On one or both ends of the lead frame, and fold and overlap one end of the lead frame toward one end of the set contact surface, and one or two separate individual pin terminals are respectively covered on the surface of the semiconductor wafer The one-pole or two-pole contacts are heated and pressurized by an oven to melt the solder balls to electrically connect with the individual pin terminals and cut the support sheet. Finally, they are encapsulated by ceramic or plastic mold materials. 6. The method for packaging a wireless semiconductor device according to the scope of the patent application, wherein the interface between the lead-frame connection surface and the unrolling surface is preferably continuous rolling of two triangular grooves. -12- 504816 6. Application for patent scope 7. For the packaging method of wireless semiconductor device such as item 6 of the patent application scope, the semiconductor device includes: Power Diode, Rectifier, Vertical And planar power metal-oxide-semiconductor field-effect transistor (Power M0SFET), bipolar junction transistor (BJT) and insulated gate bipolar transistor (IGBT). 1
TW090128579A 2001-11-19 2001-11-19 Semiconductor device and the packaging method without bonding wire TW504816B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW090128579A TW504816B (en) 2001-11-19 2001-11-19 Semiconductor device and the packaging method without bonding wire
US10/298,978 US20030094678A1 (en) 2001-11-19 2002-11-18 Wireless bonded semiconductor device and method for packaging the same
US10/892,582 US20040256703A1 (en) 2001-11-19 2004-07-15 Wireless bonded semiconductor device and method for packaging the same

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000604A (en) * 2012-11-19 2013-03-27 无锡九条龙汽车设备有限公司 Improved frame plating structure of three-terminal regulator
CN103182598A (en) * 2011-12-28 2013-07-03 贵州雅光电子科技股份有限公司 High-power automobile rectifier bridge soldering method and lug thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103182598A (en) * 2011-12-28 2013-07-03 贵州雅光电子科技股份有限公司 High-power automobile rectifier bridge soldering method and lug thereof
CN103182598B (en) * 2011-12-28 2016-05-04 贵州雅光电子科技股份有限公司 A kind of welding method of high-power automobile-used rectifier bridge and lug plate thereof
CN103000604A (en) * 2012-11-19 2013-03-27 无锡九条龙汽车设备有限公司 Improved frame plating structure of three-terminal regulator

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