TW201103113A - Package structure with lead frame - Google Patents

Package structure with lead frame Download PDF

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Publication number
TW201103113A
TW201103113A TW98123493A TW98123493A TW201103113A TW 201103113 A TW201103113 A TW 201103113A TW 98123493 A TW98123493 A TW 98123493A TW 98123493 A TW98123493 A TW 98123493A TW 201103113 A TW201103113 A TW 201103113A
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TW
Taiwan
Prior art keywords
pin
pad
lead frame
wafer
lead
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Application number
TW98123493A
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Chinese (zh)
Inventor
Ju-Tsung Chou
Yi-Cheng Chen
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Chipsip Technology Co Ltd
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Priority to TW98123493A priority Critical patent/TW201103113A/en
Publication of TW201103113A publication Critical patent/TW201103113A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

A package structure having a lead frame and a chip is provided. The lead frame has a plurality of lead groups in which each lead group has at least a first lead having a bending lead and a second lead. The chip is disposed on the lead groups, and has a plurality of first pads and second pads thereon. Each lead group corresponds to at least one of the first pads and one of the second pads, and each first lead is adjacent to one of the first pads, and each second lead is adjacent to one of the second pads. The bending lead curvedly extends from the first lead to a position in front of an end of the second lead, and electrically connects with the first pad or the second pad.

Description

201103113 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝結構，且特別是有關 於一種具導線架之封裝結構。 【先前技術】 '在半導體封裝結構中，常會將晶片設置於導線架上， 並透過數個銲線電性連接晶片之銲墊至導線架之引腳，再 透過此些引腳電性連接至外部裝置（如印刷電路板）之接 點，以傳送晶片之電性訊號至外部裝置。 依各個銲墊所傳送之電性訊號的區別，此些銲墊可分 為電源銲墊、接地銲墊或訊號銲墊等。此些銲墊的電性排 序需與此些引腳的腳位排序一致，此些銲線亦需依序地電 性連接各個銲墊及其對應之引腳，才能將晶片之電性訊號 正確地傳送至外部裝置。若改用不同的晶片，使得此些銲 墊的電性排序有所變更時，此些銲線即無法依序地連接各 個銲墊及其對應之引腳，將導致二個以上的銲線互相交會 而造成短路。 舉例而言，請參閱第1A圖及第1B圖所示，第1八圖 繪不習知技術中封裝結構之剖面示意圖， 之連接方式的示意圖。封^ =及:封，广_2。具有1片座 此鮮塾;7 =晶片座21上，並具有數個銲塾31。此 為塾3! --對應此些引腳22 ’並透過此些鲜線依序 201103113 地電性連接此些引， 導電材料62電性連接夕卜部再透過/=腳22之表面23及 蓋導線架2〇、a^^n；& 、置〇之接點6丨。封膠50覆 之表面23。 此些銲線40，並顯露此些引腳22 .二個以上 的腳位^序—致的電性排序會與此些引腳22 η及其對應之引腳π了銲、線40依序地電性連接各個銲塾 至外部裝置6〇之接點:正妙確地傳送晶4 30之電性訊號 的晶片30，使得此。’、、'、而’ #改用不同款式或廢牌 些引腳22料法一二一 =31❸電性排序有所變更時，此 的銲線40互相交會而造成短路㈣31將導致 例如：在第1Β圖中， 銲墊並透過銲線4〇a電:片3〇之-銲墊31a為電源 mu未 電生連接引腳22a，另一銲墊31b為接 地知塾並透過銲線働b為接 與銲魂40b 电性遷接引腳2几，此時銲線40a 序排列，故不會有交會的情形產生，是， ;===片3〇，使得銲墊…改為#地銲墊並透過 、、” 接引腳22b，而銲墊31b改為電源銲墊並透過 銲線40b電性連接引腳22a時，將導致銲線4〇a與銲線4〇b 於交會處41互相交會而造成短路。 由上可知，導線架2〇只適用於單一特定的晶片3〇， 而無法用於不同電性排序的晶片3G，亦即無法對不同的晶 ^ 30重新配置電性訊號’使得導線架2()之使用範圍有所 欠限。另一方面，如欲使用導線架2〇與不同電性排序的晶 片30，則需重新設計外部裝置⑼之電路，以變更各個接 點61之電性訊號，反而需耗費更大的成本。 201103113 有鑒於此，需要提供一種具創新性與進步性的封裝結 構，以解決上述之問題。 【發明内容】 本發明之目的，係提供一種具導線架之封裝結構，藉 由彎腳連接引腳至非鄰近的銲墊，以重新配置各個銲墊之 電性排序方式，使各個銲線不會互相交會而造成短路，讓 導線架適用於各種不同電性排序的晶片，毋須重新設計外 部裝置之電路。而且，晶片可設置於晶片座、引腳群或另 一晶片上，以提供多樣化的設置方式。 本發明提供一種具導線架之封裝結構，其包含一導線 架及一第一晶片。導線架具有數個引腳群，每一引腳群具 有至少一第一引腳及至少一第二引腳，第一引腳具有一彎 腳。第一晶片位於此些引腳群上，並具有數個第一銲墊及 數個第二銲墊，每一引腳群對應至少一第一銲墊及至少一 第二銲墊。其中，第一引腳鄰近第一銲墊，第二引腳鄰近 第二銲墊，彎腳自第一引腳彎曲地延伸到第二引腳之端部 的一方，並電性連接第一銲墊或第二銲墊。 另外，導線架亦可具有一晶片座，用以設置第一晶片。 封裝結構更包含一封膠，用以覆蓋彎腳及第一晶片等。 在本發明之一實施例中，彎腳係透過一銲線電性連接 第一銲墊或第二銲墊。當彎腳介於第二引腳與第二銲墊之 間時，第二引腳可透過另一銲線跨越彎腳，以電性連接第 一鲜塾或第二鮮塾。 在本發明之另一實施例中，彎腳係透過一銲球電性連 201103113 接第一銲墊或第二銲墊。告 時’至少一第一銲墊面對-銲墊或第二銲墊 連接第一引腳。 腳，並透過另一銲球電性 端部==另彎聊與至少-第二引腳之 *本發明之二二，電性隔離。 字形、-Z字形、_s字來㈣與第-引腳形成-L 少二第1腳形成-U字形1_—/字字^之形狀，亦可與至 在本發明之另一實施例子二或-F字形之形狀。 由内而外形成一内引 母第一引腳或第二引腳 内，並與-腳處於相同的平面：:内弓丄腳=於封膠 腳之一部分或全部顧霞用以叹置弟一晶片。外引 晶片’第二晶片設置於㈣腳或第一巧；f更f含-第二 相對之一第一面及一第一面，^ :片上。内⑽具有 二面用以設置該第-曰：，第一面與第-晶片貼合，第 第一晶片之第^=二面可透過1線電性連接 第二晶片二;=Γ，並透過-鋒球電性連接 距，以避免銲線接觸到第二晶^第一晶片與第二面之間 而外===:實施'中，第一引腳或第二引腳由内 内引腳密封於㈣肉腳、一第二内引腳及一外引腳。第-=，„内’並與變腳處於相同的平面，用以設 處 201103113 第二晶片設置於第一内引腳、第二内引腳或第一晶片上。 第一内引腳具有相對之一第一面及一第二面，第一面用以 設置該第一晶片，第二面用以設置該第二晶片，並透過 一銲線電性連接第二晶片之一第三銲墊。 【實施方式】 以下將以圖式及詳細說明清楚闡釋本發明之精神，凡 熟悉此技術領域之人員，在瞭解本發明之實施例後，當可 Φ 由本發明所教示之技術，加以改變及修飾，其並不脫離本 發明之精神與範圍。 請參閱第2A圖，係為本發明具導線架之封裝結構中 第一晶片與導線架之第一種連接方式的示意圖。圖中，封 裝結構100包含一導線架200及一第一晶片300。 導線架200具有數個引腳群210，此些引腳群210亦 包含一引腳群210a、一引腳群210b及一引腳群210c,,.等。 每一引腳群210具有一至數個第一引腳220及第二引腳 φ 230,其數量之多寡可依設計需求加以劃分與調整。第一引 腳220具有一彎腳221，彎腳221與第一引腳220為一體 成型。此些引腳群210之第一引腳220與第二引腳230依 一排列方向、一排列順序、一排列形狀或一排列規則排列 於第一晶片300之兩邊或周邊。每一第一引腳220或第二 引腳230可為一引指、一導腳或一接腳等。 第一晶片300設置於此些引腳群210上，並具有數個 銲墊，此些銲墊定義為數個第一銲墊310及數個第二銲墊 311。依各個銲墊所傳送之電性訊號的區別，每一第一銲墊 201103113 310或第二銲墊311可為一電源銲墊、一接地銲墊或一訊 號銲墊等。每一引腳群210對應至少一第一銲墊310及至 少一第二銲墊311，其中第一引腳220鄰近第一銲墊310， 第二引腳230鄰近第二銲墊311。換句話說，與第一引腳 相鄰或對應的鐸塾定義為第一銲誓310’而與第二引腳 230相鄰或對應的銲墊定義為第二銲墊3ΐι。此些第一銲墊 31〇與此些第二銲墊311可為單排排列、雙排排列、環狀 排列、矩陣式制或各種的排列方式。 ^ ^201103113 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package structure, and more particularly to a package structure having a lead frame. [Prior Art] In a semiconductor package structure, a wafer is often placed on a lead frame, and a plurality of bonding wires are electrically connected to the pads of the wafer to the leads of the lead frame, and then electrically connected to the leads through the pins. A contact of an external device (such as a printed circuit board) to transmit electrical signals of the chip to the external device. According to the difference of the electrical signals transmitted by the pads, the pads can be divided into power pads, ground pads or signal pads. The electrical ordering of the pads needs to be consistent with the ordering of the pins of the pins. These bonding wires also need to be electrically connected to the pads and their corresponding pins in order to correctly correct the electrical signals of the chips. Transfer to the external device. If different wafers are used to change the electrical ordering of the pads, the bonding wires cannot sequentially connect the pads and their corresponding pins, which will result in more than two bonding wires. Short-circuit caused by rendezvous. For example, referring to FIG. 1A and FIG. 1B, FIG. 18 is a schematic cross-sectional view showing a package structure in a prior art, and a schematic diagram of a connection manner thereof. Seal ^ = and: seal, wide _2. It has a 1-seat holder, which is on the wafer holder 21, and has a plurality of pads 31. This is 塾3! -- corresponding to the pins 22' and electrically connected to the leads through the fresh lines in sequence 201103113, the conductive material 62 is electrically connected to the outer portion of the surface 23 and the cover of the foot 22 The lead frame 2〇, a^^n;&, and the contact point 6〇. The surface of the sealant 50 is covered 23. The bonding wires 40 and the pins 22 are exposed. The electrical ordering of the two or more pins will be π-welded with the pins 22 η and their corresponding pins, and the line 40 is sequentially The connection of each of the soldering pads to the external device 6 is electrically connected: the wafer 30 which is precisely transmitting the electrical signals of the crystals 30 is made. ',, ', and '# change to use different styles or waste cards 22 materials method one by one = 31 ❸ when the electrical order is changed, this wire 40 crosses each other and causes a short circuit (four) 31 will cause for example: In the first figure, the pad is transmitted through the bonding wire 4〇a: the chip 3〇-the pad 31a is the power source mu, the electrical connection pin 22a, and the other pad 31b is grounded and transmitted through the bonding wire 働b In order to connect with the welding soul 40b, the electrical connection pins 2 are arranged. At this time, the bonding wires 40a are arranged in order, so there will be no intersection situation. Yes, ;===3〇, so that the welding pad... is changed to #地When the pad is connected to the lead 22b, and the pad 31b is changed to the power pad and electrically connected to the pin 22a through the bonding wire 40b, the bonding wire 4〇a and the bonding wire 4〇b are at the intersection. 41 is short-circuited by each other. As can be seen from the above, the lead frame 2〇 is only suitable for a single specific wafer 3〇, but cannot be used for different electrically ordered wafers 3G, that is, it is impossible to reconfigure the electrical properties of different crystals. The signal 'make the use range of the lead frame 2 () is limited. On the other hand, if you want to use the lead frame 2 and the differently ordered wafer 30, you need to The circuit of the external device (9) is designed to change the electrical signal of each contact 61, which in turn requires more cost. 201103113 In view of this, it is necessary to provide an innovative and progressive packaging structure to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a package structure with a lead frame, by connecting a pin to a non-adjacent pad to reconfigure the electrical order of each pad so that each wire is not Will cross each other and cause a short circuit, so that the lead frame can be applied to a variety of different electrically ordered wafers, no need to redesign the circuit of the external device. Moreover, the wafer can be placed on the wafer holder, pin group or another wafer to provide diversification The invention provides a package structure with a lead frame, comprising a lead frame and a first chip. The lead frame has a plurality of pin groups, each pin group having at least one first pin and at least one a second pin having a bent leg. The first chip is located on the pin group and has a plurality of first pads and a plurality of second pads, each pin The group corresponds to at least one first pad and at least one second pad, wherein the first pin is adjacent to the first pad, the second pin is adjacent to the second pad, and the bent leg extends from the first pin to the first One end of the two pins is electrically connected to the first pad or the second pad. In addition, the lead frame may have a wafer holder for arranging the first wafer. The package structure further includes a glue for use. In one embodiment of the invention, the bent leg is electrically connected to the first pad or the second pad through a bonding wire. When the bending leg is interposed between the second pin and the first When the two pads are between the second pads, the second pin can be electrically connected to the first fresh oyster or the second fresh oyster through another bonding wire. In another embodiment of the present invention, the bent legs are transmitted through a The solder ball is electrically connected to the first pad or the second pad of 201103113. At least one first pad facing-pad or second pad is connected to the first pin. The foot, and through another solder ball electrical end == another bend chat with at least - the second pin * the second of the invention, electrically isolated. The shape of the glyph, the -Z shape, the _s word (4) and the first pin form -L and the second leg form the shape of the U-shaped 1_-/word ^, or may be in another embodiment 2 of the present invention or -F shape. Forming an inner lead in the first pin or the second pin from the inside out, and in the same plane as the - foot:: inner bow and foot = part or all of the rubber foot is used to sigh A wafer. The outer wafer 'the second wafer is disposed on the (four) leg or the first chip; the f f includes - the second opposite one of the first side and the first side, ^: on the sheet. The inner surface (10) has two sides for setting the first surface: the first surface is bonded to the first wafer, and the second surface of the first wafer is electrically connected to the second wafer 2 through the first line; Through the - edge ball electrical connection distance, to avoid the wire contact between the second crystal and the second surface and the second side of the outer ===: implementation 'in the first pin or the second pin from the inner The pin is sealed to the (four) meat foot, a second inner pin and an outer pin. The first -=, „内' is in the same plane as the variable foot, and is used to set the 201103113 second chip on the first inner lead, the second inner lead or the first wafer. The first inner lead has a relative a first surface and a second surface, the first surface is used to set the first wafer, the second surface is used to set the second wafer, and the third surface of the second wafer is electrically connected through a bonding wire BRIEF DESCRIPTION OF THE DRAWINGS The spirit of the present invention will be clearly explained in the following description and detailed description, and those skilled in the art, after understanding the embodiments of the present invention, may be modified by the teachings of the present invention. Modifications, which do not depart from the spirit and scope of the present invention. Please refer to FIG. 2A, which is a schematic diagram of the first connection mode of the first wafer and the lead frame in the package structure of the lead frame of the present invention. 100 includes a lead frame 200 and a first chip 300. The lead frame 200 has a plurality of pin groups 210, and the pin group 210 also includes a pin group 210a, a pin group 210b, and a pin group 210c. , etc. Each pin group 210 has one to several The number of pins 220 and the second pin φ 230 can be divided and adjusted according to design requirements. The first pin 220 has a bent leg 221, and the bent leg 221 is integrally formed with the first pin 220. The first pin 220 and the second pin 230 of the pin group 210 are arranged on both sides or the periphery of the first wafer 300 in an arrangement direction, an arrangement order, an arrangement shape or an arrangement. Each of the first pins 220 Or the second pin 230 can be a finger, a pin or a pin, etc. The first die 300 is disposed on the pin group 210 and has a plurality of pads, and the pads are defined as a plurality of pads. a solder pad 310 and a plurality of second pads 311. Each of the first pads 201103113 310 or the second pads 311 can be a power pad and a ground pad according to the difference of the electrical signals transmitted by the pads. Pad or a signal pad, etc. Each pin group 210 corresponds to at least one first pad 310 and at least one second pad 311, wherein the first pin 220 is adjacent to the first pad 310, and the second pin 230 is adjacent to a second pad 311. In other words, a 相邻 adjacent or corresponding to the first pin is defined as a first swearing 310' and The solder pads adjacent to or corresponding to the pins 230 are defined as the second pads 3 ΐ. The first pads 31 〇 and the second pads 311 can be arranged in a single row, in a double row, in a ring array, or in a matrix. Or a variety of arrangements. ^ ^

母:f腳221自第一引腳22〇彎曲地延伸到第二引腳 之端部的一方，並透過一銲線400電性連接第一銲墊 」〇或第二銲墊311。如此，藉由彎腳221之長度延伸，使 鄰近彎腳221的第二鮮墊3U，皆可經由彎腳221 座第-Ϊί 一引腳22G。因此，本發明可提供第一銲塾310 1重新配置電性訊號之管道，亦可提供導線 ^ 200與具有不同電性排序的第-晶片30G進行封裝 此之=作上，彎腳221、第一引腳22〇與第二引腳23〇彼 作可組成各種不同的變化，僅舉例數種態樣如下 對於未舉例的態樣，亦應包含在本發明之範圍内。 如引腳群210所示，盆且右-楚一 21 oorv 弓I腳230。二第一引腳22〇之彎腳221各；-第二 線_電性連接第一鮮塾3U)或第二銲㈣/少一銲 ^腳群210a所示，其具有二第一㈣22〇及 “、3一〇。二第一引腳220之彎腳221各自朝對方延伸7 透過二銲線400電性連接二第一銲塾 -增 ’ 皆介於第-弓丨 、干塾10° 一’弓腳221 第—引腳230與第二銲㈣1之間’第二弓 201103113 透過另一銲線400a跨越二彎腳221，以電性連接第二銲墊 311。如此’可避免銲線400a與銲線400互相交會而短路。 如引腳群21〇b所示，其具有一第一引腳220及一第二 引腳230。第一引腳220之彎腳221介於第二引腳230與 第一銲墊311之間，第二銲墊311透過一銲線4〇〇電性連 接彎腳221，第二引腳23〇透過另一銲線4〇〇b跨越彎腳 22卜以電性連接第—銲墊310。如此，可避免第二銲墊311 為了電性連接第一引腳220，而以銲線4〇〇跨越銲線4〇〇b 造成互相交會及短路。 如引腳群210c所示，其具有二第一引腳22〇及二第二 引腳230。二第一引腳220共同具有一彎腳221。彎腳221 之#々介於一第二引腳230與第二銲塾311之間，第二 銲墊311透過一銲線400c電性連接彎腳221。如此，第二The mother: the f-foot 221 extends from the first pin 22 〇 to one of the ends of the second pin, and is electrically connected to the first pad 〇 or the second pad 311 through a bonding wire 400. Thus, by extending the length of the bending leg 221, the second fresh pad 3U adjacent to the bending leg 221 can pass through the bending pin 221 to the first pin 22G. Therefore, the present invention can provide a first solder fillet 310 1 to reconfigure the electrical signal of the pipeline, and can also provide the wire ^ 200 and the first wafer 30G with different electrical ordering for packaging, the bending, the 221, the first A pin 22 〇 and a second pin 23 can be formed into various variations, and only a few examples are as follows. For the non-exemplified aspects, it should also be included in the scope of the present invention. As shown by pin group 210, the basin is right-che- 21 oorv bow I-foot 230. Two first pins 22 〇 each of the curved legs 221; - second wire _ electrically connected to the first fresh 塾 3U) or second welded (four) / less one welding ^ foot group 210a, which has two first (four) 22 〇 And "3 〇. The first pin 220 of the first pin 220 221 extends to each other 7 through the second wire 400 electrically connected to the first wire 塾 - increase" are in the first - bow, dry 10 ° A 'bow 221' between the first pin 230 and the second solder (four) 1 'the second bow 201103113 passes through the other bonding wire 400a across the two bending legs 221 to electrically connect the second pad 311. This can avoid the bonding wire 400a and the bonding wire 400 meet each other and short-circuit. As shown in the pin group 21〇b, it has a first pin 220 and a second pin 230. The bent pin 221 of the first pin 220 is between the second lead Between the leg 230 and the first pad 311, the second pad 311 is electrically connected to the bent leg 221 through a bonding wire 4, and the second pin 23〇 passes through the other bonding wire 4〇〇b across the curved leg 22 The first bonding pad 310 is electrically connected. In this way, the second bonding pad 311 can be prevented from being electrically connected to the first pin 220, and the bonding wires 4〇〇 cross the bonding wire 4〇〇b to cause mutual intersection and short circuit. Pin group 210c The first pin 220 has a bent leg 221. The bent leg 221 is between a second pin 230 and a second solder. Between the 塾 311, the second pad 311 is electrically connected to the bent leg 221 through a bonding wire 400c. Thus, the second

要說明的疋’上述之銲線4〇〇a、銲線4〇〇b及銲線4〇〇c 皆包含於此些銲線400内。 凊參閱第2B圖’係為本發日^線架之封裝結構中第 -晶片與導線架之第二種連接方式的示意圖。圖中，封裝 結構100包含-導線架200及一第一晶片·。 221，彎腳221與第一引腳 210之第一引腳220與第二 列順序、一排列形狀或一排 導線架200具有數個引腳群211’此些引卿群211亦包 含一引腳群21U及一引腳群211b··.等。每一引腳群211具 有-至數個第-引腳220及第二引腳23()，其數量之多寡 可依設計需求加以劃分與調整。第一引腳22()具有一弯腳 引腳220為一體成型。此些引腳群 第二引腳230依一排列方向、一排 一排列規則排列於第一晶片3〇〇之 201103113 兩邊或周邊。每一第一引腳220或第二引腳23〇可為一引 指、一導腳或一接腳等。 第一晶片300設置於此些引腳群211上，並且有數個 銲塾’此些銲較義為數個第—銲墊31()及數個第二録塾 311。依各個銲墊所傳送之電性訊號的區別， 310或第二銲墊311可為一電 ’ ^等。母-引腳群211對應至少一第—銲墊及至 ^ = 一銲墊3H，其中第一引腳22〇鄰近第一鲜塾則， 第「引腳230鄰近第二銲塾311。換句話說，與第一引腳 220相鄰或面對的銲塾定義 、 230知h 為第一知塾310，而與第二引腳 :相鄰或面對的銲墊定義為第二銲墊3ΐι。此些第一銲墊 31〇與此些第二銲墊311可糸留祕秘 二 排列、矩陣弋排旧夂接為排排歹、雙排排列、環狀 跑陴式排列或各種的排列方式。 230 ί二彎腳221自第一引腳220彎曲地延伸到第二引腳 以伴持一方’並與第二引腳230之端部相隔一間距， =電性隔離。每-彎腳221面對第一鲜塾谓或第二 ⑽或二=7銲球性連接所面對之第-銲墊 得如 。如此，藉由彎腳221之長度延伸，使 電性I面對膏腳221的第二銲墊3η，皆可經由彎腳221 與、接第一引腳220。因此，本發明可提供第一銲墊31〇 =二銲塾3U重新配置電性訊號之管道，亦可提供導線 ^ 〇與具有不同電性排序的第一晶片300進行封裝。 此之實作上，彎腳221、第一引腳220與第二引腳230彼 間，還可組成各種不同的變化，僅舉例數種態樣如下。 一對於未舉例的態樣，亦應包含在本發明之範圍内。 如引腳群211所示，其具有一第一引腳22〇及二第二 201103113 = 230。_第一銲塾31〇及一第二鮮墊3ιι面對 H=21’並各自透過銲球4w電性連接彎腳如。 _ 230二群第其具有—第—引腳咖及二第二 對第-引撕… 电任建接弓腳221。第-輝墊31〇面 2〇,並透過銲球41〇a電性連接第一引腳22〇。 ^ 230 第一引腳22G共同且有-f腳221 31G。同時’此三 銲塾31】，f 尋腳22卜f腳221面對二第二 並透過一銲球41〇電性連接二第二銲墊Η】。 此外，如第2A圖及第迚圖所示， 形成一 L字形、一 z字形、 =狀。她亦可與至少二第-引腳2二= 肤飞子形或—F字形之形狀。再者，彎腳221之带 之彎= 斤非線'=生之形狀如第2A圖"腳群η。: 之ri 線性之形狀如第2B圖中引腳群211 #腳221所示，其可為階梯狀或f狐狀等形狀。 以下將運用第2A圖及第2B圖所示之第一晶 ^之連接方式的精神’提供數個不同的實施例，以進一步 =本發明具導線架之封褒結構的應用，但此些實施= 為舉例說明之用，而非用以限制本發明。 請參閱第3圖，係為本發明具導線架之封裝結構 :實施例的剖面示意圖。在本實施例之封裝結構1〇〇中， 第-晶片·與導線架雇之基本架構及連接方式 11 201103113 考上述第2A圖之詳細說明，於此不再贅述。 在第3圖中，封裝結構⑽位於外部裝置 電路板）上，並透過數個導電材料9〇2 (如印刷 9〇〇之接點901。封裝結構100主要包含一 夕卜部装置 第一晶片300。導線架200具有數個5|腳群训，、〇二，一 3〇〇位於此些引腳群21〇上。封裝結構1〇〇可包人一晶片 封膠800至少覆蓋彎腳221及第一晶片：5 = 200可經彎折處理，使得每一第一引腳22〇 線架The above-mentioned bonding wire 4〇〇a, bonding wire 4〇〇b, and bonding wire 4〇〇c are all included in these bonding wires 400. Referring to FIG. 2B, FIG. 2 is a schematic view showing the second connection mode of the first wafer and the lead frame in the package structure of the present invention. In the figure, the package structure 100 includes a lead frame 200 and a first wafer. 221, the first pin 220 of the bending pin 221 and the first pin 210 and the second column sequence, an array shape or a row of lead frame 200 have a plurality of pin groups 211'. The group 211 also includes an index. The foot group 21U and a pin group 211b··. Each pin group 211 has - to a plurality of first-pins 220 and second pins 23 (), the number of which can be divided and adjusted according to design requirements. The first pin 22() has a bent pin 220 which is integrally formed. The pin groups of the second pins 230 are arranged on both sides or the periphery of the first wafer 3's 201103113 in a row and one row. Each of the first pins 220 or the second pins 23A can be an index, a lead or a pin or the like. The first wafer 300 is disposed on the lead groups 211, and there are a plurality of solder pads 'the solders are equivalent to a plurality of first pads 31 () and a plurality of second recording pads 311. Depending on the difference of the electrical signals transmitted by the pads, the 310 or the second pads 311 may be an electric device or the like. The mother-pin group 211 corresponds to at least one first pad and to a pad 3H, wherein the first pin 22 is adjacent to the first fresh hole, and the first pin 230 is adjacent to the second pad 311. In other words The solder fillet definition adjacent to or facing the first pin 220, 230 is known as the first knowledge 310, and the second lead: the adjacent or facing solder pad is defined as the second solder pad 3ΐ. The first pads 31 〇 and the second pads 311 can be arranged in a secret arrangement, and the matrix 弋 夂 为 为 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹 歹The 230 二2 bending leg 221 extends from the first pin 220 to the second pin to accompany the one side and is spaced apart from the end of the second pin 230 by an electrical isolation. Each of the bending legs 221 Facing the first fresh 塾 or the second (10) or the second = 7 solder ball connection, the first-pad is as follows. Thus, by extending the length of the curved leg 221, the electrical I faces the paste 221 The second bonding pad 3n can be connected to the first pin 220 via the bending leg 221. Therefore, the present invention can provide a first bonding pad 31〇=2 soldering 3U reconfiguring the electrical signal pipeline, and can also provide The wire 〇 is packaged with the first wafer 300 having different electrical ordering. In this implementation, the bending leg 221, the first pin 220 and the second pin 230 may also be formed into various variations, only For example, a plurality of aspects are also included in the scope of the present invention. As shown by the pin group 211, it has a first pin 22 〇 and a second 201103113 = 230. _The first soldering 31塾 and the second fresh mat 3ιι face H=21' and each of them is electrically connected to the bent foot through the solder ball 4w. _ 230 two groups have the same - the first pin coffee and two second For the first-to-tear... The electric-option is connected to the bow 221. The first-bush pad 31 is 2〇, and is electrically connected to the first pin 22〇 through the solder ball 41〇a. ^ 230 The first pin 22G is common There are -f feet 221 31G. At the same time 'this three-weld 31', f-foot 22 22 feet 221 face two second and through a solder ball 41 〇 electrically connected two second pads Η. As shown in Fig. 2A and Fig. 2, an L-shape, a z-shape, and a shape are formed. She can also be shaped with at least two first-pins 2 = skin fly-shaped or - F-shaped. Foot 221 belt Bend = jin non-line '= shape of life as in Fig. 2A " foot group η.: ri The shape of the line is as shown in pin group 211 # foot 221 in Fig. 2B, which can be stepped or f-like The following description will be made using the spirit of the first crystal connection method shown in FIGS. 2A and 2B to provide a plurality of different embodiments to further apply the sealing structure of the lead frame of the present invention, but The implementations are for illustrative purposes and are not intended to limit the invention. Referring to Figure 3, there is shown a cross-sectional view of an embodiment of the present invention having a leadframe package structure. In the package structure 1 of the present embodiment, the basic structure and connection mode of the first wafer and the lead frame are employed. 11 201103113 The detailed description of the above FIG. 2A is omitted, and details are not described herein again. In FIG. 3, the package structure (10) is located on the external device circuit board and is permeable to a plurality of conductive materials 〇2 (eg, 9 印刷 contacts 901. The package structure 100 mainly includes an imaginary device first wafer 300) The lead frame 200 has a plurality of 5|foot group trainings, and the second and third sides are located on the pin groups 21〇. The package structure 1 can cover a wafer sealant 800 covering at least the bent legs 221 and The first wafer: 5 = 200 can be bent, so that each first pin 22 wire frame

由内而外形成-内引腳240及-外弓丨腳25〇。：弓丨:230 密封於封膠800内，並與第一引腳220之彎腳221 240 同的平面’用以設置第-晶片30〇ϋ_25(^ —= 或全部顯露於封膠800外，用以電性連捿外部裝置9^。为 ★封震結構1〇〇可包含一黏合層700，黏合層7〇〇貼°人 第一晶片300於引腳群210之内引腳240上。每一内 0 240具有相對之一第一面241及一第二面242，第—面引腳 以黏合層700貼合第-晶片3〇〇。第二面242透過 ^ 電性連接第一晶片300之第一銲墊31〇或第二銲墊3ιι。 封農結構100更包含一第二晶片5〇〇，其設置於内 腳240之第二面242，並具有數個第三 'Formed from the inside out - the inner pin 240 and the outer leg foot 25 〇. : Bow: 230 is sealed in the sealant 800 and is flush with the plane 221 240 of the first pin 220 to set the first wafer 30 〇ϋ _25 (^ —= or all exposed outside the seal 800, The electrical device is electrically connected to the external device 9 . The sealing structure 1 can include an adhesive layer 700 , and the adhesive layer 7 is attached to the pin 240 of the first chip 300 . Each of the inner portions 0 240 has a first surface 241 and a second surface 242. The first surface of the first surface is bonded to the first wafer 3 by the adhesive layer 700. The second surface 242 is electrically connected to the first wafer. The first pad 31 〇 or the second pad 3 ι of the 300. The agricultural structure 100 further includes a second wafer 5 〇〇 disposed on the second side 242 of the inner leg 240 and having a plurality of third '

Ml透過銲球411電性連接第二面242。每一銲球4ιι具有 一定的高度，可加大第二晶片5〇〇與第二面242之間ς， 使f二晶片5〇〇遠離銲線4〇〇而不致互相接觸。在本發明 另一實施例中，第二晶片500亦可設置於第一晶片300上。 °用參閱第4圖，為本發明具導線架之封裝結構之第一 實施例的剖面示意圖。在本實施例之封裝結構1〇〇中，^ 12 201103113 一晶片300與導線架200之基本架構及連接方式，請參考 上述第2B圖之詳細說明，於此不再贅述。 在第4圖中’封裝結構1 〇〇位於外部裝置9〇〇上，並 透過數個導電材料902電性連接外部裝置9〇〇之接點9〇1。 封裝結構100主要包含一導線架200及一第一晶片3〇〇。 導線架200具有數個引腳群211，第一晶片300位於此些 引腳群211上。封裝結構100可包含一封膠8〇〇，封膠8〇〇 至少覆蓋彎腳221及第一晶片300。導線架200可經彎折 處理，使得每一第一引腳220或第二引腳230由内而外形 成一第一内引腳260、一第二内引腳270及一外引腳280。 第一内引腳260密封於封膠800内，並與彎腳221處於相 同的平面，用以設置第一晶片300。第二内引腳270密封 於封膠800内’並與第一内引腳260處於不同的平面。外 引腳280之一部分或全部顯露於封膠800外，用以電性連 接外部裝置900。 封裝結構1〇〇亦可包含一第二晶片500及一黏合層 701，第二晶片500具有數個第三銲墊510。第一引腳220 或第二引腳230之第一内引腳260具有相對之一第一面261 及一第二面262。第一面261用以設置第一晶片300，並透 過銲球410電性連接第一銲墊310或第二銲墊311。第二 面262用以設置第二晶片500，並藉由黏合層701貼合第 二晶片500，且第二面262透過銲線401電性連接第三銲 墊510。在本發明之另一實施例中，第二晶片500亦可設 置於第二内引腳270或第一晶片300上。 封裝結構800更包含一第三晶片600及一黏合層702。 13 201103113 第 晶片600設置於第-晶片3⑻或第二内引腳27〇上， 並具有數個第四銲墊010。第二内引腳27〇具 第-面271及-第二面272。第-面271透過銲球412電 性連接第三晶片600之第四銲墊61〇，第 面272透過銲Ml is electrically connected to the second side 242 through the solder ball 411. Each of the solder balls 4 ι has a certain height, and the entanglement between the second wafer 5 〇〇 and the second surface 242 can be increased, so that the f wafers 5 〇〇 are away from the bonding wires 4 〇〇 without contacting each other. In another embodiment of the present invention, the second wafer 500 may also be disposed on the first wafer 300. Referring to Figure 4, there is shown a cross-sectional view of a first embodiment of a package structure having a lead frame of the present invention. In the package structure of the present embodiment, the basic structure and connection manner of a wafer 300 and a lead frame 200, please refer to the detailed description of FIG. 2B above, and details are not described herein again. In Fig. 4, the package structure 1 is located on the external device 9A, and is electrically connected to the contact 9〇1 of the external device 9 through a plurality of conductive materials 902. The package structure 100 mainly includes a lead frame 200 and a first wafer 3. The lead frame 200 has a plurality of pin groups 211 on which the first wafer 300 is located. The package structure 100 can include a glue 8 〇〇 covering at least the bend 221 and the first wafer 300. The lead frame 200 can be bent so that each of the first pins 220 or the second pins 230 is internally formed into a first inner pin 260, a second inner pin 270 and an outer pin 280. The first inner lead 260 is sealed in the encapsulant 800 and is in the same plane as the bent leg 221 for setting the first wafer 300. The second inner lead 270 is sealed within the encapsulant 800 and is in a different plane than the first inner lead 260. A portion or all of the outer pin 280 is exposed outside the sealant 800 for electrically connecting the external device 900. The package structure 1 can also include a second wafer 500 and an adhesive layer 701. The second wafer 500 has a plurality of third pads 510. The first pin 220 of the first pin 220 or the second pin 230 has a first side 261 and a second side 262 opposite to each other. The first surface 261 is used to set the first wafer 300 and is electrically connected to the first pad 310 or the second pad 311 through the solder ball 410. The second surface 262 is used to set the second wafer 500, and the second wafer 500 is bonded to the second wafer 510 through the bonding layer 701. In another embodiment of the present invention, the second wafer 500 may also be disposed on the second inner lead 270 or the first wafer 300. The package structure 800 further includes a third wafer 600 and an adhesive layer 702. 13 201103113 The first wafer 600 is disposed on the first wafer 3 (8) or the second inner lead 27A and has a plurality of fourth pads 010. The second inner lead 27 has a first face 271 and a second face 272. The first surface 271 is electrically connected to the fourth pad 61 of the third wafer 600 through the solder ball 412, and the first surface 272 is through the solder

線401電性連接第二晶片500之第三銲塾 請參閱第5圖，為本發明具導線架之封震結構之 實施例的剖面示意圖。在本實施例之封裝結構罘二 -晶片300與導線架2〇〇之基本架構及連接方式 = 上述第2A圖之洋細說明，於此不再贅述。The wire 401 is electrically connected to the third pad of the second wafer 500. Referring to FIG. 5, it is a schematic cross-sectional view of an embodiment of the sealing structure of the lead frame of the present invention. In the package structure of the present embodiment, the basic structure and connection mode of the wafer 300 and the lead frame 2 are described in detail in the above-mentioned FIG. 2A, and will not be further described herein.

在第5圖中，封裝結構100位於外部裝置9⑻上， 透過數個導電材料9 0 2電性連接外部裝置9 〇 〇之接點9並 封裝結構100主要包含一導線架200及—笛一 a u。 1〇 導線架200具有一晶片座212及數個引腳群21〇，第一曰 片300位於晶片座212之一面。封裝結構1〇〇可包含一曰曰 膠800’封膠800至少覆蓋彎腳221及第—晶片3〇〇3 一封 架200可經彎折處理，使每一第一引腳22〇 =第二引腳 由内而外形成一内引腳240及一外引腳25〇。内引腳 密封於封膠800内，並與第一引腳22〇之彎腳221處於40 同的平面，且内引腳24〇透過銲線4〇〇電性連接第一，相 300之第-銲塾·或第二銲塾311。外引腳25〇之二曰= 或全部顯露於封膠800外，用以電性連接外部裝置9^。为 封裝結構100可包含一黏合層700，黏合層7〇〇貼八 第一晶片300於晶片座212上。封裝結構1〇〇亦可包人: 第二晶片500及-黏合層術。第二晶片5⑻藉由黏= 701貼合於第一晶片300上，並具有數個第三銲墊，二 弟 14 201103113 三鲜塾51 〇读、 之另一實施過銲線4〇1電性連接内引腳240。在本發明 另一面戎例中’第二晶片500亦可設置於晶片座212之 取内弓丨腳24〇上。 請參％帛 實施例的剖面-f，為本發明具導線架之封裝結構之第四 一晶片3〇〇座^圖。在本實施例之封裝結構1〇0中，第 上述第2B圖之▲線架2〇0之基本架構及連接方式，請參考 又砰細說明，於此不再贅述。 在第6圖φ ,, _ 透過數個導封裝結構100位於外部裝置900上，並 材料902電性連接外部裝置900之接點901。 、曾'、口 1〇〇主要包含一導線架200及一第一晶片3〇(^ '線架200具有一晶片座212及數個引腳群211，第一晶 片300位於晶片座212或此些引腳群211上。封裝結構1〇〇 可包含一封膠800，封膠800至少覆蓋彎腳221及第一曰 ^ 曰曰 片300。導線架200可經彎折處理，使得每一第一引腳22〇 或第二引腳230由内而外形成一第一内引腳26〇、一第二 内引腳270及一外引腳280。 第一内引腳260密封於封膠8〇〇内，並與第一引腳22〇 之彎腳221處於相同的平面。而且，第一内引腳260具有 相對之一第一面261及一第二面262，第一面261透過銲 球410電性連接第一晶片300之第一銲墊310或第二銲墊 311。第二内引腳270密封於封膠8〇〇内，並與第一内引腳 260處於不同的平面。外引腳280之一部分或全部顯露於 封膠800外，用以電性連接外部裝置9〇〇。 封裝結構100可包含一黏合層700，用以貼合第—晶 片300於晶片座212之一面。封裝結構1〇〇更包含一第二 15 201103113 晶片500及一黏合層701。第二晶片500藉由黏合層701 貼合於晶片座212之另一面，並具有數個第三銲墊510， 第三銲墊510透過銲線401電性連接彎腳221或第一内引 腳260之第二面262。在本發明之另一實施例中，第二晶 片500亦可設置於第一内引腳260、第二内引腳270或第 一晶片300上。 封裝結構1〇〇更包含一第三晶片600及一黏合層702。 第三晶片600藉由黏合層702貼合於第一晶片500或第二 内引腳270上，並具有數個第四銲墊610，第四銲墊610 透過銲線402電性連接第二内引腳270。 請參閱第7A圖〜第7H圖，係為本發明具導線架之封 裝結構中各種不同類型之導線架的剖面示意圖。在封裝結 構100中，導線架200除了上述四個實施例之態樣外，亦 可依據内引腳220之長度、外引腳250之形狀、晶片座212 之有無或高低等差異，而形成各種不同的變化組合。然而， 第7A圖〜第7H圖只是本發明所提供之實施例，其它未提 到的導線架200亦應包含在内，而不能排除在外。 卜如第7A圖所示，導線架200具有數個第一引腳220 及數個第二引腳230，每一第一引腳220具有一彎腳221， 彎腳22卜第一引腳220與第二引腳230處於相同的平面。 2、 如第7B圖所示，第7B圖與第7A圖之導線架200 相似。第7B圖之導線架200更具有一晶片座212，晶片座 212之高度高於第一引腳220及第二引腳230之高度。 3、 如第7C圖所示，導線架200具有數個第一引腳220 及數個第二引腳230，每一第一引腳220或第二引腳230 由内而外形成一内引腳240及一外引腳250，第一引腳220 16 201103113 具有一彎腳221，且第一引腳220之内引腳240的長度大 於第二引腳230之内引腳240的長度。 4、 如第7D圖所示，第7D圖與第7C圖之導線架200 相似。第7D圖之導線架200更具有一晶片座212，晶片座 212之高度高於第一引腳220及第二引腳230之高度，而 第一引腳220之内引腳240的長度等於第二引腳230之内 引腳240的長度。 5、 如第7E圖所示，導線架200具有數個第一引腳220 及數個第二引腳230，每一第一引腳220或第二引腳230 由内而外形成一内引腳240及一外引腳250，第一引腳220 具有一彎腳221，外引腳250的形狀為一 J型或一内勾狀。 6、 如第7F圖所示，第7F圖與第7E圖之導線架200 相似。第7F圖之導線架200更具有一晶片座212，晶片座 212之高度等於第一引腳220及第二引腳230之高度。 7、 如第7G圖所示，導線架200具有數個第一引腳220 及數個第二引腳230，每一第一引腳220或第二引腳230 由内而外形成一内引腳240及一外引腳250，第一引腳220 具有一彎腳221，外引腳250的形狀為一 L型或一外彎狀。 8、 如第7H圖所示，第7H圖與第7G圖之導線架200 相似。第7H圖之導線架200更具有一晶片座212，晶片座 212之高度低於第一引腳220及第二引腳230之高度。 综上所述，本發明具導線架之封裝結構，藉由彎腳連 接引腳至非鄰近的銲墊，以重新配置各個銲墊之電性排序 方式，使各個銲線不會互相交會而造成短路，讓導線架適 用於各種不同電性排序的晶片，毋須重新設計外部裝置之 17 201103113 電路。而且，晶片可設置於晶片座、引腳群或另一晶片上， 以提供多樣化的設置方式。 本發明所揭露如上之各實施例中，並非用以限定本發 明，任何熟習此技藝者，在不脫離本發明之精神和範圍内， 當可作各種之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 φ 第1A圖繪示習知技術中封裝結構的剖面示意圖。 第1B圖繪示習知技術第1A圖之封裝結構中晶片與導 線架之連接方式的示意圖。 第2A圖繪示本發明具導線架之封裝結構中第一晶片與 導線架之第一種連接方式的示意圖。 第2B圖繪示本發明具導線架之封裝結構中第一晶片與 導線架之第二種連接方式的示意圖。 第3圖繪示本發明具導線架之封裝結構之第一實施例 _ 的剖面不意圖。 第4圖繪示本發明具導線架之封裝結構之第二實施例 的剖面示意圖。 第5圖繪示本發明具導線架之封裝結構之第三實施例 的剖面示意圖。 第6圖繪示本發明具導線架之封裝結構之第四實施例 的剖面示意圖。 第7A圖〜第7H圖繪示本發明具導線架之封裝結構中 各種不同類型之導線架的剖面示意圖。 201103113In FIG. 5, the package structure 100 is located on the external device 9 (8), electrically connected to the contacts 9 of the external device 9 through a plurality of conductive materials 902, and the package structure 100 mainly includes a lead frame 200 and a flute au . The lead frame 200 has a wafer holder 212 and a plurality of pin groups 21, and the first wafer 300 is located on one side of the wafer holder 212. The package structure 1A can include a silicone 800' sealant 800 covering at least the bent leg 221 and the first wafer 3〇〇3. The frame 200 can be bent to make each first pin 22〇= The two pins form an inner pin 240 and an outer pin 25 由 from the inside out. The inner pin is sealed in the sealant 800 and is in the same plane as the first pin 22's bent leg 221, and the inner lead 24 is electrically connected to the first through the bonding wire 4, and the phase 300 - Weld 塾 or second 塾 311. The external pins 25 曰 曰 = or all of them are exposed outside the sealant 800 for electrically connecting the external device 9^. The package structure 100 can include an adhesive layer 700, and the adhesive layer 7 is attached to the first wafer 300 on the wafer holder 212. The package structure 1 can also be packaged: the second wafer 500 and the adhesive layer. The second wafer 5 (8) is bonded to the first wafer 300 by adhesive = 701, and has a plurality of third pads, the second brother 14 201103113 Sanxian 塾 51 reading, the other implementation of the bonding wire 4 〇 1 electrical Connect the inner pin 240. In another aspect of the present invention, the second wafer 500 may also be disposed on the inner bow foot 24 of the wafer holder 212. Please refer to the section -f of the embodiment, which is a fourth wafer 3 frame of the package structure of the lead frame of the present invention. In the package structure 1〇0 of the present embodiment, the basic structure and connection mode of the ▲ wire frame 2〇0 of the above-mentioned 2Bth drawing, please refer to the detailed description, and details are not described herein again. In Fig. 6, φ, _ is transmitted through the plurality of conductive package structures 100 on the external device 900, and the material 902 is electrically connected to the contacts 901 of the external device 900. The first wafer 300 has a wafer holder 212 and a plurality of lead groups 211. The first wafer 300 is located at the wafer holder 212 or the like. The lead structure 211. The package structure 1A can include a glue 800, and the sealant 800 covers at least the bent leg 221 and the first cymbal plate 300. The lead frame 200 can be bent to make each of the first A pin 22 〇 or a second pin 230 forms a first inner pin 26 〇, a second inner pin 270 and an outer pin 280 from the inside to the outside. The first inner pin 260 is sealed to the seal 8 The first inner lead 260 has a first surface 261 and a second surface 262 opposite to each other. The first inner surface 260 has a first surface 261 and a second surface 262. The ball 410 is electrically connected to the first pad 310 or the second pad 311 of the first wafer 300. The second inner lead 270 is sealed in the encapsulation 8 and is in a different plane from the first inner lead 260. A portion or all of the outer lead 280 is exposed outside the sealant 800 for electrically connecting the external device 9 . The package structure 100 may include an adhesive layer 700 for attaching the first crystal The chip 300 is disposed on one side of the wafer holder 212. The package structure 1 further includes a second 15 201103113 wafer 500 and an adhesive layer 701. The second wafer 500 is bonded to the other side of the wafer holder 212 by the adhesive layer 701 and has The third pad 510 is electrically connected to the curved surface 221 or the second surface 262 of the first inner lead 260 through the bonding wire 401. In another embodiment of the present invention, the second wafer 500 The package structure 1 can also be disposed on the first inner lead 260, the second inner lead 270 or the first wafer 300. The package structure 1 further includes a third wafer 600 and an adhesive layer 702. The third wafer 600 is bonded by an adhesive layer 702 is attached to the first die 500 or the second inner lead 270 and has a plurality of fourth pads 610. The fourth pads 610 are electrically connected to the second inner leads 270 through the bonding wires 402. Please refer to the 7A. Figure 7 ~ Figure 7H is a schematic cross-sectional view of various types of lead frames in the package structure of the lead frame of the present invention. In the package structure 100, the lead frame 200 can be based on the aspects of the above four embodiments. The length of the inner pin 220, the shape of the outer pin 250, the presence or absence of the wafer holder 212, or the height difference However, the various combinations of changes are formed. However, the 7A to 7H drawings are merely embodiments provided by the present invention, and other lead frames 200 not mentioned should also be included, and cannot be excluded. As shown, the lead frame 200 has a plurality of first pins 220 and a plurality of second pins 230. Each of the first pins 220 has a bent leg 221, and the bent pin 22 has a first pin 220 and a second lead. The feet 230 are in the same plane. 2. As shown in Fig. 7B, the Fig. 7B is similar to the lead frame 200 of Fig. 7A. The lead frame 200 of Fig. 7B further has a wafer holder 212 having a height higher than the height of the first pin 220 and the second pin 230. 3. As shown in FIG. 7C, the lead frame 200 has a plurality of first pins 220 and a plurality of second pins 230. Each of the first pins 220 or the second pins 230 forms an internal lead from the inside to the outside. The second pin 220 16 201103113 has a bent leg 221, and the length of the inner pin 240 of the first pin 220 is greater than the length of the inner pin 240 of the second pin 230. 4. As shown in FIG. 7D, the 7D drawing is similar to the lead frame 200 of the 7Cth drawing. The lead frame 200 of FIG. 7D further has a wafer holder 212. The height of the wafer holder 212 is higher than the height of the first pin 220 and the second pin 230, and the length of the pin 240 in the first pin 220 is equal to the length. The length of the pin 240 within the two pins 230. 5. As shown in FIG. 7E, the lead frame 200 has a plurality of first pins 220 and a plurality of second pins 230, and each of the first pins 220 or the second pins 230 forms an internal reference from the inside to the outside. The pin 240 and the outer pin 250 have a bent leg 221, and the outer pin 250 has a J-shape or an inner hook shape. 6. As shown in Figure 7F, Figure 7F is similar to lead frame 200 of Figure 7E. The lead frame 200 of Fig. 7F further has a wafer holder 212 having a height equal to the height of the first pin 220 and the second pin 230. 7. As shown in FIG. 7G, the lead frame 200 has a plurality of first pins 220 and a plurality of second pins 230. Each of the first pins 220 or the second pins 230 forms an internal reference from the inside to the outside. The pin 240 and an outer pin 250 have a bent leg 221, and the outer pin 250 has an L-shape or an outer curved shape. 8. As shown in Figure 7H, Figure 7H is similar to lead frame 200 of Figure 7G. The lead frame 200 of the seventh embodiment has a wafer holder 212 having a height lower than the height of the first pin 220 and the second pin 230. In summary, the package structure of the lead frame of the present invention connects the pins to the non-adjacent pads by bending the legs to reconfigure the electrical ordering manner of the pads so that the wires do not cross each other. Short-circuit, the lead frame is suitable for a variety of different electrically ordered wafers, no need to redesign the external device 17 201103113 circuit. Moreover, the wafer can be placed on a wafer holder, pin group or another wafer to provide a variety of arrangements. The present invention is not limited to the embodiments of the present invention, and various modifications and refinements may be made without departing from the spirit and scope of the present invention. This is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic cross-sectional view showing a package structure in the prior art. Fig. 1B is a schematic view showing the manner in which the wafer and the wire frame are connected in the package structure of the prior art Fig. 1A. 2A is a schematic view showing the first connection mode of the first wafer and the lead frame in the package structure of the lead frame of the present invention. 2B is a schematic view showing a second connection manner of the first wafer and the lead frame in the package structure of the lead frame of the present invention. Fig. 3 is a cross-sectional view showing the first embodiment of the package structure of the lead frame of the present invention. Fig. 4 is a cross-sectional view showing a second embodiment of the package structure of the lead frame of the present invention. Fig. 5 is a cross-sectional view showing a third embodiment of the package structure of the lead frame of the present invention. Figure 6 is a cross-sectional view showing a fourth embodiment of the package structure of the lead frame of the present invention. 7A to 7H are cross-sectional views showing various types of lead frames in the package structure of the lead frame of the present invention. 201103113

【主要元件符號說明】 10 ： 封裝結構 20 ： 導線架 21 ： 晶片座 22, 22a, 22b ： 引腳 23 ： 表面 30 ： 晶片 31, 31a, 31b ： 鲜塾 40, 40a, 40b ： 銲線 41 : 交會處 50 : 封膠 60 : 外部裝置 61 : 接點 62 : 導電材料 100 :封裝結構 200 :導線架 210,210a,210b,210c,211, 211a，211b :引腳群 212 :晶片座 220 :第一引腳 221 :彎腳 230 :第二引腳 240 :内引腳 241, 261，271 :第一面 242, 262, 272 :第二面 250, 280 :外引腳 260 :第一内引腳 270 :第二内引腳 300 :第一晶片 310 :第一銲墊 311 :第二銲墊 400, 400a, 400b, 400c, 401 402 :銲線 410, 410a，411，412 :銲球 500 :第二晶片 510 :第三銲墊 600 :第三晶片 610 :第四銲墊 700, 701, 702 :黏合層 800 :封膠 900 :外部裝置 901 :接點 902 :導電材料 19[Main component symbol description] 10 : Package structure 20 : Lead frame 21 : Wafer holder 22 , 22a , 22b : Lead 23 : Surface 30 : Wafer 31 , 31a , 31b : Fresh 塾 40 , 40a , 40b : Solder wire 41 : Intersection 50: Sealant 60: External device 61: Contact 62: Conductive material 100: Package structure 200: Lead frame 210, 210a, 210b, 210c, 211, 211a, 211b: Lead group 212: Wafer holder 220: First Pin 221: bent leg 230: second pin 240: inner pin 241, 261, 271: first face 242, 262, 272: second face 250, 280: outer pin 260: first inner pin 270 The second inner lead 300: the first wafer 310: the first solder pad 311: the second solder pad 400, 400a, 400b, 400c, 401 402: the bonding wire 410, 410a, 411, 412: solder ball 500: second Wafer 510: third pad 600: third wafer 610: fourth pad 700, 701, 702: adhesive layer 800: sealant 900: external device 901: contact 902: conductive material 19

Claims (1)

201103113 七 申5月專利範圍： =種具導線架之封裝結構，其包含： 少-第群’每一腳群具有至 腳；以及 -引腳’該第-引腳具有一彎 -銲以第:=些:腳::群:r複數個第 鮮墊及至少-第二銲塾；_群對應至少一第一 近4:録：第一引腳鄰近該第一鋅塾，該第二引腳鄰 腳自該第-腳彎曲地延伸到續； ^塾。之端部的-方’並電性連接該第—銲塾或該第二 播2贫t申請專第1項所述之具導線架之封裝社 ：中該些引腳群之第一引腳與第二引腳依一排歹j :晶二 =周咖狀或一排列規則排列於該第 3. 如申請專利範圍第i項所述之具導線架之封裝结 構銲^中該彎腳透過一銲線電性連接該第-銲墊或該第 4. 如申請專利範圍第3項所述之具導線架之封裝結 構’其中該彎腳介於該第二引腳與該第二銲塾之間，該 第一引腳透過另一銲線跨越該彎腳，以電性一 銲墊或該第二銲墊。 第 5. 如申請專利範圍第1項所述之具導線架之封裝結 構，其中該彎腳透過一銲球電性連接該第一銲墊或^第 —塾。 — r 20 201103113 構，利觸5項所述之具導線架之封裳結 、〜彎腳面對该第一銲墊或該第二銲墊。 構，42專：範圍第5項所述之具導線架之封裝結 電性連接該第-引腳。 並透過另一鐸球 構相範圍第1項所狀具導《之封0 該相與該第二引腳之端部相隔-間距。 9.如申請專利範圍第i項所述之且 構，其中該彎腳與該第一引腳形成一 l字形、結 一 S子形或一 τ字形之形狀。 Ζ子形、 H).如申請專利範圍第丨項所述之罝 構’其中該弯腳與至少二第Ί字封裝結 字形或-F字形之形狀。 4 U子形、一E 11. 如申請專利範圍第丨項所述之且 :’其中該第一銲墊或該第二銲墊 泝銲十裝^ 地銲墊或一訊號銲墊。 罨源知墊、一接 12. 如申請專利範圍第！項所述 绫 構，其中該第-引腳或該第二弓丨、„封褒結 -接腳。 # 5丨腳為-引指、-導腳或 13. 如申請專利範圍第丨項 構，更包含-封膠，該封膠至之封褒結 片。 夕復盍邊，考腳及該第一晶 H.如申請專利範圍第13項 結構’其中該第一引腳或該第二引腳由；、:架之封裝 一内引腳，密封於該封膠内，並盥 卜^成： 的平面，該内引腳用以設置該第―、曰、…’腳處於相同 日日片，以及 21 201103113 一外引腳，其—邱八—、入A 該内引聊處於不同二==露於該封膠外，並與 部裝置。 十面該外引腳用以電性連接1 15·如申請專利範圍 結構，更包含-第二晶導線架之封裳 或該第一晶片上。 日曰°又置於该内引腳 結構3::專：：·15項所述之具導線架之封裝 二第一面，與該第-晶片貼合；以及 片。一第二面’相對於該第-面，並用以設置該第二晶 17·如申請專利範圍第16 結構，其中該第-面、h I Κ之具V線架之封裝 誃第一π勒·^ 銲線電性連接該第一晶片之 °〆第薛塾或該第二銲墊，允、类 之 二晶片之-第三銲墊，i銲;=二球=接該第 面之間距’使鱗線不接觸該第二晶片。/、这第一 18.如申請專利範圍第13項所述之具導 、，。構該第-5|腳或該第二引腳由内而外形成·'裝 相同2 = 於該賴’並與料腳處於 二，面6亥第-内引腳用以設置該第一晶片； -第二内引腳，密封於該封膠内 腳處於不同的平面；以及 乐内引 以番：外引腳，其一部分或全部顯露於該封膠外，並用 从電性連接一外部裝置。 結構範㈣18項所述之具導線架之封裝 ^ 3第一晶片，該第二晶片設置於該第一内 Ο 〇 22 201103113 引腳、該第二内引腳或該第一晶片上。 20. 如申請專利範圍第19項所述之具導線架之封装 …構，其中該第一内引腳具有： =第一面，用以設置該第一晶片；以及 =第二面，相對於該第一面，並用以設置該第二晶 μ二該第二面透過一銲線電性連接該第二晶片之一第三 鮮。 21. 如申凊專利㈣第i項所述之具導線架之封裝結 引腳2含—黏合層，該黏合層貼合該第—晶片於該些 一種具導線架之封裝結構，其包含： 腳群Si架’ Ϊ有一晶片座及複數個引腳群，每-引 ::有J少一第一引腳及至少一第二引腳，該第一引 腳具有一彎腳；以及 銲整片座上’並具有複數個第- 執,個第一1于墊，母一引腳群對應至少一第-至*及至少一第二銲墊； 近該鋥ΐ第一引腳鄰近該第-銲墊’該第二引㈣ 二二:m第一引腳彎曲地延伸物 銲墊。彳的-方’亚電性連接該第-銲墊或該第： 結槿2,3= 申請專利範㈣22項所述之具導線架之封！ 、&gt;〇構’其中該4b引腳雜夕楚 . 方向一 腳與第二㈣依一㈣ 第-曰片之Γ! 排列形狀或一排列規則排列於該 示日日片之兩邊或周邊。 24·如申請專利範圍第22項所述之具導線架之封裝 23 [S 201103113 結構，其中該彎腳介於該晶片座與該第二引腳之 25.如申請專利範圍第22項所述之具導 二° 、ί!鮮i中該f腳透過-銲線電性連接該第-鮮塾= 結構26：L申請專利範圍第25項所述之具導線架之封裝 m，、中4第—引腳透過另-銲線跨越該彎腳，以^ 性連接該第一銲墊或該第二銲墊。 電 27.如申請專利範圍# 22工員所述之具導 中該f腳透過-鲜球電性連接該第-鲜塾或; 社爐請專利範圍第27項所述之具導線架之财 、、。構，其中該彎腳面對該第一銲墊或該第二輝塾。震 姓構MS請專利㈣第27項所述之具導線架之封裳 一銲墊面對該第-引腳，並透過另-2 球電性連接該第一引腳。 为^ 結二^^22，項所述之具導線架之封裝 稱具中心腳與g亥第二引腳之端部相隔一間距。 ㉔構，更如細22項所述之具導線架之封裝 :: 冓。更包含-封膠，該封膠至少覆蓋該弯腳及該第f 結構3,2其如中%專—項所叙具_之封裝 ’、 引腳或^亥第一引腳由内而外形成： 的平:内密封於該封膠内’並與該ψ腳處於相同 該不:Z:或:::露於該封膠外，並與 j的十面，該外引腳用以電性連接一外 24 201103113 部裝置。 33.如申請專利範圍第32項所述之具導線架之封褒 結構，更包含一第二晶片，該第二晶片設置於該晶 、 該内引腳或該第一晶片上。 34. 如申請專利範圍第33項所述之具導線架之封裝 結構，其中該内引腳透過一銲線電性連接該第一晶片之 該弟#塾或§亥第一銲塾，並透過另一銲線電性連接夺 第二晶片之一第三銲塾。201103113 Qishen May patent scope: = package structure of the lead frame, which includes: less - the first group 'each leg group has a foot to the foot; and - the pin 'the first pin has a bend-weld to the first := Some: Feet:: Group: r plural number of fresh pads and at least - second soldering 塾; _ group corresponding to at least one first nearly 4: recording: the first pin is adjacent to the first zinc bismuth, the second lead The foot adjacent to the foot extends from the first leg to the continuation; ^塾. The end of the - square 'and electrically connected to the first soldering or the second broadcast 2 poor application of the lead frame of the lead frame package: the first pin of the pin group And the second pin is arranged in the row according to a row of 歹j: 晶二=周咖状, or an arrangement rule. The package is welded in the lead frame according to the item i of claim i. A lead wire electrically connected to the first pad or the package structure of the lead frame according to claim 3, wherein the bent leg is between the second pin and the second soldering pad Between the first pin and the bent leg through another bonding wire to electrically connect a pad or the second pad. 5. The package structure of the lead frame of claim 1, wherein the bent leg is electrically connected to the first pad or the first through a solder ball. — r 20 201103113 constituting the cover of the lead frame of the five items, and the bent foot facing the first pad or the second pad. Structure, 42: The package of the lead frame described in the fifth item is electrically connected to the first pin. And through the other item of the sphere structure range, the first part of the structure is labeled "the gap is separated from the end of the second pin by the spacing." 9. The structure of claim i, wherein the bent foot forms a shape of a l-shape, a S-sub-shape or a τ-shape with the first pin. The shape of the scorpion, H). The structure described in the scope of claim </ RTI> wherein the bent foot and at least two Ί are encapsulated in a shape of a chevron or a -F shape. 4 U-shaped, an E 11. As described in the scope of the patent application, and wherein: wherein the first bonding pad or the second bonding pad is soldered to a solder pad or a signal pad.罨源知 pads, one connection 12. If you apply for patent scope! The structure of the item, wherein the first pin or the second bow, the 褒 褒 - 接 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # , further comprising - sealing glue, the sealing glue to the sealing sheet. The singular side, the test foot and the first crystal H. as claimed in the thirteenth structure of the patent 'where the first pin or the second The pin is sealed by an inner pin, sealed in the sealant, and is formed into a plane, which is used to set the first, 曰, ...' feet on the same day Film, and 21 201103113 an external pin, its - Qiu Ba -, into A The internal chat is in a different two = = exposed outside the sealant, and the device. Ten external pins for electrical connection 1 15· If the structure of the patented scope is included, the cover of the second crystal lead frame or the first wafer is further included. The day 曰° is further placed in the inner lead structure 3::Special::·15 a first surface of the package with a lead frame, which is bonded to the first wafer; and a sheet. A second surface is opposite to the first surface and is used to set the second crystal. a 16th structure, wherein the first surface, the package of the V-ray frame of the first surface, the first π-ray wire is electrically connected to the first wafer or the second bonding pad, The second die of the second type of wafer, i-welding; = two balls = the distance between the first faces is 'the scale does not contact the second wafer. /, this first 18. as claimed in the thirteenth patent In the case of the item, the -5|foot or the second pin is formed from the inside out. 'Install the same 2 = in the Lai' and the material foot is in the second, the surface is 6 a pin is used to set the first chip; a second inner pin is sealed in the sealant; the foot is in a different plane; and the inner lead is: the outer lead, a part or all of which is exposed outside the sealant And electrically connected to an external device. The first wafer of the lead frame of the lead frame described in Item (4) and the second chip is disposed on the first inner 〇 22 201103113 pin, the second internal lead The package of the lead frame of claim 19, wherein the first inner lead has: = first side And the second surface is opposite to the first surface, and is configured to set the second surface. The second surface is electrically connected to the second wafer through a bonding wire. 21. The package junction pin 2 of the lead frame according to item (i) of claim 4 includes an adhesive layer, and the adhesive layer is attached to the package structure of the lead frame. The utility model comprises: a foot group Si frame Ϊ a chip holder and a plurality of pin groups, each---: a J-less first pin and at least a second pin, the first pin has a bent leg; The soldering chip holder has 'a plurality of first-first, one first one in the pad, the female one-pin group corresponding to at least one first-to-* and at least one second bonding pad; near the first pin adjacent to the first pin The first-pad's second lead (four) two-two: m first lead curved extension pad.彳的-方' electrically connected to the first-pad or the first: 槿2,3= Patent application (4) 22 with the lead frame seal! , &gt; ’ ’ 其中 该 该 该 该 该 该 该 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 方向 方向 4 方向 方向 4 4 方向 方向 方向 方向 方向 方向 方向 方向 方向. [24] The package of the lead frame 23 according to claim 22 [S 201103113, wherein the bending leg is between the wafer holder and the second pin 25. As described in claim 22 The lead wire is electrically connected to the first wire by the wire-welding wire. The structure is 26: L is the package of the lead frame according to item 25 of the patent application scope, m, 4 The first pin is connected to the bent leg through the other wire to connect the first pad or the second pad. Electricity 27. If the application of the patent scope # 22 workers described in the guide, the f-foot through the - fresh ball electrically connected to the first - fresh 塾 or; the furnace, please refer to the patent scope of the 27th item of the lead frame, ,. The bent leg faces the first pad or the second ridge. The name of the wire holder is as described in item 27 of the patent (4). A pad faces the first pin and is electrically connected to the first pin through another -2 ball. For the package of the lead frame described in the item, the center leg is spaced apart from the end of the second pin of the g-hai. 24, more like the package of the lead frame described in Item 22 :: 冓. Further comprising - a sealant, the sealant covering at least the bent leg and the f-th structure 3, 2 as shown in the % of the package - the package ', the pin or the first pin of the first step from the inside out Formed: flat: sealed inside the sealant' and in the same position as the foot: No: Z: or ::: exposed outside the sealant, and with the ten sides of j, the outer pin is used for electricity Sexual connection to an external 24 201103113 device. 33. The package structure of the lead frame of claim 32, further comprising a second wafer disposed on the crystal, the inner lead or the first wafer. 34. The package structure of the lead frame according to claim 33, wherein the inner lead is electrically connected to the first wafer of the first wafer through a bonding wire, and is transmitted through Another bonding wire is electrically connected to one of the third pads of the second wafer. 35. 如申請專利範圍第μ項所述之具導線架之封裝 結構，其中該第一引腳或該第二引腳由内而外形成： 一第一内引腳，密封於該封膠内，並與該彎腳處於 相同的平面； 一第二内引腳，密封於該封膠内，並與該第一内引 腳處於不同的平面；以及 外引腳，其一部分或全部顯露於該封膠外，並用 以電性連接一外部裝置。 6.如申請專利範圍第35項所述之具導線架之封 -，更包含一第二晶片，該第二晶片設置於該晶片座 該第-内引腳、該第二内引腳或該第一晶片上。 37·如巾請專利範圍第％項所述之具導線架之封 …構，其中該第一内引腳具有： ―自’透過一鲜球電性連接該第一晶片之該: 一銲墊或該第二銲墊；以及 第二面，相對於該第一面，並透過一銲線電性」 接該第二晶片之—第三銲墊。 2535. The package structure of the lead frame according to claim 19, wherein the first pin or the second pin is formed from the inside to the outside: a first inner pin sealed in the sealant And in the same plane as the bent foot; a second inner pin sealed in the sealant and in a different plane from the first inner lead; and an outer lead, a part or all of which is exposed In addition to the sealant, it is used to electrically connect an external device. 6. The package of lead frame according to claim 35, further comprising a second chip disposed on the first inner pin, the second inner pin or the wafer holder On the first wafer. 37. For example, the first inner lead has the following structure: The first inner lead has: ― self-connecting the first wafer through a fresh ball: a solder pad Or the second pad; and the second surface, relative to the first surface, and electrically connected to the third pad of the second wafer through a bonding wire. 25
TW98123493A 2009-07-10 2009-07-10 Package structure with lead frame TW201103113A (en)

Priority Applications (1)

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TW98123493A TW201103113A (en) 2009-07-10 2009-07-10 Package structure with lead frame

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI745516B (en) * 2017-04-27 2021-11-11 日商瑞薩電子股份有限公司 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI745516B (en) * 2017-04-27 2021-11-11 日商瑞薩電子股份有限公司 Semiconductor device and manufacturing method thereof

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