CN100426481C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN100426481C
CN100426481C CNB038249561A CN03824956A CN100426481C CN 100426481 C CN100426481 C CN 100426481C CN B038249561 A CNB038249561 A CN B038249561A CN 03824956 A CN03824956 A CN 03824956A CN 100426481 C CN100426481 C CN 100426481C
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pad
passivating film
semiconductor device
film
manufacture method
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CN1695239A (zh
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佐竹信夫
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Socionext Inc
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Abstract

一种制造半导体装置的方法，包括以下步骤：在绝缘膜(1)上形成多个焊盘(2)；在其整个表面上形成钝化膜(3)；在钝化膜(3)上形成露出所有焊盘(2)的开口部(3a)；在其整个表面上形成其他钝化膜，在该钝化膜上为每个焊盘(2)形成露出焊盘(2)的中央部的开口部。从而能够在钝化膜(3)上形成有开口部(3a)的状态下进行探测检查。当在该状态下进行探测检查时，由于焊盘(2)的整个面都露出，因此探针与焊盘(2)接触的概率升高，能够进行精确的检查。因此，可以进一步减小焊盘，或者使间距变窄，而不需要高精度的探针。

Description

半导体装置及其制造方法
技术领域
本发明涉及适用于焊盘被减小了的半导体装置及其制造方法。
背景技术
专利文献1：特开2003-068736号公报
以往，设置在半导体装置中的焊盘(Al电极)的尺寸随着其间隔(间距)变窄而被缩小。通常，在半导体装置中，形成有用以覆盖焊盘钝化膜，在该钝化膜上形成有露出各焊盘的一部分的开口部。
但是，在焊盘上形成凸起之前进行探测检查的半导体装置中，探测检查的条件(探针的精度等)依赖于形成有开口部以便露出焊盘的钝化膜的所述开口部的大小。例如，当焊盘的间距小于等于30μm时，在钝化膜上形成的开口部为边长为15μm左右的正方形形状。在此情况下，必须将在探测检查中使用的探针的尖端直径总是保持为小于等于10μm，但这种探针的成本极高，不适合批量生产。
并且，在保持高的定位精度的状态下，为了使探针的数量达到100～1000个左右，不得不降低探针的强度。这是因为，为了保持高的定位精度(在三个相互正交的方向上的精度)，要求小于等于亚微米(submicron)的精度。
由于这些情况，现状为，在焊盘被减小时，探测检查变得困难，探测检查的成本升高，在有多个焊盘在一个方向上并列排列的半导体装置中，尤其如此。
另一方面，即使在焊盘上形成了凸起后再进行探测检查的半导体装置中，为了进行探测检查，也要将正方形形状的焊盘的边长限制在20μm～30μm左右，将间距限制在30μm～40μm左右。另外，在这样的半导体装置中，在形成凸起之后的检查中即使发现了缺陷，也难以判断该缺陷是在凸起形成之前就存在的缺陷，还是在凸起形成时产生的缺陷。
发明内容
本发明是鉴于该问题而提出的，其目的在于提供一种即使减小了焊盘也能够在形成凸起之前很容易地进行探测检查的半导体装置及其制造方法。
本发明的发明者为解决上述问题，进行了认真细致的研究，结果设想了以下所示的本发明的各种实施方式。
本发明的半导体装置具有形成在半导体基板上的半导体元件、和与所述半导体元件连接的焊盘，并且用第1钝化膜覆盖形成有所述半导体元件的区域，露出所述焊盘的整个表面，其中，所述焊盘与所述第1钝化膜的开口部的缘部分离。
另外，在本发明的半导体装置的制造方法中，在半导体基板上形成半导体元件之后，形成与所述半导体元件连接的焊盘。然后，形成覆盖形成有所述半导体元件的区域的第1钝化膜，露出所述焊盘的整个表面，其中，所述焊盘与所述第1钝化膜的开口部的缘部分离。
根据本发明，由于焊盘的整个表面从第1钝化膜中露出，因此即使不使用精度极高的探针也能够在形成凸起之前进行探测检查。并且，在进行了探测检查之后，可以形成(例如)覆盖焊盘的一部分的第2钝化膜。
附图说明
图1A和图1B～图4A和图4B是按工序顺序来示出本发明的第1实施方式的半导体装置的制造方法的图。
图5A和图5B～图7A和图7B是按工序顺序来示出本发明的第2实施方式的半导体装置的制造方法的图。
图8是示出本发明的第3实施方式的半导体装置的制造方法的截面图。
图9A～图9F是按工序顺序示出形成凸起的方法的截面图。
具体实施方式
(第1实施方式)
首先对本发明的第1实施方式进行说明。其中，为了方便起见，这里对将半导体装置的结构和其制造方法一起进行说明。图1A和图1B～图4A和图4B是按照工序顺序示出本发明的第1实施方式的半导体装置的制造方法的图，图1A～图4A是俯视图，图1B～图4B是沿着图1A～图4A中的I-I线的截面图。
在第1实施方式中，如图1A和图1B所示，首先在半导体基板的上面形成晶体管等半导体元件(图中未示出)，然后形成覆盖该半导体元件的绝缘膜1。而且，在图1A和图1B～图4A和图4B中仅示出相当于一个LSI(Large Scale Integration，大规模集成电路)芯片的区域，但一个半导体基板(晶片)上可设置多个芯片形成预定区域，在各芯片形成预定区域内，划分出形成有所述半导体元件的内部元件区域11和输入输出区域12，输入输出区域12中设有用于在所述半导体元件和外部电源及电路等之间进行信号的输入输出的输入输出端子(凸起)。输入输出区域12例如被设置成将内部元件区域11夹在中间地在2个部位相互并行地延伸。
接着，在绝缘膜1上形成用于连接其后形成的输入输出端子和内部元件区域11内的半导体元件的触点插头(图中未示出)。然后，如图1A和图1B所示，在输入输出区域12内，在绝缘膜1的上面形成多个焊盘2、电源线(图中未示出)和引出布线(图中未示出)。焊盘2例如由Al制成。同时，焊盘2例如通过引出布线和电源线等与在绝缘膜1上形成的触点插头相连接。
之后，如图2A和图2B所示，在整个表面上形成钝化膜3，在钝化膜3上形成露出所有焊盘2的开口部3a。例如可以使用SiN膜作为钝化膜3，例如可以使用高密度等离子法作为形成该钝化膜的方法。开口部3a的平面形状例如是带状。这种状态下的半导体装置也可以进行转让、租赁等。
接着，如图3A和图3B所示，在整个表面上形成钝化膜4。例如可以使用SiN膜作为钝化膜4，可以使用(例如)高密度等离子法作为形成该钝化膜4方法。然后，在钝化膜4上为每个焊盘2都形成露出焊盘2的中央部的开口部4a。开口部4a的平面形状例如是正方形形状。
接着，如图4A和图4B所示，在每个焊盘2上形成凸起5。这样就完成了半导体装置。
在该第1实施方式中，在钝化膜3上形成有开口部3a的状态下，可以进行探测检查。当在该状态下进行探测检查时，因为焊盘2的整个表面都露出，所以探针与焊盘2接触的概率升高，可以进行精确的检查。因此，不需要探针的高精度，就可以进一步减小焊盘，或者使间隔变窄。
并且，通过在形成凸起5之前进行检查，可以确定在凸起5形成之前已经产生的缺陷。因此，还可以保证形成凸起5之前的半导体装置的可靠性为何种程度。即，即使在形成了凸起5后所进行的检查中发现了缺陷的情况下，也能够判别该缺陷是在凸起5形成前就存在的缺陷还是在凸起5形成时产生的缺陷。
并且，如上所述完成后的半导体装置，例如通过TAB(Tape AutomatedBonding：带自动化键合)接合到带载(tape carrier)上，或者应用到COF中(Chip On Film，薄膜上芯片)。
(第2实施方式)
接着说明本发明的第2实施方式。其中，为了方便起见，这里对半导体装置的结构和其制造方法一起进行说明。图5A和图5B～图7A和图7B是按照工序顺序示出本发明的第2实施方式的半导体装置的制造方法的图，图5A～图7A是俯视图，图5B～图7B是沿着5A～图7A中的I I-II线的截面图。并且，图5A和图5B～图7A和图7B中仅示出输入输出区域12。
如图5A和图5B所示，第2实施方式中，和第1实施方式一样地进行直到在绝缘膜1上形成触点插头(图中未示出)为止的处理。接着，在输入输出区域12内，在绝缘膜1上形成多个焊盘8、电源线6和引出布线7。
在本实施方式中，使焊盘8的平面形状为长方形形状，配置成其短边和焊盘8的排列方向平行。并且电源线6配置成向焊盘8的排列方向延伸，焊盘8和第1实施方式中一样，例如经由引出布线7和电源线6等与在绝缘膜1上形成的触点插头相连接。
接着，在整个表面上形成钝化膜3，在钝化膜3上形成露出所有焊盘2的开口部3a。该开口部3a的平面形状例如是带状。和第1实施方式一样，该状态下的半导体装置也可以进行转让、租赁等。
并且，在形成了开口部3a后，也可以进行探测检查。在进行探测检查时，例如，将探针按压在从焊盘8的中心起靠近电源线6侧的位置上。然后，进行探测检查。其结果，如图6A和图6B所示，在焊盘8上形成探针的痕迹9。
在进行了探测检查后，如图7A和图7B所示，在整个面上形成钝化膜4。然后，在钝化膜4上，对每个焊盘8形成露出从焊盘8的中心起远离电源线6的区域的开口部4a。开口部4a的平面形状，例如是正方形形状。其结果，探针的痕迹9被钝化膜4完全覆盖。
然后，和第1实施方式一样，在每个焊盘8上形成凸起(图中未示出)。这样就完成了半导体装置。
根据该第2实施方式，不仅可得到与第1实施方式一样的效果，还可以利用钝化膜4可靠地覆盖因按压探针所形成的痕迹9。因此，避免了在痕迹9上形成凸起。当在探针的痕迹9上形成凸起时，有时会使凸起会发生变形，或者TAB(Tape Automated Bonding)时的拉伸强度不够。对此，本实施方式中，如上所述，由于凸起没有形成在探针的痕迹9上，所以可以避免这种问题于未然。
(第3实施方式)
下面说明本发明的第3实施方式。其中，为了方便起见，在这里对半导体装置的结构和其制造方法一起进行说明。图8是示出本发明的第3实施方式的半导体装置的制造方法的截面图。并且，图8中只示出输入输出区域12。
如图8所示，在第3实施方式中，和第1实施方式一样地进行到在绝缘膜1上形成触点插头(图中未示出)为止的处理。接着，在输入输出区域12内，在绝缘膜1上形成多个焊盘10、电源线6和引出布线7。
在本实施方式中，使焊盘10的平面形状为正方形形状。并且，将电源线6配置成向焊盘10的排列方向延伸，焊盘10和第1实施方式一样，例如经由引出布线7和电源线6等与在绝缘膜1上形成的触点插头相连接。
接着，在整个表面上形成钝化膜3，在钝化膜3上形成露出所有焊盘2的开口部3a。该开口部3a的平面形状例如是带状。和第1实施方式一样，该状态下的半导体装置也可以进行转让和租赁等。
并且，在形成开口部3a后，也能够进行探测检查。在进行探测检查时，例如，将探针按压在沿焊盘10的排列方向与焊盘10的中心相偏离的位置。然后，进行探测检查。其结果，如图8所示，在焊盘8上形成探针的痕迹9。
在进行了探测检查后，和第1实施方式一样，在整个面上形成钝化膜(图中未示出)。接着，在钝化膜上为每个焊盘10形成露出从焊盘10的中心起偏离痕迹9的区域(开口部形成预定部21)的开口部(图中未示出)。开口部4a的平面形状例如是长方形形状。其结果，和第2实施方式一样，探针的痕迹9被钝化膜完全覆盖。
根据这种第3实施方式，可得到与第2实施方式一样的效果。
并且，可以通过层叠多个Al膜来形成焊盘、引出布线和电源线。例如在由3片Al膜形成焊盘的情况下，引出布线可以和构成焊盘的3片Al膜中的位于最下面的Al膜同时形成，电源线可以和构成焊盘的3片Al膜中的除位于最上面的Al膜之外的另外2片Al膜同时形成。
这里对形成凸起的方法进行说明。其中，这里，对形成图9A所示的结构后的工序进行说明。在图9A所示的状态下，在半导体基板(图中未示出)的表面等上形成有半导体元件(图中未示出)，在这些元件的上方，形成有埋入了阻挡层金属(barrier metal)膜52和钨插头53的SiN膜51。在SiN膜51上面层叠有阻挡层金属膜54、金属布线55和阻挡层金属膜56。在SiN膜51上还层叠有覆盖阻挡层金属膜54、金属布线55和阻挡层金属膜56的CVD绝缘膜57和SiN膜58。CVD绝缘膜57和SiN膜58中埋入有阻挡层金属膜59和钨插头60。SiN膜58上面层叠有阻挡层金属膜61、例如由AlCu合金形成的焊盘62和阻挡层金属膜63。SiN膜58上面还层叠有覆盖阻挡层金属膜61、焊盘62和阻挡层金属膜63的CVD绝缘膜64和SiN膜65。CVD绝缘膜57和64例如是高密度等离子氧化膜。并且，在SiN膜65上面有选择地形成多晶酰亚胺被覆膜66。在阻挡层金属膜63、CVD绝缘膜64和SiN膜65上形成有露出焊盘62的开口部。
在形成这样的结构后，如图9B所示，在整个表面上形成电镀电极用的阻挡层金属膜67。
接着，如图9C所示，形成覆盖多晶酰亚胺被覆膜66的抗蚀掩膜68。此时，在抗蚀掩膜68上形成整合在露出焊盘62的开口部的开口部。
接着，如图9D所示，在抗蚀掩膜68的开口部以及阻挡层金属膜63、CVD绝缘膜64和SiN膜65的开口部内利用电镀法形成凸起69。凸起69例如由Au制成。
之后，如图9E所示，除去抗蚀掩膜68。
然后，如图9F所示，除去露在凸起69之外的阻挡层金属膜67。
另外，也可以不形成多晶酰亚胺被覆膜66。并且，在图9A中，钨插头53和60位于形成有凸起69的区域的正下面，但是它们的形成位置并不因此受限。
如以上的详细说明，根据本发明，由于焊盘的整个表面从第1钝化膜露出，因此即使不采用精度极高的探针也能够在凸起形成前容易地进行探测检查。因此，能够保证凸起形成前的状态的可靠性。并且，即使在由于探测检查在凸起上形成探针的痕迹的情况下，如果采用其后形成的第2钝化膜将痕迹覆盖，也可以避免凸起变形和接合时的拉伸强度不够等问题。

Claims (19)

1.一种半导体装置，其特征在于，具有：
形成在半导体基板上的半导体元件；
与所述半导体元件连接的焊盘；
第1钝化膜，其覆盖形成有所述半导体元件的区域，露出所述焊盘的整个表面，其中，
所述焊盘与所述第1钝化膜的开口部的缘部分离。
2.根据权利要求1所述的半导体装置，其特征在于，具有第2钝化膜，所述第2钝化膜形成在所述第1钝化膜的上面，覆盖形成有所述半导体元件的区域和所述焊盘的缘部，露出所述焊盘的一部分。
3.根据权利要求2所述的半导体装置，其特征在于，
在所述焊盘上形成有探针的痕迹；
所述第2钝化膜覆盖所述痕迹。
4.根据权利要求3所述的半导体装置，其特征在于，
在一个方向上设置有多个所述焊盘；
所述焊盘的从所述第2钝化膜中露出的部分和所述痕迹排列在与所述焊盘的排列方向平行的方向上。
5.根据权利要求3所述的半导体装置，其特征在于，
所述焊盘在一个方向上设置有多个；
所述焊盘的从所述第2钝化膜中露出的部分和所述痕迹排列在与所述焊盘的排列方向正交的方向上。
6.根据权利要求5所述的半导体装置，其特征在于，所述焊盘的平面形状为向与所述焊盘的排列方向正交的方向延伸的长方形。
7.根据权利要求1所述的半导体装置，其特征在于，所述第1钝化膜是SiN膜。
8.根据权利要求2所述的半导体装置，其特征在于，所述第2钝化膜是SiN膜。
9.根据权利要求1所述的半导体装置，其特征在于，
从在所述第1钝化膜上形成的1个开口部中分别露出多个所述焊盘的整个表面。
10.一种半导体装置的制造方法，其特征在于，具有下列工序：
在半导体基板上形成半导体元件的工序；
形成与所述半导体元件连接的焊盘的工序；
形成覆盖形成有所述半导体元件的区域的第1钝化膜，露出所述焊盘的整个表面的工序，其中，
所述焊盘与所述第1钝化膜的开口部的缘部分离。
11.根据权利要求10所述的半导体装置的制造方法，其特征在于，形成所述第1钝化膜的工序包括：
形成覆盖形成有所述半导体元件的区域和所述焊盘的第1膜的工序；
在所述第1膜上形成露出所述焊盘的整个表面的开口部的工序。
12.根据权利要求10所述的半导体装置的制造方法，其特征在于，具有在所述第1钝化膜的上面形成覆盖形成有所述半导体元件的区域和所述焊盘的缘部的第2钝化膜、使所述焊盘的一部分露出的工序。
13.根据权利要求12所述的半导体装置的制造方法，其特征在于，
形成所述第2钝化膜的工序包括：
形成覆盖形成有所述半导体元件的区域和所述焊盘的第2膜的工序；
在所述第2膜上形成露出所述焊盘的一部分的开口部的工序。
14.根据权利要求12所述的半导体装置的制造方法，其特征在于，当在所述焊盘上形成有探针的痕迹时，所形成的所述第2钝化膜覆盖所述痕迹。
15.根据权利要求14所述的半导体装置的制造方法，其特征在于，
在一个方向上并列形成多个所述焊盘；
形成所述第2钝化膜，使得所述焊盘的从所述第2钝化膜露出的部分和所述痕迹排列在与所述焊盘的排列方向平行的方向上。
16.根据权利要求14所述的半导体装置的制造方法，其特征在于，
在一个方向上并列形成多个所述焊盘；
形成所述第2钝化膜，使得所述焊盘的从所述第2钝化膜露出的部分和所述痕迹排列在与所述焊盘的排列方向正交的方向上。
17.根据权利要求16所述的半导体装置的制造方法，其特征在于，使所述焊盘的平面形状为向与所述焊盘的排列方向正交的方向延伸的长方形。
18.根据权利要求10所述的半导体装置的制造方法，其特征在于，形成SiN膜作为所述第1钝化膜。
19.根据权利要求12所述的半导体装置的制造方法，其特征在于，形成SiN膜作为所述第2钝化膜。
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US8735275B2 (en) 2014-05-27
US9331035B2 (en) 2016-05-03
JP4213672B2 (ja) 2009-01-21
US20050179114A1 (en) 2005-08-18
US20140042613A1 (en) 2014-02-13
WO2004093184A1 (ja) 2004-10-28

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