CN1643684A - 具有接合焊盘的半导体器件及其制造方法 - Google Patents

具有接合焊盘的半导体器件及其制造方法 Download PDF

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CN1643684A
CN1643684A CNA038057700A CN03805770A CN1643684A CN 1643684 A CN1643684 A CN 1643684A CN A038057700 A CNA038057700 A CN A038057700A CN 03805770 A CN03805770 A CN 03805770A CN 1643684 A CN1643684 A CN 1643684A
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pad
district
bond
bond pad
layer
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CN100435327C (zh
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罗伊斯·E.·永
彼德·R.·哈帕
涂安·特朗
杰弗利·W.·玫兹
乔治·R.·里尔
迪乌·V.·迪恩
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SK Hynix Inc
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Freescale Semiconductor Inc
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Abstract

一种接合焊盘(10)具有基本上不重叠的探测区(14)和引线接合区(12)。在一个实施例中，接合焊盘(10)连接于最末金属层焊盘(16)，且在互连区(24)上方延伸。接合焊盘(10)由铝制成，最末金属层焊盘(16)由铜制成。探测区(14)与引线接合区(12)分离，避免了最末金属层焊盘(16)被探针测试损坏，从而实现更可靠的引线接合。在另一实施例中，探测区(14)在钝化层(18)上方延伸。在接合焊盘之间要求非常细的节距的应用中，形成为一条线的多个接合焊盘的探测区(14)和引线接合区(12)可以交错排布，以增加探测区(14)之间的距离。此外，在互连区(24)上方形成接合焊盘(10)，减小了集成电路的尺寸。

Description

具有接合焊盘的半导体器件 及其制造方法
技术领域
本发明涉及半导体器件，尤其涉及一种具有用于探针和引线接合隔离的接合焊盘的半导体器件及其制造方法。
背景技术
在集成电路的制造中，引线接合是一种经过验证的用于使具有电路的半导体芯片连接于元件封装上的引脚的方法。在集成电路制造中，在完成元件组装之前，测试半导体芯片的功能是一种惯例。“探针测试”是一种用于测试半导体的方法，其中探针触点通常用作芯片上的接合焊盘的机械和电学界面。
使用机械界面，例如探针的一个问题，是当芯片引线接合后，接合焊盘可能损坏或污染，妨碍接合焊盘和封装引脚之间可靠的电连接。现代的深亚微米半导体技术中接合焊盘的几何尺寸特征减小使这一问题变得更糟。减小接合焊盘的几何尺寸包括其上形成更小的引线接合的更小的接合焊盘。这增加了对被探针触点损坏的接合焊盘的质量和可靠性的关注。随着接合焊盘的尺寸的减小，探针触点对接合焊盘区造成的损坏比例增加。接合焊盘尺寸缩小的另一个问题是对于使用常规方法，比如悬臂探针的强探针测试来说接合焊盘之间的间隔可能太小。
因此，需要以下能力：探针测试芯片，而不会导致不可靠的引线接合连接，并确保在具有小型接合焊盘和接合焊盘的细节距间隔的芯片上进行强探针测试。并且在很多情况下，需要满足以前的标准，且不会显著影响芯片的尺寸，以使成本下降。
附图说明
图1示出了本发明的引线接合焊盘的顶视图。
图2示出了本发明的具有图1的引线接合焊盘的半导体器件剖面图。
图3示出了本发明另一实施例的半导体器件剖面图。
图4示出了本发明另一实施例的半导体器件剖面图。
图5至14示出了本发明的具有多个引线接合焊盘的集成电路的另外实施例的顶视图。
具体实施方式
一般而言，本发明提供了一种具有多个接合焊盘的集成电路。所述多个接合焊盘都具有基本上不重叠而相邻的探测区和引线接合区。在一个实施例中，接合焊盘在集成电路的有源电路和/或电互连层上延伸。接合焊盘的一部分或全部在所述互连层上方延伸，且所述焊盘的一部分可以在钝化层上方形成且连接于最末金属层焊盘。在一个实施例中，接合焊盘由铝制成，且最末金属层焊盘由铜制成。
将探测区与引线接合区分开，且在有源电路上方形成接合焊盘具有几个优点。在要求接合焊盘之间有非常细的节距的应用中，探测区和引线接合区可以交错，以有效地增加探测区之间的距离。通过使探测区与引线接合区分开，引线接合区不会被探针测试损坏，实现更可靠的引线接合。而且，在包括金属互连层的有源电路上方形成接合焊盘，可以使集成电路更小。
图1示出了本发明的接合焊盘10的顶视图。接合焊盘10分成引线接合区12和探测区14，如虚线所示。引线接合区12和探测区14根据需求排布和确定尺寸，以适应引线接合和探测工具的尺寸和精度。在所示实施例中，引线接合区12示为小于探测区14。在其他实施例中，所述区域可以尺寸不同。
接合焊盘10在具有图2、图3和图4所示剖面图的不同半导体器件中设计。应指出的是，在所有附图中，类似或相同的元件赋予相同的附图标记。而且应指出的是所述附图不是按比例绘出的。图2示出了本发明的半导体器件20的剖面图。半导体器件20具有边缘或周边25，钝化层18，接合焊盘10，互连区24和有源区或衬底26。接合焊盘10具有引线接合区12和探测区14(参见图1)，且相对于周边25定位。互连区24包括金属层28，30，和32，用于在半导体器件20的各元件之间排布电源线、地线、信号线及其他线。如图2所示，金属层28，下文中称为最末金属层28靠近包括接合焊盘10的半导体器件20的表面定位，其中探测和引线结合区用于与半导体器件20外的器件(未示出)形成连接。互连区24的金属层可以使用通孔互相连接。互连金属层32电连接于具有接触的有源区26。
半导体器件20承受常规的制造技术，在有源区26，或衬底上形成电路。所述电路可以用于各种集成电路应用，比如，通信、传输、通用计算，或娱乐。在所示实施例中，金属层28，30，和32由导体材料制成，例如，铝、铜、或金。在其他实施例中，可以有更多或更少的金属层。接合焊盘10成为最末金属层28的一部分。金属层28形成后，在半导体器件的表面上淀积钝化层18。在钝化层18中形成开口，比如所示的在接合焊盘10上，使得可以比如在半导体器件20和封装的引脚之间实现电接触。
接合焊盘10由相对较厚的铜层制成。在一个实施例中，铜可以为0.3到1.0微米厚。测试表明接合焊盘10的强度足以承受引线接合工具的冲击，且可以在互连层24上方形成，而不会损坏互连层24和任何下面的有源区26的电路，如图2所示。
图3示出了本发明的半导体器件34的剖面图。半导体器件34具有边缘或周边25，钝化层18，互连区24和有源区或衬底26，接合焊盘36。接合焊盘36包括最末金属层焊盘16和铝焊盘层35。铝焊盘层35包括引线接合区38和探测区37。铝焊盘层35的厚度可以在约0.5至2.0微米之间。接合焊盘36相对于半导体器件34周边25定位，通过阻挡层22与最末金属层焊盘16分开。为容纳探测区37和引线接合区38，接合焊盘36进行布局和确定尺寸。
半导体器件34承受如针对图2的半导体器件20所述的常规制造技术和材料。此外，阻挡层22在钝化层18上方形成，而在最末金属层16和接合焊盘36之间，以及在接合焊盘36和钝化层18之间形成扩散阻挡和粘结层。在淀积了阻挡层22之后，在阻挡层22上淀积铝焊盘层35。然后阻挡层22和铝焊盘层35形成图案，从而形成探测和引线接合区所需的最终形状和尺寸。在所述实施例中，铝焊盘层35由铝形成，但在其他实施例中，铝焊盘层35可以由其他导电材料形成。而且，互连区24的金属层28，30，和32，以及最末金属层焊盘16由铜制成。在其他实施例中，其他导电材料可以用于接合焊盘36，最末金属层焊盘16，和金属层28，30，和32。例如，金属层28，30，和32和最末金属层焊盘16可以由铝或金制成，且最末金属层焊盘16可包括金。而且，在所示的实施例中阻挡层22由钽制成。但在其他实施例中，阻挡层22可以是任何材料，用于在不同的和相邻的材料之间形成扩散阻挡和粘结层。扩散层和粘结层材料的示例是氮化钽，钛，氮化钛，镍，钨，钛钨合金和氮化硅钽。
接合焊盘36的铝层焊盘35和最末金属层焊盘16分别由较厚的铝和铜层形成。因此，接合焊盘36的强度足以承受引线接合工具的冲击，并且可以在互连层24上形成，而不会损坏互连层24和任何下面有源区26的电路，如图3所示。
图4示出了本发明另一实施例的半导体器件40的剖面图。半导体器件49具有边缘或周边25，钝化层18，互连区24、有源区26，接合焊盘44。接合焊盘44包括铝焊盘45和最末金属焊盘42。最末金属焊盘42成为最末金属层28的一部分。接合焊盘44相对于半导体器件40周边25定位，分成探测区和引线接合区，如图4所示被竖直虚线分开。铝焊盘45通过阻挡层43与最末金属层焊盘42分离。
半导体器件40承受如图2和图3所述的常规制造技术和材料。然而，在图4的器件中，接合焊盘44的一部分在钝化层18及下面的有源电路26和/或互连区24上方延伸，其余部分在钝化层18的开口处连接于最末金属层焊盘42。如上所述，接合焊盘44分成引线接合区和探测区。探测区位于接合焊盘10的延伸到钝化层18上且在互连区24的电互连层28，30，和32上方的部分上。引线接合区在接合焊盘44的连接于最末金属层焊盘42的部分上形成。所述引线接合区的强度足以承受引线接合工具的冲击，而不会损坏下面的电路或使其变形，并且可以在互连区24的金属层上形成。
通过使探测区在钝化层18上方延伸，最末金属层焊盘42的尺寸不受影响，而接合焊盘44的尺寸可以增加，且不会增加半导体器件的整体尺寸。而且，因为最末金属层焊盘42不用于探针测试或引线接合，所以最末金属层焊盘42的尺寸和形状，以及钝化层18上的开口形状和尺寸仅受接合焊盘44电连接所需面积的限制。在其他实施例中，可以有多个较小的最末金属层焊盘和相应的钝化开口，它们一起为接合焊盘44提供足够的电连接。因为接合焊盘44在钝化层18上方延伸，且最末金属层焊盘42的尺寸不受影响，所以在排布探测区和引线接合区上有更大的柔性。例如，在其他实施例中，探测区和引线接合区可以不相邻。
接合焊盘44可以由铝制成，最末金属层焊盘42可以由铜制成。除了为实现更可靠的引线接合、使探测区与引线接合区分离之外，在钝化层18上探测消除了无意中使最末金属层焊盘42的铜暴露的危险。暴露的铜容易氧化，产生引线接合不可靠的表面。
图5示出了本发明一个实施例的半导体器件60的顶视图。集成电路60包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图2或图3所示的实施例构造。集成电路60包括多个接合焊盘62至65，它们沿集成电路60的边缘61形成。每一所述多个接合焊盘的虚线示出了在钝化层上形成的开口66。每个接合焊盘分成如图1所示的探测区和引线接合区。每个接合焊盘上椭圆围绕的区域是通常定为用于探针测试的区域，而每个接合焊盘上圆围绕的区域是通常定为用于引线接合的区域。所述多个接合焊盘相对于周边61定位。引线接合区比每个焊盘探测区更接近周边61。相邻接合焊盘的引线接合区保持在离边缘61等距离的一条线上。类似地，相邻接合焊盘的探测区保持在离边缘61等距离的一条线上。在其他实施例中，探测区和引线接合区可以互换。
图6示出了本发明另一实施例的半导体器件70的顶视图。集成电路70包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图4所示的实施例构造。集成电路70包括多个接合焊盘72至75，它们沿集成电路70的边缘71形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口76。每个焊盘分成如图1所示的探测区和引线接合区。每个接合焊盘上椭圆围绕的区域是通常定为用于探针测试的区域，而每个接合焊盘上圆围绕的区域是通常定为用于引线接合的区域。所述多个接合焊盘相对于周边71定位。每个接合焊盘的引线接合区比探测区更接近周边71。相邻接合焊盘的引线接合区保持在离边缘71等距离的一条线上。类似地，相邻接合焊盘的探测区保持在离边缘71等距离的一条线上。在其他实施例中，探测区和引线接合区可以互换。
接合焊盘72至75的一部分在钝化层上方形成，所述接合焊盘的一部分在最末金属层焊盘上方形成，如图4所示。
图7示出了本发明另一实施例的半导体器件80的顶视图。集成电路80包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图2或3所示的实施例构造。集成电路80包括多个接合焊盘82至85，它们沿集成电路80的边缘81形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口86。每个焊盘分成如图1所示的探测区和引线接合区。每个接合焊盘上椭圆围绕的区域是通常定为用于探针测试的区域，而每个接合焊盘是圆围绕的区域是通常定为用于引线接合的区域。所述多个接合焊盘通常具有相同的尺寸，且通常相对于周边81以相同的距离排布。
探测区(用椭圆示出)以交错的、交替的形式在引线接合区(圆)的相对侧上形成，而引线接合区保持在离集成电路80的边缘81等距离的一条线上。而且，每个接合焊盘的中心保持在离边缘81等距离的一条线上。基本上所有的接合焊盘82至85在最末金属层焊盘上方形成，如图3所示
通过交错或交替排布探测区，增加了探测区之间的距离，可以允许非常细节距的器件进行更强的探针测试，以及使用多种探针技术的柔性，比如，悬臂和竖直探针技术。目前的探针技术不能支持低于特定最小节距的焊盘节距，在此节距指的是焊盘之间的距离。通过使接合焊盘细长且使探测区交错，目前的探针技术可以扩展到具有较小节距的焊盘。使引线接合区保持在一条线上，可以使引线接合设备的编程更简单。应指出的是，在其他实施例中，探测区和引线接合区可以互换。
图8示出了本发明另一实施例的半导体器件90的顶视图。集成电路90包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图4所示的实施例构造。集成电路90包括多个接合焊盘92至95，它们沿集成电路90的边缘91形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口96。
除了钝化层上的开口96较小，且仅围绕用圆示出的每个引线接合区之外，图8的接合焊盘布局与图7的接合焊盘布局相同。探测区用椭圆示出，且如图7所述交错放置。而且，探测区在半导体器件90的钝化层上方延伸。
图9示出了本发明另一实施例的半导体器件100的顶视图。集成电路100包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图2或3所示的实施例构造。集成电路100包括多个接合焊盘102至105，它们沿集成电路100的边缘101形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口106。
钝化层上的开口106围绕每个接合焊盘102-105的引线接合区(圆)和探测区(椭圆)。接合焊盘以交错的方式排布，其中接合焊盘102和104比接合焊盘103和105更远离周边101。而且，每个接合焊盘的探测区如图7和图8所述交错。此外，每个焊盘的引线接合区以离周边101相等的距离排布。
图9的接合焊盘比图8的接合焊盘短，因为已经去除了不用于探针测试或引线接合的区域。接合焊盘的去除部分所提供的空间可以在半导体器件的表面上提供更大的表面积，用于集成电路上更多的部件或接合焊盘。
图10示出了本发明另一实施例的半导体器件110的顶视图。集成电路110包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图4所示的实施例构造。集成电路110包括多个接合焊盘112至115，它们沿集成电路110的边缘111形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口116。
接合焊盘112至115以交错的方式排布，其中接合焊盘112和114比接合焊盘113和115更远离周边111。而且，每个接合焊盘的探测区如上面针对图7、图8和图9的描述交错排布。而且，每个焊盘的引线接合区以离周边111相等的距离排布。
钝化层上的开口116较小，且仅围绕用圆示出的每个引线接合区。探测区在半导体器件110的钝化层上方延伸。
图11示出了本发明另一实施例的半导体器件120的顶视图。集成电路120包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图2或3所示的实施例构造。集成电路120包括多个接合焊盘122-125，它们沿集成电路120的边缘121形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口126。每个焊盘分成如图1所示的探测区和引线接合区。每个接合焊盘上椭圆围绕的区域是通常定为用于探针测试的区域，而每个接合焊盘上由圆围绕的区域是通常定为用于引线接合的区域。多个接合焊盘相对于周边121定位。在图11所示的实施例中，探测区和引线接合区都交错放置。
图12示出了本发明另一实施例的半导体器件130的顶视图。集成电路130包括类似于图1所示的多个接合焊盘，并可根据图4所示的实施例构造。集成电路130包括多个接合焊盘132-135，它们沿集成电路130的边缘131形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口136。每个焊盘分成如图1所示的探测区和引线接合区。每个接合焊盘上椭圆围绕的区域是通常定为用于探针测试的区域，而每个接合焊盘上圆围绕的区域是通常定为用于引线接合的区域。所述多个接合焊盘相对于周边131定位。在图12所示的实施例中，探测区和引线接合区都交错放置。而且，探测区在钝化层上方形成。
图13示出了本发明另一实施例的半导体器件140的顶视图。集成电路140包括类似于图1所示的接合焊盘的多个接合焊盘，且可以根据图2和3所示的实施例构造。集成电路140包括多个接合焊盘142至145，它们沿所述集成电路140的边缘141形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口146。每个接合焊盘上椭圆围绕的区域上通常定为用于探针测试的区域，而每个接合焊盘上圆围绕的区域是通常定为用于引线接合的区域。所述接合焊盘的长轴平行于边缘141，相邻接合焊盘的探测区和引线接合区保持在离边缘141等距离的一条线上。因为接合焊盘的长轴与边缘141平行，所以接合焊盘的整体高度减小了，同时对于焊盘不受限的集成电路来说，保持了分离的引线接合区和探测区。
图14示出了本发明另一实施例的半导体器件150的顶视图。集成电路150包括类似于图1所示的接合焊盘的多个接合焊盘，并且可以根据图4所示的实施例构造。集成电路150包括多个接合焊盘152至155，它们沿所述集成电路150的边缘151形成。每一所述多个接合焊盘上的虚线指示了在钝化层上形成的开口156。每个接合焊盘上椭圆围绕的区域是通常定为用于探针测试的区域，而每个接合焊盘上圆围绕的区域是通常定为用于引线接合的区域。所述接合焊盘的长轴与边缘151平行，相邻接合焊盘的探测区和引线接合区保持在离边缘151等距离的一条线上。因为接合焊盘的长轴与边缘151平行，所以接合焊盘的整体高度降低了，同时对于焊盘不受限的集成电路来说，保持了分离的引线接合区和探测区。在图14中，探测区在钝化层上方形成。
在前述的说明书中，已经参照具体实施例描述了本发明。然而，本领域的普通技术人员将理解，可以作出多种修改和变化，而不脱离下面的权利要求中所述的本发明的范围。因此，所述说明书和附图被认为是示例性的，而不是限制性的，并且所有这些修改被认为包括在本发明的范围内。
上面已经参照具体的实施例描述了益处，其他优点和问题的解决方案。然而，所述益处、其他优点、问题的解决方案，和能够使任何益处、其他优点和问题的解决方案出现或变得更为明显的任何要素，都不解释为任一或全部权利要求的关键的、必须的或主要的特征或要素。如同在此使用的，术语“包含”、“包含有”或其任何其他变体，旨在覆盖非排它性的包含内容，所以包含一列要素的工艺、方法、物品或设备不仅包括这些要素，而且可包含未明确列出的其他要素或与这些工艺、方法、物品或设备与之俱来的要素。

Claims (10)

1.一种集成电路，包含：
具有有源电路和周边的衬底；
在所述衬底上方的第一多个互连层；
在所述第一多个互连层上方的多个最末层焊盘；
具有对应于所述最末层焊盘的多个开口的钝化层；以及
多个接合焊盘，通过所述开口与所述最末层焊盘连接，具有在所述开口上方的第一部分和在所述钝化层上方的第二部分，其中，第二部分的面积大于第一部分。
2.如权利要求1所述的集成电路，其特征在于：所述多个接合焊盘都具有第一和第二区，其中所述第一和第二区之一用于接收探针，所述第一和第二区的另一个用于接收引线接合，其中所述第一和第二区基本上不重叠。
3.如权利要求2所述的集成电路，其特征在于：所述第一区比第二区更靠近所述衬底的周边，且所述多个接合焊盘的第一接合焊盘和第二接合焊盘互相接近，且所述第一焊盘的第一区和所述第二焊盘的第二区用于接收所述探针。
4.如权利要求1所述的集成电路，其特征在于：所述多个接合焊盘在所述有源电路上方延伸，且所述第二部分明显大于所述第一部分。
5.一种制造集成电路的方法，包含：
提供具有有源电路的衬底；
在所述衬底上方形成多个互连层；
在具有围绕所述衬底的周边的多个最末层焊盘且具有多个互连线路的所述多个互连层上，形成最末互连层；
在最末互连层上方形成具有多个开口的钝化层，其中所述多个开口分别对应所述多个最末层焊盘的最末层焊盘，且所述多个开口每个都在与其对应的所述最末层焊盘上方；以及
形成通过所述开口连接于所述最末层焊盘的多个接合焊盘，其中所述多个接合焊盘的每一接合焊盘：
对应于所述多个开口的一开口；
具有在与其对应的所述开口上方的第一部分和在所述钝化层上方的第二部分，其中所述第二部分的面积大于第一部分；具有基本上不重叠的第一区和第二区，其中每个接合焊盘的所述第一区比每个接合焊盘的所述第二区更靠近所述衬底的周边，其中相邻接合焊盘的第一区在探测区和引线接合区之间交替。
6.一种集成电路，包含：
具有有源电路和周边的衬底；
在所述衬底上方的多个互连层，所述多个互连层具有最末互连层；
在所述最末互连层上方形成的多个接合焊盘，其中每一所述多个接合焊盘都具有第一区和第二区，所述第一区仅用作探测区，所述第二区仅用作引线接合区，且其中所述多个互连层和有源电路位于所述多个接合焊盘下面；以及
在所述最末互连层上方形成的、具有多个开口的钝化层，每一所述多个开口对应于所述多个接合焊盘之一。
7.如权利要求6所述的集成电路，其特征在于：所述多个接合焊盘沿所述周边形成为一条线，且每一所述接合焊盘的第二区比每一所述接合焊盘的第一区更接近所述衬底的周边。
8.如权利要求6所述的集成电路，其特征在于：所述多个接合焊盘沿所述周边形成为一条线，且相邻接合焊盘的第二区离所述周边的距离基本上相等，且相邻接合焊盘的第一区从所述第二区的较靠近所述周边的一侧到所述第二区的较远离所述周边的另一侧交替。
9.如权利要求6所述的集成电路，其特征在于：所述多个接合焊盘沿所述周边形成为一条线，且所述多个接合焊盘的奇数接合焊盘的所述第一区位于离所述周边第一距离的位置，所述多个接合焊盘的偶数接合焊盘的所述第一区位于离所述周边第二距离的位置，所述第一距离比所述第二距离更远离所述周边。
10.如权利要求9所述的集成电路，其特征在于：所述奇数接合焊盘的所述第二区位于离所述周边第二距离的位置，所述偶数接合焊盘的所述第一区位于离所述周边第一距离的位置。
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