US20150262902A1 - Integrated circuits protected by substrates with cavities, and methods of manufacture - Google Patents

Integrated circuits protected by substrates with cavities, and methods of manufacture Download PDF

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Publication number
US20150262902A1
US20150262902A1 US14/214,365 US201414214365A US2015262902A1 US 20150262902 A1 US20150262902 A1 US 20150262902A1 US 201414214365 A US201414214365 A US 201414214365A US 2015262902 A1 US2015262902 A1 US 2015262902A1
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Prior art keywords
substrate
die
cavity
manufacture
dies
Prior art date
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Abandoned
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US14/214,365
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English (en)
Inventor
Hong Shen
Charles G. Woychik
Arkalgud R. Sitaram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Technologies LLC
Original Assignee
Invensas LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to US14/214,365 priority Critical patent/US20150262902A1/en
Application filed by Invensas LLC filed Critical Invensas LLC
Assigned to INVENSAS CORPORATION reassignment INVENSAS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARKALGUD, SITARAM R., SHEN, HONG, WOYCHIK, CHARLES G.
Priority to US14/288,064 priority patent/US9355997B2/en
Priority to KR1020167028245A priority patent/KR20160132093A/ko
Priority to PCT/US2015/019609 priority patent/WO2015138393A1/en
Priority to TW104107704A priority patent/TWI573223B/zh
Publication of US20150262902A1 publication Critical patent/US20150262902A1/en
Priority to US15/165,837 priority patent/US9887166B2/en
Priority to US15/265,148 priority patent/US9899281B2/en
Assigned to ROYAL BANK OF CANADA, AS COLLATERAL AGENT reassignment ROYAL BANK OF CANADA, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DIGITALOPTICS CORPORATION, DigitalOptics Corporation MEMS, DTS, INC., DTS, LLC, IBIQUITY DIGITAL CORPORATION, INVENSAS CORPORATION, PHORUS, INC., TESSERA ADVANCED TECHNOLOGIES, INC., TESSERA, INC., ZIPTRONIX, INC.
Priority to US15/865,842 priority patent/US10446456B2/en
Priority to US16/599,683 priority patent/US11205600B2/en
Assigned to INVENSAS CORPORATION, TESSERA, INC., FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS), INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.), PHORUS, INC., DTS, INC., DTS LLC, TESSERA ADVANCED TECHNOLOGIES, INC, IBIQUITY DIGITAL CORPORATION reassignment INVENSAS CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: ROYAL BANK OF CANADA
Abandoned legal-status Critical Current

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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This document relates to integrated circuits, and more particularly to assemblies having dies that include semiconductor integrated circuits.
  • one or more circuits are manufactured in a semiconductor wafer and are then separated into “dies” (also called “chips”) in a process called “singulation” or “dicing”.
  • the dies such as shown at 110 in FIG. 1 , are attached to a wiring substrate (“WS”, e.g. printed wiring board) 120 which has conductive lines 130 connecting the dies to each other and to other elements of the system. More particularly, the dies have contact pads 110 C connected to the dies' circuits (not shown), and these contact pads are attached to contact pads 120 C of WS 120 .
  • Pads 120 C are interconnected by conductive lines 130 .
  • connections 140 which may include solder, conductive epoxy, or other types.
  • Encapsulant 150 (e.g. epoxy with silica or other particles) protects the dies 110 and the connections 140 from moisture and other contaminants, ultraviolet light, alpha particles, and possibly other harmful elements.
  • the encapsulant also strengthens the die-to-WS attachment against mechanical stresses, and helps conduct heat away from the dies (to an optional heat sink 160 or directly to the ambient (e.g. air)).
  • the dies are protected by an additional, protective substrate attached to a wiring substrate.
  • the dies are located in cavities in the protective substrate (the dies may protrude out of the cavities).
  • the protective substrate may be similar to cap wafers used to protect MEMS components (Micro-Electro-Mechanical Structures); see K. Zoschke et al., “Hermetic Wafer Level Packaging of MEMS Components Using Through Silicon Via and Wafer to Wafer Bonding Technologies” (2013 Electronic Components & Technology Conference, IEEE, pages 1500-1507); see also U.S. Pat. No. 6,958,285 issued Oct. 25, 2005 to Siniaguine.
  • the protective substrate puts pressure on the die (e.g.
  • each die may physically contact the cavity surface) to strengthen the die-to-WS 120 mechanical attachment, to provide good thermal conductivity between the die and the protective substrate, to help flatten the die if it is warped, and to reduce the vertical dimension.
  • the protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate.
  • the die does not contact the cavity surface, but the die is separated from the cavity surface by solid material (e.g. a bonding layer) which physically contacts the die and the cavity surface.
  • the die or the solid material physically contacts the cavity surface at some but not all operating temperatures (e.g. the physical contact may exist only at higher temperatures at which the die expands).
  • An operating temperature is a temperature at which electrically functionality can be obtained.
  • the cavity contains a stack of dies, and the top die in a stack contacts the cavity surface (or a solid material overlying the top die physically contacts the cavity surface). In some embodiments, the entire top surface of each die, or the top die in the stack if there is a stack, physically contacts the cavity surface. In some embodiments, the protective substrate puts downward pressure on the dies in each cavity to strengthen the dies' attachment to the wiring substrate and to counteract the die warpage.
  • the wiring substrate is an interposer.
  • Interposers are commonly used as intermediate substrates to accommodate a mismatch between die fabrication technology and printed wiring substrates (PWSs). More particularly, the die's contact pads 110 C can be placed much closer to each other (at a smaller pitch) than PWS pads 120 C. Therefore ( FIG. 2 ), an intermediate substrate 120 . 1 can be used between the dies 120 and the PWS (shown at 120 . 2 ).
  • Interposer 120 . 1 includes a substrate 120 . 1 S (e.g. semiconductor or other material), a redistribution layer (RDL) 210 .T on top of substrate 120 . 1 S, and another redistribution layer 210 .B on the bottom of substrate 120 . 1 S.
  • RDL redistribution layer
  • Each RDL 210 .T, 210 .B includes interconnect lines 216 insulated from each other and from substrate 120 . 1 S by the RDL's dielectric 220 .
  • Lines 216 are connected to contact pads 120 . 1 C.T on top of the interposer and contact pads 120 . 1 C.B on the bottom.
  • Lines 216 of RDL 210 .T are connected to lines 216 of RDL 210 .B by conductive (e.g. metallized) through-vias 224 .
  • Pads 120 . 1 C.T are attached to the dies' pads 110 C by connections 140 . 1 as in FIG. 1 .
  • Pads 120 . 1 C.B are attached to pads 120 . 2 C of PWS 120 . 2 with connections 140 . 2 .
  • Pads 120 . 1 C.B are at a larger pitch than pads 120 . 1 C.T, to accommodate the pitch of the PWS contacts 120 . 2 C.
  • the interposer substrate 120 . 1 S should be as thin as possible to shorten the signal paths between dies 110 and PWS 120 . 2 and thus make the system faster and less power hungry. Also, if the interposer is thin, fabrication of metallized vias 224 is facilitated. However, thin interposers are hard to handle: they are brittle, easily warped, and do not absorb or dissipate heat during fabrication. Therefore, a typical fabrication process (such as described in Zoschke et al. cited above) attaches the interposer to a temporary substrate (“support wafer”) during fabrication. The support wafer is later removed. Attaching and detaching temporary support wafers is burdensome. The process of the aforementioned U.S. Pat. No. 6,958,285 does not use the support wafer. Neither some of the novel processes described below.
  • FIGS. 1 and 2 illustrate vertical cross-sections of assemblies including integrated circuits and constructed according to prior art.
  • FIGS. 3A , 3 B, 3 C, 3 D, 3 E, 4 A, 4 B, 4 C, 5 A, 5 B, 5 C, 5 D, 5 E. 1 , 6 , 7 , 8 A, 8 B, 8 C, 9 A, 9 B, 9 C, 9 D, 10 illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below.
  • FIGS. 5E.2 and 5 E. 3 are bottom views of horizontal cross sections according to some embodiments as set forth in detail below.
  • FIGS. 6 , 7 , 8 A, 8 B, 8 C, 9 A, 9 B, 9 C, 9 D, 10 , 11 , 12 illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below.
  • FIG. 3A shows the beginning stages of fabrication of an interposer 120 . 1 according to some embodiments of the present invention.
  • the interposer substrate 120 . 1 S is initially chosen to be sufficiently thick to provide easy handling and adequate heat dissipation in fabrication.
  • substrate 120 . 1 S is a monocrystalline silicon wafer of a 200 mm or 300 mm diameter and a thickness of 650 micron or more. These materials and dimensions are exemplary and do not limit the invention.
  • substrate 120 . 1 S can be made of other semiconductor materials (e.g. gallium arsenide), or glass, or sapphire, or metal, or possibly other materials. Possible materials include NbTaN and LiTaN.
  • the substrate will later be thinned; for example, in case of silicon, the final thickness could be 5 to 50 microns. Again, these dimensions are not limiting.
  • Substrate 120 . 1 S is patterned to form blind vias 224 B ( FIG. 3B ).
  • “Blind” means that the vias do not go through substrate 120 . 1 S. This can be done, for example, as follows for silicon substrates.
  • optional layer 310 FIG. 3A
  • layer 310 can be silicon dioxide formed by thermal oxidation, chemical vapor deposition (CVD), or sputtering.
  • photoresist 320 is deposited and photolithographically patterned to define the vias.
  • Layer 310 and substrate 120 . 1 S are etched in areas exposed by resist 320 to form the blind vias.
  • the via depth is equal or slightly greater than the final depth of substrate 120 . 1 S, e.g. 5 to 51 microns for some silicon-substrate embodiments.
  • the vias can be formed by a dry etch, e.g. dry reactive ion etching (DRIE).
  • An exemplary diameter of each via can be 60 microns or less, but other dimensions are possible.
  • the vias can be vertical (as shown) or may have sloped sidewalls. As noted above, the particular dimensions, processes and other features are illustrative and not limiting.
  • dielectric layer 324 ( FIG. 3C ) is formed on the entire top surface of substrate 120 . 1 S.
  • Dielectric 324 lines the via surfaces.
  • dielectric 324 is formed by thermal oxidation of the silicon substrate or by CVD or physical vapor deposition (PVD).
  • Dielectric 324 will electrically insulate the substrate from subsequently formed metal in vias 224 B.
  • the dielectric thickness depends on the desired process parameters, and is 1 micron in an exemplary thermal-oxide embodiment (a thermal oxide is silicon dioxide formed by thermal oxidation). Other dimensions and materials can be used instead.
  • Dielectric 324 can be omitted if substrate 120 . 1 S is itself dielectric.
  • metal 224 M ( FIG. 3D ) is formed in vias 224 B over the dielectric 324 .
  • metal 224 M fills up the vias, but in other embodiments the metal is a liner on the via surfaces.
  • metal 224 M is electroplated copper.
  • a barrier layer (metal or dielectric, not shown separately) is formed first on dielectric 324 to aid in copper adhesion and prevent copper diffusion into the dielectric 324 or substrate 120 . 1 S. Suitable barrier layers may include a layer of titanium-tungsten (see Kosenko et al., US pre-grant patent publication 2012/0228778 published Sep.
  • a seed layer e.g. copper
  • PVD physical vapor deposition
  • copper is electroplated on the seed layer to fill the vias 224 B and cover the whole substrate 120 . 1 S.
  • the copper is then removed from the areas between the vias by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the CMP may also remove the barrier layer (if present) from these areas, and may stop on dielectric 324 . As a result, the copper and the barrier layer remain only in and over the vias 224 B.
  • vias 224 For ease of description, we will refer to vias 224 as “metallized”, but non-metal conductive materials can also be used (e.g. doped polysilicon).
  • layer 224 M does not fill the vias but only lines the via surfaces, some other material (not shown) can be formed on layer 224 M as a filler to fill the vias and provide a planar top surface for the wafer.
  • This filler material can be polyimide deposited by spin coating for example.
  • RDL 210 .T ( FIG. 3E ) is formed on top of substrate 120 . 1 S to provide contact pads 120 . 1 C.T at desired locations.
  • RDL 210 .T can be formed by prior art techniques described above in connection with FIGS. 1 and 2 for example.
  • RDL 210 .T is omitted if the contact pads 120 . 1 C.T are provided by the top areas of metal 224 M.
  • substrate 120 . 1 S is not dielectric, then a dielectric layer can be formed on the substrate and photolithographically patterned to expose the contact pads 120 . 1 C.T.
  • Interposer 120 . 1 may include transistors, resistors, capacitors, and other devices (not shown) in substrate 120 . 1 S and redistribution layer 210 .T. These devices can be formed before, during and/or after the fabrication of vias 224 and RDL 210 .T using the process steps described above and/or additional process steps. Such fabrication techniques are well known. See e.g. the aforementioned U.S. Pat. No. 6,958,285 and pre-grant patent publication 2012/0228778.
  • Dies 110 are attached to contact pads 120 . 1 C.T with connections 140 . 1 , using possibly prior art methods described above in connection with FIGS. 1 and 2 or other methods (e.g. diffusion bonding; in this case the connections 140 . 1 are not additional elements but are part of contact pads 110 C and/or 120 . 1 C.T).
  • an encapsulant (not shown) can be formed around the dies and/or under the dies using the same techniques as described above in connection with FIG. 1 (e.g. by molding and/or underfilling).
  • the encapsulant can be any suitable material (e.g. epoxy with silica or other particles). No encapsulant is used in some embodiments. Other embodiments use an encapsulant, but the requirements for the encapsulant are relaxed because the dies will be protected by an additional, protective substrate 410 ( FIG. 5A ) as described below.
  • the encapsulant is provided only underneath the dies (as underfill), i.e. only between the dies and substrate 120 . 1 S (around the connections 140 . 1 ).
  • FIGS. 4A-4C illustrate fabrication of protective substrate 410 .
  • substrate 410 should be sufficiently rigid to facilitate subsequent handling of the assembly as explained below.
  • substrate 410 includes monocrystalline silicon substrate 410 S of a thickness 650 microns or higher. Other materials and thicknesses are possible, based on any factors that may be important (including the availability of materials and processes).
  • One possible factor is reducing the mismatch of the coefficients of thermal expansion (CTE) between substrates 410 and 120 . 1 S: if substrate 120 . 1 S is silicon, then substrate 410 S could be silicon or another material with a similar CTE.
  • Another factor is reducing the CTE mismatch between substrate 410 and dies 110 .
  • substrate 410 S will not have any circuitry, but if circuitry is desired in or on substrate 410 S then this may affect the choice of material.
  • the circuitry can be fabricated before, and/or during, and/or after the steps described below.
  • Another possible factor is high thermal conductivity to enable the substrate 410 to act as a heat sink.
  • metal may be appropriate.
  • Cavities 414 are formed in substrate 410 to match the size and position of dies 110 .
  • An exemplary process is as follows (this process is appropriate for a silicon substrate 410 S, and may be inappropriate for other materials; known processes can be used for silicon or other materials).
  • an auxiliary layer 420 FIG. 4B
  • Resist 430 is deposited and patterned photolithographically to define the cavities.
  • Auxiliary layer 420 exposed by the resist openings is etched away.
  • substrate 410 S is etched in these openings to form cavities 414 with sloped, upward-expanding sidewalls.
  • the cavity depth depends on the thickness of dies 414 and connections 140 . 1 as explained below. Non-sloped (vertical) or retrograde sidewalls, or other sidewall profiles are also possible.
  • auxiliary layer 420 is also removed, but in other embodiments layer 420 remains in the final structure.
  • substrate 410 is attached to interposer 120 . 1 so that each die 110 fits into a corresponding cavity 414 .
  • legs 410 L of protective substrate 410 are attached to the top surface of interposer 120 . 1 (e.g. to RDL 210 .T if the RDL is present; legs 410 L are those portion(s) of protective substrate 410 that surround the cavities).
  • the substrate-to-interposer attachment is shown as direct bonding, but other types of attachments (e.g. by adhesive) can also be used as described further below.
  • the entire assembly is marked with numeral 504 .
  • each die's top surface physically contact the top surfaces of cavities 414 .
  • each die's top surface is bonded to the cavity top surface (directly or in some other way, e.g. by adhesive). This bonding increases the bonding strength between the two substrates and improves the thermal conductivity of the thermal path from the dies to the protective substrate.
  • the bond between the dies and the cavity surfaces restricts the dies' lateral motion and thus counteracts lateral or other forces that could weaken the connections 140 . 1 . For example, if the protective substrate 410 and interposer 120 .
  • the dies are not bonded to the cavities' top surfaces, and thus the dies' top surfaces can slide laterally along the cavities' top surfaces in thermal movement. This may reduce the thermal stresses, e.g. if the die-interposer CTE matching is better than the matching between the interposer and protective substrate 410 .
  • the downward pressure of substrate 410 on the dies helps counteract the die warpage.
  • the dies' tendency to warp increases with temperature, and the pressure may also increase with temperature (e.g. if the dies expand vertically more than the protective substrate's legs 410 L).
  • the dies are underfilled and/or encapsulated from above by a suitable stress-relieving material, e.g. epoxy.
  • a suitable stress-relieving material e.g. epoxy
  • the encapsulant may be a solid material (possibly thermosetting) physically contacting the top surfaces of cavities 414 .
  • the encapsulant may or may not be bonded to the cavity surfaces as described above, with benefits similar to those described above for the no-encapsulant embodiments.
  • the top surfaces of the dies (or encapsulant) should have uniform height.
  • the dies (or encapsulant) can be polished before joining of substrate 410 to interposer 120 . 1 . Suitable polishing processes include lapping, grinding, and chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the cavity surfaces and/or the dies can be provided with a suitable temperature interface material (TIM, not shown here but shown at 525 in FIGS. 5E.2 and 5 E. 3 discussed below) to improve the thermal transfer between the dies and substrate 410 .
  • TIM's thermal conductivity can usually be higher than that of air.
  • Exemplary TIMs are those that exist in semisolid, gel-like (grease-like) state throughout the range of expected operating temperatures (e.g. 0° C. to 200° C. for some assemblies) or at least when the temperatures are high to make die cooling particularly desirable (20° C. to 200° C. for some assemblies).
  • the gel-like materials fill free spaces between the dies and substrate 410 to provide a thermally conductive path away from the dies.
  • An exemplary TIM material is a thermal grease available from Arctic Silver, Inc. (having an office in California, USA); the grease's thermal conductivity is 1 W/mK.
  • the interposer is thinned from the bottom to expose the metal 224 M ( FIG. 5B ).
  • the thinning involves partial removal of substrate 120 . 1 S and dielectric 324 (if the dielectric is present).
  • the thinning may be performed by known techniques (e.g. mechanical grinding or lapping of substrate 120 . 1 S followed by dry or wet, masked or unmasked etch of substrate 120 . 1 S and dielectric 324 ; the substrate and the dielectric are etched simultaneously in some embodiments.)
  • dielectric 324 protrudes out of substrate 120 .
  • interposer 120 . 1 is kept flat by substrate 410 , so the handling of the assembly 504 is facilitated.
  • Substrate 410 also helps absorb and dissipate the heat generated during this and subsequent fabrication stages and in subsequent operation of assembly 504 .
  • the final thickness of substrate 120 . 1 S can therefore be very low, e.g. 50 microns or even 5 microns or less.
  • blind vias 224 B FIG. 3B
  • the shallow depth facilitates fabrication of the metallized vias (i.e. facilitates the via etch and subsequent deposition of dielectric and metal into the vias).
  • the shallow depth also shortens the signal paths through the vias.
  • each via can be narrower while still allowing reliable dielectric and metal deposition. The via pitch can therefore be reduced.
  • protective substrate 410 can be thinned from the top; this is not shown.
  • the combined thickness of substrates 120 . 1 S and 410 is defined by desired properties, such as rigidity, resistance to warpage, heat dissipation, and assembly size.
  • RDL 210 .B is formed on the bottom of substrate 120 . 1 S, possibly using prior art techniques (as in FIG. 2 for example).
  • the RDL provides contact pads 120 . 1 C.B and connects them to metal 224 M. (If the RDL is omitted, the contact pads are provided by metal 224 M).
  • the assembly 504 can be diced into stacks 504 S ( FIG. 5D ). Then the stacks (or the entire assembly 504 if dicing is omitted) are attached to other structures, such as wiring substrate 120 . 2 (e.g. a printed wiring substrate) in FIG. 5E.1 .
  • wiring substrate 120 . 2 e.g. a printed wiring substrate
  • a stack 504 S is attached to PWS 120 . 2 , and more particularly the stack's contacts 120 . 1 C.B are attached to PWS contacts 120 . 2 C, possibly by the same techniques as in FIG. 1 or 2 .
  • Conductive lines 130 of PWS 120 . 2 connect the contact pads 120 . 2 C to each other or other elements. These details are not limiting.
  • FIG. 5E.2 shows a possible bottom view of the horizontal cross section along the line 5 E. 2 - 5 E. 2 in FIG. 5E.1 .
  • the dies are surrounded by temperature interface material (TIM) 525 .
  • TIM temperature interface material
  • the legs 410 L form a region completely surrounding each die, and the interposer area bonded to the legs also completely surrounds each die.
  • FIG. 5E.3 shows another possible bottom view of the same horizontal cross section, also with TIM 525 .
  • the legs 410 L are provided only on two opposite sides of each die (left and right sides) but are not provided above and below the dies.
  • Each cavity 414 is a horizontal groove in substrate 410 S, possibly containing multiple dies spread laterally along the groove. The groove may run through the entire substrate. Other cavity shapes are also possible.
  • protective substrate 410 and interposer 120 . 1 can be bonded by adhesive, and FIG. 6 illustrates such bonding by adhesive 610 .
  • Adhesive 610 is provided on legs 140 L or the corresponding areas of interposer 120 . 1 or both. The structure is shown at the stage of FIG. 5A (before interposer thinning).
  • the adhesive is elastic, with a low elasticity modulus (e.g. silicone rubber with elasticity modulus of 50 MPa), to help absorb the thermal expansion of dies 110 (so that the pressure from the expanding dies 110 would not damage the protective substrate 410 or the dies).
  • the dies' CTE is equal to or greater than the CTE of protective substrate 410 or substrate 410 S.
  • the adhesive's elasticity also absorbs the height non-uniformity of the top surfaces of dies 110 or the top surfaces of cavities 414 .
  • the adhesive may have a CTE equal to or greater than the dies' CTE.
  • Exemplary adhesives are epoxy-based underfills.
  • FIG. 7 shows a similar embodiment, but the adhesive 610 covers the whole bottom surface of protective substrate 410 S.
  • the adhesive bonds the dies' (or encapsulant's) top surfaces to the top surfaces of the cavities.
  • the adhesive's CTE can be equal to, or greater than, or less than, the dies' CTE.
  • FIGS. 8A-8C illustrate the use of separate bonding layers 810 , 820 to directly bind the protective substrate 410 to interposer 120 . 1 .
  • the bonding layers are silicon dioxide, but other materials can also be used (e.g. metals for eutectic bonding).
  • the dies are attached to interposer 120 . 1 as in FIG. 3E ; the dies are then optionally underfilled and/or encapsulated from above (in FIG. 8A , encapsulant 150 encapsulates and underfills the dies).
  • Bonding layer 810 e.g. silicon dioxide or metal, is formed to cover the interposer and the dies (and the encapsulant if present), by any suitable techniques (e.g. sputtering).
  • the protective substrate 410 is provided with cavities as in FIG. 4C .
  • a bonding layer 820 e.g. silicon dioxide or metal, is formed to cover the substrate surface by any suitable techniques (e.g. sputtering, or thermal oxidation if substrate 410 S is silicon).
  • the interposer is joined to substrate 410 so that the layers 810 , 820 physically contact each other.
  • the structure is then heated to bond the layer 820 to layer 810 where the two layers meet, i.e. at legs 410 L and at the cavities' top surfaces.
  • the layer 820 is removed at the cavities' top surfaces not to bond the dies to the cavities' top surfaces.
  • FIGS. 9A-9D illustrate an exemplary process.
  • Interposer 120 . 1 is fabricated essentially as in FIG. 3E or 6 or 8 A, but without vias 224 (the vias will be formed later).
  • dielectric 324 is a flat layer on interposer substrate 120 . 1 S.
  • contact pads 910 are formed on substrate 120 . 1 S at the locations of future vias 224 .
  • RDL 210 .T is optionally fabricated on top of the interposer to connect the contact pads 910 to pads 120 . 1 C.T on top of the interposer. (Alternatively, the pads 120 .
  • 1 C.T can be provided by pads 910 .
  • Dies 110 are attached to pads 120 . 1 C.T, and optionally underfilled and encapsulated.
  • Bonding layer 810 (as shown) is optionally deposited as in FIG. 8A for bonding to the protective substrate (alternatively, the bonding can be by an adhesive as in FIG. 6 or 7 , or by a direct bonding process as described above in relation to FIG. 5A ).
  • Interposer 120 . 1 with the dies attached is then bonded to protective substrate 410 ( FIG. 9B ) as in any embodiment described above. Then the interposer is thinned ( FIG. 9C ). The dies will be protected by substrate 410 during subsequent steps. Substrate 410 can be thinned at any desired stage.
  • metallized vias 224 are formed from the interposer bottom.
  • An exemplary process is as follows:
  • Dielectric 920 e.g. silicon dioxide or silicon nitride
  • Dielectric 920 is deposited (e.g. by sputtering or CVD) to cover the bottom surface of interposer substrate 120 . 1 S.
  • Vias are etched from the bottom through dielectric 920 and substrate 120 . 1 S. This is a masked etch which stops on contact pads 910 .
  • Dielectric 930 e.g. silicon dioxide or silicon nitride
  • Dielectric 930 is deposited (e.g. by sputtering or CVD) to cover the bottom surface of interposer substrate 120 . 1 S and to line the vias.
  • Dielectric 930 covers the contact pads 910 from the bottom.
  • Dielectric 930 is etched to expose the contact pads 910 . This can be a masked etch. Alternatively, a blanket anisotropic (vertical) etch can be used to remove the dielectric 930 from over at least a portion of each contact pad 910 while leaving the dielectric on the via sidewalls. The vertical etch may or may not remove dielectric 930 outside the vias.
  • a conductive material 224 M (e.g. metal) is formed in the vias, possibly by the same techniques as described above (e.g. copper electroplating).
  • the conductive material is not present outside the vias (e.g. it can be polished away by CMP).
  • the conductive material may fill the vias or just line the via surfaces.
  • the conductive material in each via physically contacts the corresponding pad 910 .
  • FIGS. 5 C- 5 E. 3 Subsequent processing steps can be as described above in connection with FIGS. 5 C- 5 E. 3 .
  • the bottom RDL 210 .B ( FIG. 5C ) and connections 140 . 2 can be formed as described above.
  • the structure can be diced if desired ( FIG. 5D ), and attached to another structure (e.g. PWS 120 . 2 in FIG. 5E.1 ).
  • Vias 224 are optional, and further the substrate 120 . 1 can be any wiring substrate, such as shown at 120 in FIG. 10 .
  • This figure illustrates an embodiment using an adhesive 610 to bond the protective substrate 410 to WS 120 at legs 410 L and at the cavity top surfaces, but any other bonding method described above can be used. No underfill or other encapsulant is shown, but underfill with or without encapsulation of the entire die can be present.
  • the techniques described above in connection with FIGS. 5A-10 can be used to attach any number of separate protective substrates 410 to the same interposer 120 . 1 or WS 120 ; different protective substrates 410 can be attached to the same side of a substrate 120 . 1 or 120 , with different dies in different cavities of the same or different protective substrates 410 .
  • Other protective substrates 410 can be attached to the opposite side of substrate 120 . 1 or 120 . Some of the dies may have no protective substrate 410 to protect them.
  • Each substrate 120 . 1 S or 410 S can be a wafer, and the two substrates can be of the same size in a given assembly 504 ; but different sizes are also possible in the same assembly.
  • the dies can also be stacked one above another in the same cavity (see FIG. 11 showing the structure at the same fabrication stage as FIG. 6 ), with only the top die of each stack physically contacting the corresponding cavity's top surface.
  • the dies in each stack may have their respective circuits interconnected through their contact pads 1110 C and respective connections 140 (which can be of any type described above).
  • substrates 120 . 1 S, 410 S are bonded together by adhesive 610 on legs 410 L as in FIG. 6 , but the other bonding methods described above can also be used.
  • Stacked dies can also be used with other variations described above, e.g. when the protective substrate is bonded directly to the PWS.
  • substrate 410 S has circuitry, possibly connected to the circuitry in the dies and/or the interposer 120 . 1 S or the PWS. See FIG. 12 , showing the top dies connected to substrate 410 S by structures 1210 ; each structure 1210 includes a contact pad in substrate 410 S, a corresponding contact pad on a top die 110 , and a connection (e.g. solder or any other type described above) bonding the two contact pads to each other.
  • encapsulant 150 underfills and completely surrounds each die, contacting the cavities' top surfaces. As noted above, encapsulation and/or underfilling are optional.
  • the vias 224 can be formed after the RDLs, and can be etched through one or both of the RDLs.
  • a first substrate e.g. 120 . 1 or 120
  • first contact pads e.g. the top pads 120 . 1 C.T
  • each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
  • a second substrate (e.g. 410 or 410 S) comprising one or more cavities, the second substrate being attached to the first substrate, wherein at least part of each die is located in a corresponding cavity in the second substrate, the second substrate comprising a surface area (e.g. a surface of legs 410 L) which lies outside of the cavities and is attached to the first substrate;
  • At least one die satisfies one or both of conditions (A) and (B):
  • the die is separated from the surface of the corresponding cavity by solid material (e.g. an encapsulant or a bonding layer) which physically contacts the die and the surface of the corresponding cavity.
  • solid material e.g. an encapsulant or a bonding layer
  • each cavity in a side view in which each cavity is in a bottom surface of the second substrate (e.g. as in FIG. 5C or 5 E. 1 ), said surface area of the second substrate laterally surrounds each cavity (e.g. as in FIG. 5E.2 ).
  • the at least one die is attached to the surface of the corresponding cavity.
  • the at least one die is not attached to the surface of the corresponding cavity.
  • the one or more first contact pads are located at a first side of the first substrate
  • the first substrate comprises one or more second contact pads at a second side opposite to the first side (e.g. contact pads 120 . 1 C.B at the interposer bottom); and
  • the first substrate comprises one or more electrically conductive paths passing through the first substrate (e.g. metallized vias 224 ) and electrically connecting at least one first contact pad to at least one second contact pad.
  • At least one of the conditions (A) and (B) is satisfied at room temperature.
  • the at least one die is under pressure from the second substrate.
  • the pressure does not exceed 200 MPa at room temperature. In some embodiments, the pressure is greater than the atmospheric pressure (1 bar, i.e. 10 5 Pa), and can be in the range from 1 bar to 200 MPa or any sub-range of this range. The pressure can also be above or below this range.
  • Some embodiments provide a method for fabricating an electrically functioning manufacture, the method comprising:
  • a first substrate (e.g. 120 . 1 ) comprising a first side and one or more first contact pads at the first side;
  • each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
  • obtaining a second substrate (e.g. 410 ) comprising one or more cavities;
  • the second substrate attaching the second substrate to the first substrate, with at least part of each die being located in a corresponding cavity in the second substrate, the second substrate comprising a surface area (e.g. bottom areal of legs 410 L) which lies outside of the cavities and is attached to the first substrate;
  • a surface area e.g. bottom areal of legs 410 L
  • At least one die satisfies one or both of conditions (A) and (B):
  • the die is separated from the surface of the corresponding cavity by solid material which physically contacts the die and the surface of the corresponding cavity.
  • each cavity in a side view in which each cavity is in a bottom surface of the second substrate, said surface area of the second substrate laterally surrounds each cavity.
  • the at least one die is attached to the surface of the corresponding cavity.
  • the at least one die is not attached to the surface of the corresponding cavity.
  • the one or more first contact pads are located at a first side of the first substrate
  • the first substrate comprises one or more second contact pads at a second side opposite to the first side;
  • the first substrate comprises one or more electrically conductive paths passing through the first substrate and electrically connecting at least one first contact pad to at least one second contact pad.
  • At least one of the conditions (A) and (B) is satisfied at room temperature.
  • the at least one die is under pressure from the second substrate when the first substrate is attached to the second substrate.
  • the pressure does not exceed 200 MPa at room temperature.
  • the one or more dies are a plurality of dies
  • the method further comprises polishing a solid surface at a first side of the dies before attaching the first substrate to the second substrate, the first side of the dies being a side opposite to each die's one or more contact pads, the solid surface being a surface of the dies or of an encapsulant formed on the dies.
  • the solid surface is a surface of the encapsulant which comprises an epoxy.
  • a first substrate comprising one or more first contact pads
  • each die comprising a semiconductor integrated circuit which comprises one or more contact pads each of which is attached to a respective first contact pad;
  • a second substrate comprising one or more cavities, the second substrate being attached to the first substrate, wherein at least part of each die is located in a corresponding cavity in the second substrate, the second substrate comprising a surface area which lies outside of the cavities and is attached to the first substrate;
  • At least one die is under pressure from the second substrate.
  • the pressure does not exceed 200 MPa at room temperature.
  • each cavity in a side view in which each cavity is in a bottom surface of the second substrate, said surface area of the second substrate laterally surrounds each cavity.
  • the at least one die is attached to the surface of the corresponding cavity.
  • the at least one die is not attached to the surface of the corresponding cavity.
  • the one or more first contact pads are located at a first side of the first substrate
  • the first substrate comprises one or more second contact pads at a second side opposite to the first side;
  • the first substrate comprises one or more electrically conductive paths passing through the first substrate and electrically connecting at least one first contact pad to at least one second contact pad.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
US14/214,365 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture Abandoned US20150262902A1 (en)

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US14/214,365 US20150262902A1 (en) 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US14/288,064 US9355997B2 (en) 2014-03-12 2014-05-27 Integrated circuit assemblies with reinforcement frames, and methods of manufacture
KR1020167028245A KR20160132093A (ko) 2014-03-12 2015-03-10 공동을 가진 기판에 의해 보호되는 집적 회로 및 제조 방법
PCT/US2015/019609 WO2015138393A1 (en) 2014-03-12 2015-03-10 Integrated circuits protected by substrates with cavities, and methods of manufacture
TW104107704A TWI573223B (zh) 2014-03-12 2015-03-10 空腔基板保護之積體電路
US15/165,837 US9887166B2 (en) 2014-03-12 2016-05-26 Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US15/265,148 US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15/865,842 US10446456B2 (en) 2014-03-12 2018-01-09 Integrated circuits protected by substrates with cavities, and methods of manufacture
US16/599,683 US11205600B2 (en) 2014-03-12 2019-10-11 Integrated circuits protected by substrates with cavities, and methods of manufacture

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US14/214,365 US20150262902A1 (en) 2014-03-12 2014-03-14 Integrated circuits protected by substrates with cavities, and methods of manufacture

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US14/558,462 Active US9324626B2 (en) 2014-03-12 2014-12-02 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15/005,220 Active US9691696B2 (en) 2014-03-12 2016-01-25 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15/265,148 Active US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15/865,842 Active US10446456B2 (en) 2014-03-12 2018-01-09 Integrated circuits protected by substrates with cavities, and methods of manufacture
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US15/005,220 Active US9691696B2 (en) 2014-03-12 2016-01-25 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US15/265,148 Active US9899281B2 (en) 2014-03-12 2016-09-14 Integrated circuits protected by substrates with cavities, and methods of manufacture
US15/865,842 Active US10446456B2 (en) 2014-03-12 2018-01-09 Integrated circuits protected by substrates with cavities, and methods of manufacture
US16/599,683 Active US11205600B2 (en) 2014-03-12 2019-10-11 Integrated circuits protected by substrates with cavities, and methods of manufacture

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