TW202247365A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202247365A
TW202247365A TW110147688A TW110147688A TW202247365A TW 202247365 A TW202247365 A TW 202247365A TW 110147688 A TW110147688 A TW 110147688A TW 110147688 A TW110147688 A TW 110147688A TW 202247365 A TW202247365 A TW 202247365A
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Taiwan
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die
die group
group
substrate
thickness
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TW110147688A
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English (en)
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張任遠
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台灣積體電路製造股份有限公司
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Publication of TW202247365A publication Critical patent/TW202247365A/zh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種半導體元件包括封裝基板及接合至封裝基板上的第一晶粒組。第一晶粒組的特徵在於第一厚度。半導體元件亦具有接合至封裝基板的第二晶粒組。第二晶粒組的特徵在於第二厚度。半導體元件進一步包括設置在第一晶粒組上的載體基板。載體基板的特徵在於第三厚度，該第三厚度為第一厚度與第二厚度之間的差的函數。模製化合物材料設置在封裝基板上且覆蓋第一晶粒組及第二晶粒組。模製化合物材料包括在第一晶粒組與第二晶粒組之間的空腔。

Description

具有應力消除結構的多晶片封裝
本揭示內容涉及用於降低半導體元件封裝中的熱應力的應力消除結構及其形成方法。
半導體晶粒可以與封裝基板中的其他電路電連接。封裝基板提供與印刷電路板上的其他電路的電連接。半導體晶粒可以具有不同功能，且難以使用相同的半導體處理技術進行處理，因此單獨製造該些半導體晶粒。藉由將複數個晶粒裝配至元件中可以獲得具有高性能的大型多功能元件。該些晶粒可以堆疊在一起以形成晶粒組，且晶粒組可以設置於封裝基板。不同的晶粒組及封裝基板具有不同的熱膨脹係數(coefficient of thermal expansion，CTE)。例如，元件晶粒中的矽基板可具有2.5 ppm/℃的CTE，介電層可具有在約0.5 ppm/℃與約8 ppm/℃之間的CTE，而封裝基板可具有約18 ppm/℃的CTE。例如在錫回焊(solder reflow)中或在操作期間，明顯不同的CTE可導致封裝基板在高溫下翹曲。封裝基板的翹曲可導致晶粒及/或凸塊裂紋及材料分層。
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以下揭示內容提供了用於實現提供之標的的不同特徵的許多不同的實施例或實例。以下描述組件及佈置的特定實例用以簡化本揭示內容。當然，該些僅為實例，且不旨在進行限制。例如，在下面的描述中在第二特徵上方或之上形成第一特徵可包括其中第一及第二特徵直接接觸形成的實施例，且亦可包括其中在第一特徵與第二特徵之間形成附加特徵的實施例，以使得第一特徵及第二特徵可以不直接接觸。此外，本揭示內容可以在各個實例中重複元件符號及/或字母。此重複係出於簡單及清楚的目的，其本身並不指定所討論之各種實施例或組態之間的關係。
為了便於描述，本文中可以使用諸如「在……下方」、「在……下」、「下方」、「在……上方」、「上方」之類的空間相對術語，來描述如圖中所示的一個元件或特徵與另一元件或特徵的關係。除了在附圖中示出的方位之外，空間相對術語意在涵蓋元件在使用或操作中的不同方位。設備可以其他方式定向(旋轉90度或以其他方位)，並且在此使用的空間相對描述語亦可被相應地解釋。介詞，例如「上」及(如「側壁」中的)「側面」相對於晶圓或基板的頂表面上的習用平面或表面界定，而與晶圓或基板的方位無關。術語「水平」定義為平行於晶圓或基板的習用平面或表面的平面，與晶圓或基板的方位無關。術語「垂直」係指垂直於如上定義的水平線的方向，即，垂直於基板的表面。術語「第一」、「第二」、「第三」及「第四」在本文中可用於描述各種元件、組件、區域、層或部分，但這些元件、組件、區域、層或部分不受這些術語的限制。這些術語僅用於將一個元件、組件、區域、層或部分與另一區域、層或部分區分開。因此，在不脫離本揭示內容的教導的情況下，下面討論的第一元件、部件、區域、層或部分可稱為第二元件、部件、區域、層或部分。
複數個晶粒組封裝至共同的封裝基板中以形成封裝元件。封裝基板包括用於電連接晶粒組的導電線。可以使用覆晶接合將該些晶粒組接合至封裝基板的一側，且執行回焊以熔化使晶粒組及封裝基板互連的焊球。如上所述，不同的晶粒組及封裝基板可以具有不同的CTE。CTE失配會導致晶粒組翹曲，從而導致晶粒組內晶粒裂紋及分層，且對封裝元件的良率及性能產生不利影響。在一些實施例中，由於包裝層及晶粒組中的晶粒具有不同的CTE，因此在晶粒組上方形成包裝層的後續包裝成型製程會惡化晶粒組中的晶粒的翹曲。
與習用技術相比，本揭示內容實現了許多益處及優點。例如，實施例提供用於降低封裝半導體元件中的熱應力的應力消除結構。實施例克服了與封裝基板及接合在封裝基板上的晶粒組中的翹曲相關聯的問題，特別地，由於晶粒及封裝基板的熱膨脹係數(coefficient of thermal expansion，CTE)顯著不同而導致的堆疊晶粒中的裂紋及分層。本揭示內容的實施例具有有利的應力消除特徵或結構。例如，藉由將載體基板附接至晶粒組的上表面，可以減少由包裝層引起的應力。在一些實施例中，當在載體基板中嵌入氣隙時，可以進一步提高應力降低效果。
在一些實施例中，載體基板熔融接合(fusion bonded)至晶粒組的上表面。熔融接合的優點為在載體基板與晶粒組的上表面之間沒有形成附加層(例如，黏合劑層)。在一些實施例中，載體基板包括一或多個氣隙以提高應力消除能力。可以使用現有的CMOS製程技術在載體基板中形成一或多個氣隙。
在一些實施例中，應力消除特徵包括包裝層中的空腔，其中空腔設置在兩個相鄰的晶粒組之間。空腔可以進一步降低封裝元件中的應力。在一些實施例中，一種方法包括以下步驟：提供第一晶粒組及第二晶粒組，確定第一晶粒組與第二晶粒組之間的高度差，及因應所確定的高度差提供載體基板。該方法亦包括以下步驟：基於高度差減薄載體基板以獲得減薄的載體基板，及將減薄的載體基板設置於第一晶粒組以形成高度調整的(height-adjusted)第一晶粒組，該高度調整的第一晶粒組具有在第二晶粒組的高度範圍內的高度。在實施例中，載體基板實質上沒有電子元件。本揭示內容的這些及其他實施例，連同其許多優點及特徵，將結合下文及相應的附圖更詳細地描述。
本文描述的例示性實施例涉及具有安裝在襯底基板或封裝基板上的垂直堆疊晶片的多晶片元件。如本文所使用，晶片及晶粒可互換使用，且係指藉由將半導體晶圓分離成單獨的晶粒而形成的半導體晶圓的片，對半導體晶圓執行半導體製造製程。晶片或晶粒可包括具有相同硬體佈局或不同硬體佈局、相同功能或不同功能的經處理的半導體電路。一般而言，晶片或晶粒具有基板、複數個金屬線、插入金屬線之間的複數個介電層、電連接金屬線的複數個導孔及主動及/或被動元件。晶粒可以裝配在一起成為多晶片元件或晶粒組。如本文所使用，晶片或晶粒亦可指包括用以處理及/或儲存資料的電路的積體電路。晶片、晶粒或積體電路的實例包括現場可程式閘陣列(例如，field programmable gate array，FPGA)、處理單元(例如，圖形處理單元(graphics processing unit，GPU)或中央處理器(central processing unit，CPU))、應用特定積體電路(application specific integrated circuit，ASIC)、記憶體元件(例如，記憶體控制器、記憶體)等。
第1圖為根據一些例示性實施例的晶粒10的簡化剖面圖。參看第1圖，晶粒10包括表示積體電路(晶粒)製造的第一部分的前段製程(front-end-of-line，FEOL)，其中各個元件(例如，電晶體、電容器、二極體、電阻器、電感器等) 102形成在基板101中及上。基板101可為半導體基板或非半導體基板。例如，基板101可包括塊材矽基板。在一些實施例中，基板101可包括元素半導體(諸如晶體結構中的矽或鍺)、化合物半導體(例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)或其組合。可能的基板101亦可包括絕緣層上半導體(semiconductor-on-insulator，SOI)基板。在實施例中，基板101為SOI基板的矽層。視設計要求而定，基板101可包括各種摻雜區域，例如n型井或p型井。摻雜區摻雜有p型摻雜劑(例如硼)、n型摻雜劑(例如磷或砷)或其組合。
FEOL可包括以下步驟：在半導體基板101的上表面部分中界定主動區；形成隔離各個元件的溝槽隔離結構；執行用於形成井的植入；形成閘極結構、源極區及漏極區；及在半導體基板101及主動元件102上形成層間介電層(interlayer dielectric layer，ILD) 103。晶粒10亦包括表示在FEOL之後晶粒製造的第二部分的後段製程(back-end-of-line，BEOL)。BEOL包括以下步驟：基於形成的各個元件的位置形成金屬及導孔圖案。例如，在層間介電層103上形成複數個金屬間介電層(intermetal dielectric layer，IMD) 104，其中複數個圖案化的金屬線及導孔依次形成在IMD層104中。層間介電層(interlayer dielectric layer，IMD)各自可包括介電質或絕緣材料。合適的介電材料的實例包括氧化矽、摻雜氧化矽、本領域已知的各種低k介電材料及高k介電材料及其組合。IMD層104可以由習用技術形成，諸如化學氣相沈積(chemical vapor deposition，CVD)、電漿增強CVD (plasma enhanced CVD，PECVD)、物理氣相沈積(physical vapor deposition，PVD)或其他沈積方法。金屬線及導孔105形成在IMD層104中以提供至元件102的電連接。在實施例中，金屬線及導孔105可包括銅、鋁、鎳、鎢、鈷或其合金。
在實施例中，晶粒10亦包括IMD層104上的金屬墊106及具有電隔離金屬墊106的介電材料的鈍化層107。在實施例中，晶粒10進一步包括密封環108，該密封環108圍繞晶粒10且自金屬墊106穿過IMD層104及ILD層103延伸至基板101的表面。密封環108用以防止水分、水及其他污染物進入晶粒。在實施例中，晶粒10亦包括位於基板101的底表面上的複數個接觸墊109，接觸墊經由一或多個基板導孔110電連接至金屬線及導孔105。晶粒10亦包括介電層111，該介電層111含有設置在基板101的底表面上的一或多個接合墊。
第2圖為根據一些例示性實施例的具有彼此堆疊的複數個晶粒的晶粒組20的簡化剖面圖。參看第2圖，晶粒組20包括堆疊晶粒結構210，該堆疊晶粒結構210具有以實質水平佈置堆疊在彼此頂部的複數個晶粒211、212及213。在實施例中，每一晶粒可為類似於第1圖的晶粒10的半導體元件。例如，堆疊晶粒211、212及213中的每一者包括基板201、形成於基板201表面上的主動區202、複數個介電層203、形成在該些介電層203中的複數個金屬線及複數個金屬導孔204，以及位於頂部金屬間層206上的鈍化層207。在實施例中，堆疊晶粒亦可包括被動元件，例如電阻器、電容器、二極體、電感器等。在實施例中，堆疊晶粒經由熔融接合在鈍化層207的接合表面處彼此接合。在實施例中，一或多個接合墊嵌入晶粒211的鈍化層207中，且含有一或多個接合墊的介電層設置於晶粒212的下表面，使得晶粒211及212在晶粒211上表面上的鈍化層與晶粒212下表面上的介電層之間混合接合。
基板201可為半導體基板或非半導體基板。例如，基板201可包括塊材矽基板。在一些實施例中，基板201可包括元素半導體，諸如晶體結構的矽或鍺，化合物半導體，例如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦或其組合。可能的基板201亦可包括絕緣層上半導體(semiconductor-on-insulator，SOI)基板。在實施例中，基板201為SOI基板的矽層。視設計要求而定，基板201可包括各種摻雜區域，例如n型井或p型井。摻雜區摻雜有p型摻雜劑，例如硼，n型摻雜劑，例如磷或砷，或其組合。主動區202可包括電晶體。介電層203可包括層間介電(interlayer dielectric，ILD)層及金屬間介電(intermetal dielectric，IMD)層。在一些實施例中，ILD層及IMD層可為低k介電層，該低k介電層的介電常數(k值)小於預定值，例如約3.9、小於約3.0、小於2.5。在一些其他實施例中，介電層203可包括具有等於或大於3.9的介電常數的非低k介電材料。金屬線及導孔可包括銅、鋁、鎳、鎢或其合金。
晶粒組20亦可包括一或多個貫穿矽導孔(through silicon via，TSV)或貫穿氧化物導孔(through oxide via，TOV) 208，用以將堆疊晶粒211、212及213的金屬線中的一或多者電連接。一或多個貫穿矽導孔或貫穿氧化物導孔208可包括銅、鋁、鎢或其合金。在一些實施例中，堆疊晶粒211、212及213中的每一者亦可包括堆疊晶粒的側壁上的側金屬互連結構209。側金屬互連結構209可包括延伸穿過該些介電層203的曝露表面的一或多個金屬佈線。在不同的晶粒211、212及213已經接合在一起之後，側金屬互連結構209可以與金屬層同時形成且曝露於晶粒組20的側表面，且經由化學機械研磨(chemical mechanical polishing，CMP)製程研磨側表面。
在一些實施例中，可以藉由使用熔融接合(fusion bonding)、共晶接合(eutectic bonding)、金屬對金屬接合(metal-to-metal bonding)、混合接合(hybrid bonding)製程等將複數個晶圓接合在一起來形成晶粒組20。熔融接合包括以下步驟：將晶圓的氧化層接合至另一晶圓的氧化層。在實施例中，氧化物層可包括氧化矽。在共晶接合製程中，將兩種共晶材料放在一起，且施加特定的壓力及溫度以熔化共晶材料。在金屬對金屬接合製程中，將兩個金屬墊放置在一起，對金屬墊施加壓力及高溫以將該些金屬墊接合在一起。在混合接合製程中，兩個晶圓的金屬墊在高壓及高溫下接合在一起，同時接合兩個晶圓的氧化表面。
在一些實施例中，每一晶圓可包括複數個晶粒，諸如第1圖的半導體元件。接合的晶圓含有具有複數個堆疊晶粒的複數個晶粒組。藉由機械鋸切、雷射切割、電漿蝕刻等將接合的晶圓分割成單獨的晶粒組，該些晶粒組可為如第2圖所示的晶粒組20。
第3A圖為根據一些實施例的以三維(three-dimensional，3D)組態堆疊在彼此頂部的複數個晶圓的簡化立體圖。參看第3A圖，在例示性實施例中，第一晶圓「晶圓1」為可以在其上形成複數個晶粒的基底晶圓。第二晶圓「晶圓2」為可以在其上形成複數個晶粒的中間晶圓，而第三晶圓「晶圓3」為可以在其上形成複數個晶粒的頂部晶圓。晶圓可具有貫穿基板導孔(through substrate via，TSV)及/或貫穿氧化物導孔(through oxide via，TOV)及背面接合層(例如，金屬化層及/或介電層)，且使用任何已知的接合技術(例如，熔融接合、共晶接合、金屬接合、混合接合等)接合在一起以形成3D堆疊晶圓組態。三個晶圓(晶圓1、晶圓2及晶圓3)藉由貫穿基板導孔、貫穿氧化導孔及/或背面金屬化層及介電層彼此電連接。每一晶圓可以具有不同的晶粒。例如，晶圓1可包括中央處理器、圖形處理單元及邏輯單元的晶粒，晶圓2可包括記憶體元件及記憶體控制器的晶粒，且晶圓3可包括匯流排介面、輸入/輸出埠及通信及網絡元件的晶粒。在第3A圖所示的實例中，使用了三個晶圓，但應理解，該數量僅為說明性的且選擇用於描述示例實施例而不應為限制性的。在一些實施例中，鈍化層形成在每一晶圓的上表面且包括厚度以提供基板及金屬化層之間的分離。在實施例中，鈍化層包括氧化物材料。
第3B圖為第3A圖的堆疊晶圓組態的簡化立體圖，該堆疊晶圓組態根據例示性實施例切割且分離成單獨的條。例如，可以藉由機械鋸切、電漿蝕刻、雷射切割等將堆疊的晶圓切割成單獨的條及單獨的晶粒組。參看第3B圖，每一晶圓包括基板、包括層間介電層(interlayer dielectric layer，ILD)及金屬間介電層(intermetal dielectric layer，IMD)的複數個介電層，及形成在介電層中的複數個金屬線及複數個導孔304。堆疊晶圓的晶粒經由貫穿基板導孔及貫穿氧化物導孔彼此電耦合。在一些實施例中，單獨的條放置在研磨板上，且在切割或分割成晶粒之前研磨條的表面。
第3C圖為根據例示性實施例的包括複數個堆疊晶粒的單個晶粒組30的簡化立體圖。參看第3C圖，晶粒組30包括堆疊在彼此頂部的第一晶粒301a、第二晶粒301b及第三晶粒301c。第一、第二及第三晶粒中的每一者可包括基板、包括複數個主動元件(未示出)的主動區、形成在基板上且用以用以將每一晶粒的主動區與每一晶粒電連接的互連結構303。互連結構303可包括複數個介電層303a、形成在介電層303a中的金屬線303b及連接不同層中的金屬線303b的導孔303c。在一些實施例中，介電層303a包括氧化矽、氮化矽、碳化矽、氮氧化矽及/或其組合。在一些實施例中，介電層303a可包括具有低k值的一或多個低k介電層。在一些實施例中，低k介電材料的k值可低於約3.0。
在一些實施例中，晶粒藉由貫穿基板導孔(through substrate via，TSV)及貫穿氧化物導孔(through oxide via，TOV) 308彼此電耦合。在一些實施例中，晶粒組30亦包括接合層317，該接合層317包括氧化物材料，例如，氧化矽。在一些實施例中，接合層317可包括複數個接合膜及具有複數個焊接區域的電連接器309。在一些實施例中，電連接器309包括銅柱、焊帽及/或導電凸塊310，用以電耦合至印刷電路板或其他基板上的其他電子電路。在一些實施例中，晶粒組30包括與第2圖類似的複數個半導體晶粒或晶片。在實施例中，晶粒組30的堆疊晶粒包括邏輯元件、輸入/輸出(input/output，IO)元件、處理單元，例如資料處理單元、圖形處理單元、應用特定積體電路(application specific integrated circuit，ASIC)、現場可程式閘陣列(field programmable gate array，FPGA)、其他適用類型的元件。在一些實施例中，晶粒組30為包括複數個功能的系統積體電路(system-on-integrated circuit，SoIC)元件。在第3A圖所示的實例中，示出了三個晶粒，但應理解，該數量僅為說明性的且選擇用於描述例示性實施例而不應為限制性的。例如，晶粒組30可包括單個晶粒、兩個晶粒或多於三個晶粒。在一些實施例中，可以使用電連接器309經由覆晶接合將晶粒組30接合至封裝基板(例如，中介層、印刷電路板)。
在一些實施例中，晶粒藉由混合接合製程彼此接合。在實施例中，第一晶粒301a具有形成在其上表面的第一接合表面，該第一接合表面包括第一接合介電層315a及第一導電接觸結構316a。第二晶粒301b具有形成於其基板底部的第二接合面，該第二接合面包括第二接合介電層315b及導電接觸結構316b。在實施例中，第一導電接觸結構316a及第二導電接觸結構316b可電耦合至互連結構303。在另一實施例中，第一導電接觸結構316a及第二導電接觸結構316b可以不電耦合至互連結構303。在實施例中，第一晶粒301a及第二晶粒301b直接混合接合在一起，使得第一導電接觸結構316a及第二導電接觸結構316b接合在一起，且第一接合介電層315a及第二接合介電層315b接合在一起。在實施例中，第一接合介電層315a及第二接合介電層315b均包括氧化矽，且第一導電接觸結構316a及第二導電接觸結構316b均包括銅。
在實施例中，晶粒亦包括密封環320，用以阻止在接合製程及/或分離期間由應力產生的裂紋。密封環320亦用以防止水、水分及其他污染物進入晶粒。在實施例中，密封環320包括用以抑制電磁雜訊的銅。在實施例中，第一晶粒301a可包括接合介電層330，用以藉由熔融接合至載體基板。
第4圖為根據例示性實施例的包括複數個堆疊晶粒的晶粒組40的簡化剖面圖。參看第4圖，晶粒組40包括堆疊在彼此頂部的複數個晶粒。在例示性實施例中，晶粒組40包括晶粒401a、401b、401c、401d及401e。在例示性實施例中，每一晶粒包括基板、前段製程(front-end-of-line，FEOL)結構及後段製程結構。FEOL結構通常包括積體電路製造的第一部分，諸如形成溝槽隔離結構、執行用於形成井的植入、形成主動區，例如源極/漏極區、閘極結構及層間介電層。BEOL結構通常包括在金屬間介電層中形成導電線、導孔以電耦合形成在基板上的電子電路。在一些實施例中，晶粒401a、401b、401c、401d及401e為記憶體晶粒。記憶體晶粒可包括記憶體元件，例如靜態隨機存取記憶體(static random access memory，SRAM)元件、動態隨機存取記憶體(dynamic random access memory，DRAM)元件、其他合適的元件或其組合。在一些實施例中，晶粒401a為記憶體控制器晶粒，該記憶體控制器晶粒電連接至設置在其上的記憶體晶粒401b、401c、401d及401e。在一些實施例中，晶粒組40可用作高頻寬記憶體(high bandwidth memory，HBM)。在第4圖所示的實例中，示出了五個晶粒，但應理解，該數量僅為說明性的且選擇用於描述例示性實施例而不應為限制性的。例如，在一些實施例中，晶粒組40可包括少於或多於五個晶粒。
在一些實施例中，晶粒組40亦包括複數個導電部件402，延伸穿過晶粒401a至401e且電耦合至設置在晶粒401a、401b、401c、401d及401e之間以將其電連接在一起的複數個導電接合結構403。導電部件402用作貫穿基板導孔(through substrate via，TSV)以將晶粒彼此電連接。在實施例中，導電接合結構403包括微小的焊接凸塊，諸如受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊或球柵陣列(ball grid array，BGA)凸塊及使用各種製程步驟形成在晶粒上表面的的柱。在一些實施例中，晶粒組40亦包括形成在晶粒401a的BEOL結構的表面上且用以將晶粒組40接合至基板410的接合結構405。晶粒組40翻轉且安裝在基板410上。在一些實施例中，晶粒組40亦包括包裝晶粒401a、401b、401c、401d及401e的模製化合物層411。模製化合物層411包括環氧基樹脂或其他合適的材料。在一些實施例中，模製化合物層411填充晶粒401a、401b、401c、401d及401e之間的氣隙且圍繞導電接合結構403及405。
第5A圖為根據實施例的封裝元件50的簡化剖面圖。參看第5A圖，封裝元件50包括封裝基板500、第一晶粒組501及第二晶粒組502。使用接合製程將第一晶粒組501及第二晶粒組502設置於封裝基板500上。接合製程可包括熔融接合、共晶接合、金屬對金屬接合、混合接合製程等。熔融接合包括以下步驟：將晶圓的氧化層接合至另一晶圓的氧化層。在實施例中，氧化物層可以包括氧化矽。在共晶接合製程中，將兩種共晶材料放在一起，且施加特定的壓力及溫度以熔化共晶材料。在金屬對金屬接合製程中，將兩個金屬墊放置在一起，對金屬墊施加壓力及高溫以將其接合在一起。在混合接合製程中，兩個晶圓的金屬墊在高壓及高溫下接合在一起，同時兩個晶圓的氧化表面接合。
在一些實施例中，第一晶粒組501可包括經由混合接合與其他晶粒彼此堆疊的複數個晶粒。第二晶粒組502可包括經由金屬對金屬接合彼此堆疊的複數個晶粒。在實施例中，第一晶粒組501可為參考第3C圖所示及描述的晶粒組30。在實施例中，第二晶粒組502可以為參考第4圖所示及描述的晶粒組40。第一晶粒組501及第二晶粒組502均具有平坦的上表面。參看第5A圖，封裝基板包括複數個接合墊500a、500b，藉由將導電凸塊511附接至接合墊500a，第一晶粒組501覆晶(flip-chip)設置在封裝基板500上方，且藉由將導電凸塊521附接至接合墊500b，第二晶粒組502安裝在封裝基板500上。封裝基板包括用以電連接第一及第二晶粒組的複數個導電線。
第5B圖為根據實施例的第一晶粒組501的剖面圖。參看第5B圖，第一晶粒組501包括具有基板501s的第一晶粒501a、形成在基板501s上的FEOL結構501f、形成在FEOL結構501f上的BEOL結構501b、位於BEOL結構511b上的鈍化層501p，以及位於鈍化層511p上的介電層511d。在實施例中，第一晶粒511亦包括接觸墊511c及形成在接觸墊511c上的焊球511s。在實施例中，FEOL結構511f可包括具有合適材料的一或多個介電層，例如氧化矽、氮化矽、低k介電質，例如碳摻雜氧化物，極低k介電質，諸如多孔碳摻雜二氧化矽等或其組合。BEOL結構可包括一或多個金屬間介電層、圖案化金屬線及導孔。
在實施例中，第一晶粒組501亦包括具有基板511s的第二晶粒501b、形成在基板511s上的FEOL結構511f、形成在FEOL結構511f上的BEOL結構511b、形成在BEOL結構512b的表面上的介電層512d，以及介電層512d中的接合結構512b。在實施例中，第二晶粒501b藉由混合接合方式接合至第一晶粒501b，亦即，第二晶粒501b的接合結構512b的金屬表面接合至介電層511d中的接合結構511b的金屬表面，該金屬表面設置在第一晶粒501a的下表面上，且介電層512d及511d的表面接合在一起。
第5C圖為根據實施例的第二晶粒組502的剖面圖。參看第5C圖，第二晶粒組502包括堆疊在彼此頂部的複數個晶粒502a、502b、502c、502d、502e。晶粒502a、502b、502c、502d、502e經由複數個導電接合結構503彼此電連接。在實施例中，晶粒401亦包括接合結構521，形成在晶粒401a的表面上且用以將晶粒組502接合至基板500。第二晶粒組502亦包括包裝晶粒501a、501b、501c、501d及501e的模製化合物層511。
在一些實施例中，第一晶粒組501及第二晶粒組502凸塊接合至基板500。基板500、第一晶粒組501及第二晶粒組502可具有不同的熱膨脹係數(coefficient of thermal expansion，CTE)。當封裝元件50中的溫度改變時，不同的CTE會引起熱應力。
參看第5A圖，封裝元件50經受模製操作(molding operation)。在例示性模製操作中，在第一晶粒組510、第二晶粒組520及基板500上方形成模製化合物(molding compound)530。在壓縮模製(compressing molding)製程中，可以在壓縮模製機中使用液態熱固性環氧樹脂模製化合物，模製化合物可加熱至提升溫度，在該提升溫度下，模製化合物變成較低黏性液體，且圍繞第一晶粒組510及第二晶粒組520以及基板500。晶粒化合物530在冷卻時固化，然後自壓縮成型機釋放。在模製化合物530固化之後，可以執行研磨操作以移除模製化合物530的頂部分。由於環氧樹脂的CTE與矽的CTE不匹配，當環氧樹脂模製化合物黏附至晶粒組501及502時，CTE失配在晶粒組501及502上引入熱應力。在實施例中，模製化合物530包括與模製化合物層411的材料相似或實質相同的材料。在實施例中，晶粒化合物530為高導熱模製化合物，用於良好散熱。
在一些實施例中，第一晶粒組501的特徵在於第一厚度(或高度) 501T及第一熱膨脹係數CTE1，且第二晶粒組502的特徵在於第二厚度(或高度) 502T及第二熱膨脹係數CTE2。在實施例中，第二厚度502T大於第一厚度501T。在實施例中，第一晶粒組501可為系統IC (system-on-IC，SoIC)元件，而第二晶粒組502為高頻寬記憶體(high-bandwidth memory，HBM)元件。在一些實施例中，第一晶粒組包括彼此堆疊的兩(2)至十(10)個晶粒，且第二晶粒組包括彼此堆疊的三(3)至十五(15)個晶粒。本發明人觀察到，當第一晶粒組與第二晶粒組之間的厚度或高度差超過一定值時，當第一及第二晶粒組用模製化合物材料包裝時，第一晶粒會產生應力，且平坦化製程在模製化合物材料的上表面上進行。當第一晶粒組包括混合接合時，這種應力可能會很嚴重。本發明人亦發現，當第一晶粒組與第二晶粒組的厚度差大於30%時，封裝元件50容易因第一與第二晶粒組的上表面的應力不均而產生翹曲及變形。
因此，本揭露提供了一種可以有效減少封裝元件50上的應力積累的應力消除特徵。在一個實施例中，應力消除特徵用以藉由將假性晶圓(dummy wafer)(例如，載體晶圓或基板)附接至第一晶粒組的上表面來補償第一晶粒組與第二晶粒組之間的高度差。在一個實施例中，假性晶圓經由熔融接合附接至第一晶粒組的上表面。
第6圖為根據實施例的封裝元件60的簡化剖面圖。封裝元件60與封裝元件50相似，不同之處在於將應力消除特徵黏附至第一晶粒組以補償第一晶粒組與第二晶粒組之間的高度差。參看第6圖，封裝元件60包括應力消除特徵，該應力消除特徵含有安裝在第一晶粒組501的上表面的載體基板604。載體基板604具有第三厚度604T，其中第三厚度604T及第一晶粒組501的第一厚度501T的總和至少等於或大於第二厚度502T。在一些實施例中，第三厚度604T及第一厚度501T的總和在第二厚度501T的30％以內。此外，載體基板604至少包括含有介電材料607的溝槽605及包裝在介電材料607中的氣隙或空腔606。在一些實施例中，載體基板604的材料特性可與第一晶粒組501的材料特性相似。在一些實施例中，載體基板604的材料不同於模製化合物的材料，使得模製化合物不會在模製操作期間將應力傳遞或延伸至第一晶粒組。在實施例中，載體基板604的材料與第一晶粒組501的基板的材料實質相同。在實施例中，介電材料607完全圍繞氣隙或空腔606。在實施例中，介電材料607的介電常數值與FEOL或BEOL製程中的介電層的介電常數值相似。
在一些實施例中，載體基板為其上沒有形成任何電子組件的空白載體基板。載體基板可包括玻璃、陶瓷、矽、氧化矽等，氣隙完全密封在介電材料中，以防止在成型製程期間及之後殘留水分及污染物進入或殘留在氣隙中。介電材料可包括低k介電材料。在實施例中，氣隙包括空氣或真空。下面將參考第7圖及第8A圖至第8F圖詳細描述形成氣隙的製程。
在實施例中，載體基板的下表面在接合至第一晶粒組的上表面之前被平坦化以調整厚度604T。在實施例中，載體基板與第一晶粒組的接合包括熔融接合。在例示性實施例中，熔融接合包括以下步驟：將載體基板及第一晶粒組壓向彼此及執行退火製程以使載體基板及第一晶粒組由於原子吸引力而接合在一起。在實施例中，退火製程在500℃至1200℃範圍內的溫度下進行。
第7圖為根據實施例的製造載體基板的方法70的簡化流程圖。參看第7圖，方法70包括以下步驟：提供具有第一表面及與第一表面相對的第二表面的載體基板(步驟701)。在實施例中，載體基板可包括矽。圖案化罩幕形成在第一表面上且具有至少一個開口(步驟702)。至少一個開口可為橢圓形、圓形、矩形、八邊形或其他多邊形。圖案化罩幕可以由光阻劑層形成。在步驟703，使用圖案化罩幕作為蝕刻罩幕在載體基板上執行蝕刻製程以形成溝槽。蝕刻製程可以為濕式製程、乾式製程或其組合。此後，移除罩幕圖案(步驟704)。介電材料藉由電漿增強化學氣相沈積(plasma enhanced chemical vapor deposition，PECVD)形成，該PECVD的間隙填充能力較差，亦即，PECVD在溝槽的上轉角處的沈積速率高，而在溝槽底部出的沈積速率低，導致在溝槽中形成氣隙(步驟705)。介電材料可包括TEOS、SiO 2等。此後，將介電材料平坦化直至介電材料的上表面與載體基板的第一表面齊平(步驟706)。
第8A圖至第8F圖為根據實施例的製造載體基板的方法的中間階段的剖面圖。參看第8A圖及步驟701及702，提供具有上表面及下表面的載體基板801，且在載體基板的上表面形成具有至少一個開口803的圖案化罩幕802。至少一個開口803曝露出載體基板的部分上表面。參看第8B圖及步驟703，藉由使用圖案化罩幕802蝕刻作為罩幕而在載體基板801中形成溝槽804。參看第8C圖及步驟704，移除圖案化罩幕802。參看第8D圖及步驟705，藉由PECVD在載體基板的上表面形成介電材料805。由於PECVD製程的間隙填充能力較差，在溝槽的上轉角形成較厚的介電材料層，使溝槽的開口變窄。進一步繼續PECVD製程直至介電材料關閉開口，從而在溝槽中形成氣隙806。氣隙806完全密封在介電材料中，如第8E圖所示。在實施例中，可以將氣體(例如，空氣)引入蝕刻室，從而填充氣隙806。在實施例中，自蝕刻室中泵出空氣，從而在氣隙806中產生真空或接近真空。此後，參看第8F圖，對介電材料進行平坦化製程，例如化學機械研磨(chemical mechanical polishing，CMP)，使得介電材料805的上表面與載體基板801的第一表面齊平，如第8F圖所示。
第9圖為根據實施例的一種調整元件厚度的方法90的簡化流程圖。參看第9圖，方法90包括以下步驟：步驟901，提供第一晶粒組及第二晶粒組，第一晶粒組具有第一高度或厚度，且第二晶粒組具有第二高度或厚度，第二高度或厚度大於第一高度或厚度。在步驟902，方法90包括以下步驟：確定第一晶粒組與第二晶粒組之間的高度或厚度差。在實施例中，當高度差大於第二晶粒組的第二高度的特定百分比時，方法90將採取校正動作以減小高度差。在例示性實施例中，當高度差大於第二晶粒組的第二高度的30%時，方法90將採取校正動作。在步驟903，因應所確定的高度或厚度差，方法90進一步包括以下步驟：提供實質上沒有電子元件的載體基板。在實施例中，載體基板為空白矽基板。可以使用如第7圖所示的製造製程形成載體基板。在步驟904，方法90包括以下步驟：基於所確定的高度差減薄載體基板以獲得具有第三高度或厚度的減薄載體基板。在步驟905，方法90包括以下步驟：將減薄的載體基板設置於第一晶粒組的上表面，以在第二晶粒組的高度範圍內調整第一晶粒組的高度或厚度。在實施例中，方法90包括以下步驟：移除載體基板的表面部分，使得第一晶粒組的第一高度及減薄載體基板的第三高度的總和等於或大於第二晶粒組的第二高度。參考第6圖，在一些實施例中，第三高度604T及第一高度501T的總和在第二高度501T的30%以內。
返回參看第6圖，在一些實施例中，模製化合物530具有不同於封裝基板500、第一晶粒組501及第二晶粒組502的材料特性的熱膨脹係數。此外，封裝晶粒50可以與寬範圍的工作溫度內工作，例如自-40攝氏度至+150攝氏度。寬範圍的溫度會對封裝晶粒50造成熱應力。封裝基板、介電層、導電層、載體基板及模製化合物的材料特性具有隨溫度顯著變化的熱膨脹係數(coefficient of thermal expansion，CTE)。例如，矽的CTE在20攝氏度時為約2.5×10 -6/K(2.5 ppm/℃)，銅的CTE在20攝氏度時為約14 ppm/℃至19 ppm/℃，介電質的CTE在20攝氏度時為約0.5 ppm/℃至8 ppm/℃。晶粒組的整體CTE在20攝氏度時可為約2 ppm/℃至約10 ppm/℃。在-40攝氏度至+150攝氏度的溫度範圍內，模製化合物的CTE可變化超過兩個數量級。載體基板與模製化合物材料之間的大CTE差異會導致晶粒組翹曲。因IC，實施例進一步提供了可以減少或消除該熱應力的應力消除特徵。在實施例中，模製化合物530包括設置在第一晶粒組與第二晶粒組之間的至少一個空腔或空隙。
第10圖為根據實施例的封裝元件100的剖面圖。封裝元件100類似於封裝元件60，不同之處在於封裝元件100進一步包括在第一晶粒組與第二晶粒組之間的模製化合物區域中的至少一個空隙或空腔。參看第10圖，應力消除特徵進一步包括設置在第一晶粒組與第二晶粒組之間的至少一個空腔或空隙1001。在實施例中，可以基於第一晶粒組與第二晶粒組之間的厚度或高度差來調整空腔或空隙1001的尺寸。在實施例中，空腔或空隙1001的尺寸可以根據第一晶粒組與第二晶粒組之間的CTE差異進行調整。在實施例中，第一晶粒組與第二晶粒組之間的厚度或高度差為第二晶粒組的約30%或更小。在實施例中，第一晶粒組為系統積體電路(system-on-integrated circuit，SoIC)，而第二晶粒組為高頻寬記憶體(high bandwidth memory，HBM)元件。在實施例中，第一晶粒組的CTE為約2 ppm/℃至約10 ppm/℃，而第二晶粒組的CTE為約3 ppm/℃至約15 ppm/℃。
在實施例中，模製化合物包括高黏度材料，該高黏度材料藉由旋塗製程沈積在基板、第一晶粒組及第二晶粒組上。模製化合物可包括黏度高於去離子水黏度的模製材料，且可藉由旋塗製程以相對高的轉速，例如在1000 rpm及7000 rpm之間的範圍內形成。高速旋塗製程導致在第一晶粒組與第二晶粒組之間形成空隙。在一些實施例中，控制或調整旋塗的轉速以獲得模製化合物材料中空隙的目標密度及尺寸，從而降低封裝元件中具有失配CTE的晶粒的熱應力。在一些實施例中，模製化合物可包括有機聚合物、陶瓷、玻璃、塑膠等。
第11圖為根據實施例的具有應力消除結構的封裝元件110的剖面圖。封裝元件110類似於第10圖的封裝元件100，不同之處在於示出了更詳細的排列及元素(例如，第一晶粒組中的晶粒混合接合、載體基板與第一晶粒組之間的熔融接合、第二晶粒組的金屬對金屬接合及模製封裝結構)。參看第11圖，封裝元件110包括覆晶接合至基板1100的第一晶粒組1101及第二晶粒組1102。在實施例中，第一晶粒組1101及第二晶粒組1102均包括用以接合至基板1100的凸塊。凸塊可為焊球、導電凸塊、球柵陣列等。
第一晶粒組1101可類似於第3C圖的晶粒組30或第5B圖的晶粒組501，而第二晶粒組1102可類似於第4圖的晶粒組40或第5C圖的晶粒組502。在實施例中，第一晶粒組1101包括設置在第一平面水平中的第一晶粒1101a、第二晶粒1101b及設置在第二平面水平中的第三晶粒1101c，其中第二晶粒及第三晶粒經由在約100℃至200℃的溫度及約0.7巴至約10巴的壓力下接合的貫穿基板導孔1107及氧化物對氧化物(介電)層1104藉由金屬對金屬接合而混合接合至第一晶粒1101a。在一些實施例中，假性層1105設置在第二平面水平中且用以當第二平面水平沒有足夠的晶粒密度時向第二平面水平提供機械穩定性。第一晶粒組1101亦包括圍繞第一平面水平中的第一晶粒1101a以及第二平面水平中的第二晶粒1101b及第三晶粒1101c的圍繞晶粒介電層(例如，TEOS、SiO 2) 1108。第一晶粒組1101亦包括圍繞第一晶粒1101a、第二晶粒1101b及第三晶粒1101c中的每一者的密封環1109且用以防止水分進入晶粒。
在實施例中，第二晶粒組1102包括經由導電接合結構1112彼此接合的第一晶粒1102a、第二晶粒1102b、第三晶粒1102c及第四晶粒1102d。在實施例中，第一、第二、第三及第四晶粒電連接且機械連接至複數個導電接合結構1113。第二晶粒組1102亦包括包裝晶粒1110a至1110d且填充晶粒之間的氣隙的模製化合物層1115。
第一晶粒組1101及第二晶粒組1102可具有不同的高度(厚度)及CTE。當第一晶粒組及第二晶粒組封裝在模製化合物中時，第一晶粒組與第二晶粒組之間的高度差可能對具有較小高度的晶粒組引起不均勻的頂部應力。本發明人發現，當高度差大於第二晶粒組的一定百分比高度範圍時，模製應力會導致第一晶粒組翹曲及分層。本發明人在此提供了一種解決方案，藉由在第一晶粒組1101的上表面安裝載體基板1140來補償高度差，從而降低第一晶粒組的不均勻頂部應力。
參看第11圖，載體基板1140包括具有至少一個溝槽1145的矽基板、溝槽中的介電材料1147以及完全包裝在介電材料1147中的至少一個氣隙1146。在實施例中，載體基板1140具有以第一晶粒組與第二晶粒組之間的高度或厚度差為特徵的厚度或厚度。在實施例中，第一晶粒組具有第一厚度，第二晶粒組具有第二厚度，且載體基板的厚度與第一晶粒組的第一厚度的總和等於或大於第二晶粒組的厚度。載體基板1140及第一晶粒組1101熔融接合在一起。在一些實施例中，載體基板1140可包括玻璃基板、石英、樹脂、矽基板。在一些實施例中，載體基板1140可以使用黏附層附接至第一鈍化層的頂表面。載體基板可以減輕施加至第一晶粒組的機械應力及熱應力。載體基板可支撐晶粒組不翹曲。參看第7圖至第9圖描述了包括封裝氣隙及厚度調整的載體基板的製造製程，為簡潔起見，此處省略詳細描述。
仍然參看第11圖，封裝元件110亦包括位於基板1100上且覆蓋第一晶粒組1101及第二晶粒組1102的包裝層1130。包裝層1130包括設置在第一晶粒組與第二晶粒組之間的包裝區中的空腔1131且用以補償第一晶粒組與第二晶粒組的CTE失配。在實施例中，空腔1301的尺寸可以根據第一晶粒組與第二晶粒組之間的CTE差異進行調整。在實施例中，包裝層1130可包括類似於參看第5A圖描述的模製化合物530的模製材料。在實施例中，包裝層1130可包括黏度高於去離子水的有機聚合物、陶瓷、玻璃、塑膠。在實施例中，空腔1131可以藉由旋塗製程以相對高的轉速形成，從而導致在第一晶粒組與第二晶粒組之間形成的空隙。在一些實施例中，控制或調整旋塗的轉速以獲得模製化合物中空隙的目標密度及尺寸，從而降低封裝元件110中具有失配CTE的晶粒的熱應力。
本揭示內容的實施例提供一種封裝元件，具有用於降低封裝元件的熱應力的應力消除特徵。在實施例中，封裝包括基板、接合至基板的第一晶粒組、附接至第一晶粒組且含有至少一個氣隙的載體基板，以及與第一晶粒組間隔開且接合至基板的第二晶粒組。
本揭示內容的實施例提供了一種半導體元件。該半導體元件包括封裝基板、接合至封裝基板且以第一厚度為特徵的第一晶粒組、接合至封裝基板且以第二厚度為特徵的第二晶粒組，以及位於第一晶粒組上且以第三厚度為特徵的載體基板，該第三特徵為第一厚度與第二厚度之間的差的函數。
本揭示內容的實施例亦提供了一種形成封裝元件的方法。該方法包括以下步驟：提供第一晶粒組及第二晶粒組；確定第一晶粒組及第二晶粒組之間的高度差；因應確定的高度差，提供載體基板，該載體基板實質上沒有電子元件；基於高度差減薄載體基板以獲得減薄的載體基板，且將減薄的載體基板設置於第一晶粒組以形成高度在第二晶粒組的高度範圍內的高度調整的第一晶粒組。
上文僅概述了本揭示內容的實施例的特徵。鑒於本文的教示，對所描述的實施例的各種修改和替代對於熟習此項技術者而言將是顯而易見的。熟習此項技術者將理解，等效構造不脫離本揭示內容的範圍，且在不脫離本揭示內容的精神及範圍的情況下，可以在本文中進行各種變化、替換及變更。
10:晶粒 20、30、40:晶粒組 50、60、100:封裝元件 70、90:方法 101:半導體基板 102:主動元件 103:層間介電層 104:金屬間介電層 105:金屬線及導孔 106:金屬墊 107:鈍化層 108:密封環 109:接觸墊 110:貫穿基板導孔 111:介電層 201:基板 202:主動區 203:介電層 204:金屬導孔 206:頂部金屬間層 207:鈍化層 208、303c、304、308:導孔 209:側金屬互連結構 210:堆疊晶粒結構 211~213:堆疊晶粒 301a:第一晶粒 301b:第一晶粒 301c:第三晶粒 303:互連結構 303a:介電層 303b:金屬線 309:電連接器 310:導電凸塊 315a:第一接合介電層 315b:第二接合介電層 316a:第一導電接觸結構 316b:第二導電接觸結構 317:接合層 320:密封環 330:接合介電層 401a~401e:晶粒 402:導電部件 403:導電接合結構 405:接合結構 410:基板 411:模製化合物層 500:封裝基板 500a、500b:接合墊 501:第一晶粒組 501a:第一晶粒 501b:BEOL結構 501d:介電層 501f:FEOL結構 501p:鈍化層 501s:基板 501T:第一厚度 502:第二晶粒組 502a~502f:晶粒 502T:第二厚度 503:導電接合結構 511:導電凸塊 511b:BEOL結構 511c:接觸墊 511d:介電層 511f:FEOL結構 511p:鈍化層 511s:焊球 512b:接合結構 512d:介電層 521:導電凸塊 530:模製化合物 604:載體基板 604T:第三厚度 605:溝槽 606:空腔 607:介電材料 701~706:步驟 801:載體基板 802:圖案化罩幕 803:開口 804:溝槽 805:介電材料 806:氣隙 901~905:步驟 1001:空腔或空隙 1100:基板 1101:第一晶粒組 1101a:第一晶粒 1101b:第二晶粒 1101c:第三晶粒 1102:第二晶粒組 1102a:第一晶粒 1102b:第二晶粒 1102c:第三晶粒 1102d:第四晶粒 1104:介電層 1105:假性層 1107:貫穿基板導孔 1108:晶粒介電層 1109:密封環 1112:導電接合結構 1113:導電接合結構 1115:模製化合物層 1130:封裝層 1131:空腔 1140:載體基板 1145:溝槽 1146:氣隙 1147:介電材料 FEOL:前段製程 BEOL:後段製程
結合附圖，根據以下詳細描述可以最好地理解本揭示內容。應注意，根據產業中的標準實務，各種特徵未按比例繪製。實際上，為了討論清楚起見，各種特徵的尺寸可任意增加或減小。 第1圖為根據一些例示性實施例的晶粒的簡化剖面圖。 第2圖為根據一些例示性實施例的具有彼此堆疊的複數個晶粒的晶粒組20的剖面圖。 第3A圖為根據一些實施例的以三維(three-dimensional，3D)組態彼此堆疊的複數個晶圓的簡化立體圖。 第3B圖為第3A圖的堆疊晶圓組態的簡化立體圖。 第3C圖為根據例示性實施例的包括複數個堆疊晶粒的單一晶粒組30的簡化立體圖。 第4圖為根據例示性實施例的包括複數個堆疊晶粒的晶粒組40的簡化剖面圖。 第5A圖為根據實施例的封裝元件的簡化剖面圖。 第5B圖為根據實施例的第一晶粒組的剖面圖。 第5C圖為根據實施例的第二晶粒組的簡化剖面圖。 第6圖為根據實施例的封裝元件的簡化剖面圖。 第7圖為根據實施例的製造載體基板的方法的簡化流程圖。 第8A圖至第8F圖為根據實施例的製造載體基板的方法的中間階段的簡化剖面圖。 第9圖為根據實施例的調整元件厚度的方法的簡化流程圖。 第10圖為根據實施例的封裝元件的簡化剖面圖。 第11圖為根據實施例的具有應力消除結構的封裝元件的簡化剖面圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
90:方法
901~905:步驟

Claims (20)

  1. 一種封裝，包含： 一基板； 一第一晶粒組，包含一第一組一或多個晶粒，該第一晶粒組接合至該基板； 一載體基板，附接至該第一晶粒組且在該載體基板內包含至少一個氣隙；及 一第二晶粒組，包含一第二組一或多個晶粒，該第二晶粒組與該第一晶粒組分開且不同，且接合至該基板，其中該第一晶粒組具有與該第二晶粒組相同的高度或實質相同的高度。
  2. 如請求項1所述之封裝，更包含一封裝層，位於該基板上且覆蓋該第一晶粒組及該第二晶粒組，其中該封裝層包含設置在該第一晶粒組與該第二晶粒組之間的一空腔。
  3. 如請求項2所述之封裝，其中該封裝層包含一有機聚合物。
  4. 如請求項1所述之封裝，其中該第二晶粒組包含： 複數個晶粒，堆疊在彼此的頂部且由一模製化合物材料封裝。
  5. 如請求項1所述之封裝，其中該載體基板的一厚度的特徵在於該第一晶粒組的一第一厚度與該第二晶粒組的一第二厚度之間的一差。
  6. 如請求項1所述之封裝，其中該第一晶粒組的特徵在於一第一厚度，該第二晶粒組的特徵在於一第二厚度，該載體基板的特徵在於一第三厚度，其中該第一厚度及該第三厚度的一總和等於或大於該第二厚度。
  7. 如請求項1所述之封裝，其中該第一晶粒組包含彼此混合接合的一第一晶粒及一第二晶粒。
  8. 如請求項1所述之封裝，其中該載體基板熔融接合至該第一晶粒組。
  9. 如請求項1所述之封裝，其中該載體基板包含填充有以介電材料的至少一個溝槽，且該至少一個氣隙完全封裝於該介電材料中。
  10. 一種半導體元件，包含： 一封裝基板； 一第一晶粒組，接合至該封裝基板，該第一晶粒組的特徵在於一第一厚度； 一第二晶粒組，接合至該封裝基板，該第二晶粒組的特徵在於一第二厚度； 一載體基板，位於該第一晶粒組上且特徵在於一第三厚度，該第三厚度為該第一厚度與該第二厚度之間的一差的一函數；及 一模製化合物材料，位於該封裝基板上且覆蓋該第一晶粒組及該第二晶粒組，該模製化合物材料包含位於該第一晶粒組與該第二晶粒組之間的一空腔。
  11. 如請求項10所述之半導體元件，其中該載體基板包含一溝槽。
  12. 如請求項11所述之半導體元件，其中該載體基板進一步包含： 一介電材料，位於該溝槽中；及 一氣隙，封裝於該介電材料中。
  13. 如請求項10所述之半導體元件，其中該第三厚度及該第一厚度的一總和在該第二厚度的30%內。
  14. 如請求項10所述之半導體元件，其中該第一厚度及該第三厚度的一總和等於或大於該第二厚度。
  15. 如請求項10所述之半導體元件，其中該第一晶粒組及該載體基板彼此熔融接合。
  16. 一種形成一封裝元件的方法，包含： 提供一第一晶粒組及一第二晶粒組； 確定該第一晶粒組與該第二晶粒組之間的一高度差； 因應該確定的高度差提供一載體基板，該載體基板沒有電子元件； 基於該高度差減薄該載體基板，得到一減薄的載體基板；及 將該減薄的載體基板設置於該第一晶粒組以形成一高度調整的第一晶粒組，該高度調整的第一晶粒組具有在該第二晶粒組的一高度範圍內的一高度。
  17. 如請求項16所述之方法，更包含： 將該高度調整的第一晶粒組及該第二晶粒組設置於一封裝基板上；及 在該封裝基板上形成覆蓋該高度調整的第一晶粒組及成型材料第二晶粒組的一模製材料，其中該模製材料包含該高度調整的第一晶粒組與該第二晶粒組之間的一空腔。
  18. 如請求項16所述之方法，其中： 該第一晶粒組具有一第一高度； 該第二晶粒組具有一第二高度； 該減薄的載體基板具有一第三高度；且 該第一高度及該第三高度的一總和等於或大於該第二高度。
  19. 如請求項16所述之方法，其中將該減薄的載體基板設置於該第一晶粒組之步驟包含：熔融接合。
  20. 如請求項16所述之方法，其中該載體基板包含： 至少一個溝槽； 一介電材料，位於該至少一個溝槽中；及 一氣隙，位於該至少一個溝槽中且完全封裝於該介電材料中。
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