TWI606587B - 碳摻雜半導體元件 - Google Patents

碳摻雜半導體元件 Download PDF

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TWI606587B
TWI606587B TW103109713A TW103109713A TWI606587B TW I606587 B TWI606587 B TW I606587B TW 103109713 A TW103109713 A TW 103109713A TW 103109713 A TW103109713 A TW 103109713A TW I606587 B TWI606587 B TW I606587B
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semiconductor layer
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TW201448208A (zh
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凱勒斯塔夏
史文森布萊恩Ｌ
費希滕寶尼可拉斯
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全斯法姆公司
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Description

碳摻雜半導體元件
本揭示案大體而言係關於製造半導體元件，且特定言之，係關於碳摻雜半導體元件。
用於電力電子應用中之許多電晶體已用矽(Si)半導體材料製造。用於電力應用之普通電晶體元件包括Si低導通電阻功率電晶體(CoolMOS)、Si電力金屬氧化物半導體場效電晶體(Power MOSFET)及Si絕緣閘雙極電晶體(Insulated Gate Bipolar Transistor；IGBT)。儘管Si功率元件並不昂貴，但該等元件有許多缺點，包括相對低之切換速度及高位準之電雜訊。最近，碳化矽(SiC)功率元件由於該等元件之優越特性而被考慮。現III族氮化物或III-N半導體元件(諸如，基於氮化鎵(GaN)之元件)正作為有吸引力之候選物脫穎而出，以承載大電流、支援高電壓及提供非常低之導通電阻及快速切換時間。
在一個態樣中，一種用於製造半導體元件之方法可包括：在反應器中形成III-N半導體層；及在形成III-N半導體 層時將烴前驅物注入至反應器內，從而碳摻雜III-N半導體層及使III-N半導體層絕緣或半絕緣。
在第二態樣中，一種半導體元件可包括基板及在基板上之碳摻雜絕緣或半絕緣III-N半導體層。III-N半導體層中之碳摻雜密度大於1×1018cm-3、5×1018cm-3或1×1019cm-3，及III-N半導體層中之差排密度小於2×109cm-2。
在第三態樣中，一種用於形成半導體材料結構之方法可包括：在反應器中於基板上形成第一III-N半導體層；及在形成第一III-N半導體層時，將烴前驅物注入至反應器內，從而碳摻雜第一III-N半導體層及使第一III-N半導體層絕緣或半絕緣。該方法可進一步包括在第一III-N半導體層上形成第二III-N材料層，其中第二III-N材料層具有實質上比該第一III-N材料層低之碳濃度。
在第四態樣中，一種材料結構可包括在異質基板上之第一III-N半導體層及在第一III-N材料結構之與該異質基板相對之一側上之第二III-N半導體層，第二III-N半導體層比第一III-N半導體層薄。第一III-N半導體層貫穿該層可具有大於1×1018cm-3之碳濃度，及貫穿第二III-N半導體層之碳濃度可小於貫穿第一III-N半導體層之碳濃度。此外，第二III-N材料層之與基板相對之表面可具有小於5個特徵結構每平方公分之目視特徵結構密度，其中目視特徵結構中之每一者具有大於100奈米之平均高度。
在第五態樣中，一種材料結構可包括在異質基板上之第一III-N半導體層及第一III-N材料結構之與異質基板相對 之一側上之第二III-N半導體層，第二III-N半導體層比第一III-N半導體層薄。第一III-N半導體層可為具有大於1×1018cm-3之碳濃度之絕緣或半絕緣層。第二III-N半導體層之碳濃度可小於第一III-N半導體層之碳濃度，及在第二III-N半導體層之與異質基板相對之表面處之差排密度可小於2×109cm-2。
本文所述之方法及元件可各自包括以下特徵中之一或多者。注入烴前驅物可包含注入具有化學式(CxHy)之烴前驅物，其中x及y為大於或等於1之整數。在基板上形成III-N半導體層可包含在矽基板上於III-N成核層上形成III-N半導體層以作為III-N緩衝層。該等方法可包含在III-N緩衝層之上形成III-N溝道層及在III-N溝道層之上形成III-N障壁層，從而鄰近於溝道層與障壁層之間的界面形成二維電子氣(2DEG)主動溝道。形成III-N半導體層以作為III-N緩衝層可包含在複數個生長條件下形成III-N緩衝層，且形成III-N溝道層可包含在該等相同或實質上相同的生長條件下形成III-N溝道層。複數個生長條件可包含表面溫度及反應器壓力。複數個生長條件進一步可包含III族前驅物流動速率與V族前驅物流動速率之比率。在基板上形成III-N半導體層可包含藉由金屬有機化學氣相沉積(metal organic chemical vapor deposition；MOCVD)形成III-N半導體層。障壁層可包含AlGaN，溝道層可包含無摻雜或無意摻雜(unintentionally doped；UID)GaN，且緩衝層可包含AlGaN或GaN或上述兩者。
形成III-N半導體層可包含以III族前驅物莫耳流動速率將III族前驅物注入至反應器中，及將烴前驅物注入至反應器中可包含以烴前驅物莫耳流動速率將烴前驅物注入至反應器中，其中烴前驅物莫耳流動速率至少為III族前驅物莫耳流動速率之0.02倍。形成III-N半導體層可包含以III族前驅物莫耳流動速率將III族前驅物注入至反應器中，及將烴前驅物注入至反應器中可包含以烴前驅物莫耳流動速率將烴前驅物注入至反應器中，其中該烴前驅物莫耳流動速率大於III族前驅物莫耳流動速率。烴前驅物可包含丙烷或甲烷或上述兩者。該等方法可進一步包含向半導體元件添加閘極端子、汲極端子及源極端子，從而形成III-N高電子遷移率電晶體(high electron mobility transistor；HEMT)。該等方法可進一步包含向半導體元件添加陽極端子及陰極端子，從而形成III-N二極體。使III-N半導體層絕緣或半絕緣可包含使III-N半導體層具有至少1×105Ω.cm或1×107Ω.cm之電阻率。碳摻雜III-N半導體層可導致III-N半導體層具有大於1×1018cm-3之碳濃度。烴前驅物可在形成第一III-N材料層時而不是在形成第二III-N材料層時注入至反應器。
III-N半導體層可具有在基板遠端之第一側及在第一側與基板之間的第二側，其中III-N半導體層中之差排密度為鄰近於III-N半導體層之第一側之差排密度。III-N半導體層可包含在III-N成核層上之III-N緩衝層，其中基板為矽基板。元件可進一步包含在III-N緩衝層上之III-N溝道層及在III-N溝道層上之III-N障壁層，從而鄰近溝道層與障壁層之間的界 面形成二維電子氣(2DEG)主動溝道。障壁層可包含AlGaN，溝道層可包含無摻雜或無意摻雜(UID)GaN，且緩衝層可包含AlGaN或GaN或上述兩者。基板可為異質基板。元件可進一步包含閘極端子、汲極端子及源極端子，其中半導體元件為III-N高電子遷移率電晶體(HEMT)。元件可進一步包含陽極端子及陰極端子，其中半導體元件為III-N二極體。III-N半導體層中之碳摻雜密度可小於5×1021cm-3。
第二III-N材料層之與基板相對之表面可具有小於5個特徵結構每平方公分之目視特徵結構密度，其中目視特徵結構中之每一者具有大於100奈米之平均高度。第一III-N半導體層與第二III-N半導體層之組合厚度可小於6微米，例如，小於5微米、小於4微米或小於3微米。第二III-N材料層比第一III-N材料層薄。
本說明書中所述之標的物之特定實施例可經實施以實現以下優點中之一或多者。相較於習知技術，絕緣或半絕緣碳摻雜III-N層可在對層之一或多個生長參數之較少約束的情況下以根據廣泛濃度範圍(1e16cm-3至1e22cm-3)之碳摻雜位準形成。絕緣或半絕緣層可經形成具有低差排密度及生長在異質基板(例如Si或SiC基板)上之平滑表面。在金屬有機化學氣相沉積(MOCVD)期間注入無鹵素前驅物(例如，烴前驅物)可降低或消除含鹵素分子與金屬有機前驅物之相互作用，從而避免在碳摻雜AlGaN之MOCVD生長期間CX4(X=鹵素)前驅物對合金組成物(亦即，AlGaN中Al與Ga之比率)之影響。
100‧‧‧III族氮化物半導體元件
102‧‧‧基板
104‧‧‧成核層
106‧‧‧緩衝層
108‧‧‧III-N溝道層
110‧‧‧III-N障壁層
112‧‧‧二維電子氣
114‧‧‧源極
116‧‧‧汲極
118‧‧‧閘極
200‧‧‧示例性方法
202‧‧‧矽基板
204‧‧‧成核層
206‧‧‧反應器
208‧‧‧緩衝層
210‧‧‧溝道層
212‧‧‧III-N材料層結構
300‧‧‧系統
302‧‧‧反應器
304‧‧‧基板
306‧‧‧III-N層
308‧‧‧反應器控制系統
310‧‧‧壓力控制模組
312‧‧‧沉積溫度控制模組
314‧‧‧生長速率模組
316‧‧‧載體氣體
318‧‧‧V族前驅物氣體
320‧‧‧III族前驅物氣體
322‧‧‧烴前驅物氣體
402‧‧‧基板
404‧‧‧成核層
406‧‧‧緩衝層
418‧‧‧附加層
420‧‧‧III-N材料結構
500‧‧‧目視特徵結構
502‧‧‧平均直徑
504‧‧‧平均高度
520‧‧‧III-N材料結構
第1A圖及第1B圖為示例性III-N半導體元件之橫截面視圖。
第2圖為用於製造包括碳摻雜層之III-N半導體元件之示例性方法之流程圖。
第3圖為用於製造具有經碳摻雜之至少一個層之III-N半導體元件之系統之方塊圖。
第4圖為示例性III-N半導體材料結構之橫截面視圖。
第5A圖及第5B圖分別為形成在III-N材料結構之表面上之目視特徵結構之橫截面示意圖及平面示意圖。
在各種圖式中相同元件符號指示相同元件。
第1A圖為示例性III族氮化物(亦即，III-N)半導體元件100之橫截面視圖。舉例而言，元件可藉由向元件添加源極114端子、汲極116端子及閘極118端子(如在第1B圖中所示)而成為電晶體，例如III-N高電子遷移率電晶體(HEMT)。在另一實例中，元件可藉由向元件添加陽極端子及陰極端子(未圖示)而成為二極體。
元件包括基板102。基板可為(例如)矽、SiC、氮化鋁(AlN)、GaN、藍寶石(Al2O3)或用於III-N材料之生長之任意其他合適生長基板。因大的天然基板(亦即，由III-N材料形成之基板)當前難以獲得且趨於非常昂貴的，故元件通常形成在異質基板(亦即，由並非III-N材料之材料形成之基板)上，諸如矽、碳化矽或藍寶石。元件包括在基板上之 成核層104。成核層可為III-N成核層及可包括，例如AlN。
元件可包括緩衝層106。緩衝層可為III-N緩衝層及可包括，例如，C摻雜AlGaN或GaN或上述兩者。緩衝層可包括若干不同層，例如，一些層更接近基板及具有較高Al濃度，而一些層距離基板較遠及具有較低Al濃度。緩衝層可藉由碳摻雜緩衝層而製成絕緣的或半絕緣的。此舉可有用於(例如)防止表面下之洩露或過早崩潰。
元件包括III-N溝道層108及III-N障壁層110，其中溝道層及障壁層之組成物經選擇以誘發鄰近於溝道層與障壁層之間的界面的二維電子氣(2DEG)112主動溝道。舉例而言，溝道層可包括無摻雜或無意摻雜(UID)GaN，且障壁層可包括AlGaN。
術語III族氮化物或III-N材料、層、元件及結構可指根據化學計量通式BwAlxInyGazN由化合物半導體材料組成之材料、元件或結構，其中w+x+y+z約為1，且w、x、y及z各自大於或等於零且小於或等於1。在III族氮化物或III-N元件中，導電溝道可部分或整體包含在III-N材料層內。
元件之層可藉由在反應器中之分子束磊晶(molecular beam epitaxy；MBE)或金屬有機化學氣相沉積(MOCVD)或其他技術來形成。實現在以NH3作為氮前驅物藉由MOCVD形成之III-N層中之碳摻雜的一種方式為調節層生長條件以使得來自金屬有機前驅物(例如，TMGa或TMAl或上述兩者)之碳併入層中。舉例而言，有利於碳併入之一些生長條件包括：低反應器壓力、低NH3分壓、低沉積溫度及高生長速率。
當為足以使層絕緣或半絕緣以用於某些應用之位準的碳摻雜而實施該等生長條件時，該等生長條件受限以相對於層之其他特徵(例如，層之螺旋差排密度及表面粗糙度)校準。舉例而言，考慮形成在異質(亦即，非III-N)基板(例如，矽(Si)、碳化矽(SiC)或藍寶石(Al2O3))上之層。
此類層可在包括較低反應器壓力、較低NH3分壓、較低沉積溫度及較高生長速率中之一或多者之生長條件下形成，但該等生長條件亦可導致層中之較高差排密度及較高位準之點缺陷。使用該等方法將碳摻雜位準增加至大於約5×1018cm-3(及在一些情況下大於8×1017cm-3)可附加地導致表面粗糙或不良表面形態或上述兩者。
實現層中之碳摻雜之另一方式為在層之生長期間將烴前驅物注入至反應器。烴前驅物包括化學組成物(CxHy)之分子，其中x及y為大於或等於1之整數。烴之實例包括丙烷(C3H8)、甲烷(CH4)及C2H2。
實現碳摻雜之此方式可導致層具有超過1×1018cm-3、5×1018cm-3、1×1019cm-3或3×1019cm-3之碳摻雜同時具有小於2×109cm-2(例如，約1×109cm-2或更小或約8×108cm-2或更小)之差排密度。III-N半導體層中之碳摻雜密度可在1×1019cm-3與5×1021cm-3之間，或在1×1018cm-3與5×1021cm-3之間。在一些實施方式中，成核層之厚度介於20nm至50nm之間，緩衝層之厚度介於1微米至10微米之間(例如，約5微米)，溝道層之厚度為約200nm至1000nm(通常約400nm)，且障壁層之厚度介於10nm至40nm之間(例如， 約25nm)。
第2圖為用於製造包括碳摻雜層之III-N半導體元件之示例性方法200之流程圖。為說明之目的，將參考第1圖之示例性元件100描述方法，但該方法可用於製造其他元件及用於碳摻雜其他元件中之其他類型之層。
成核層形成在矽基板(202)上。舉例而言，矽基板可置入反應器(諸如MOCVD反應器)中，且成核層可(例如，作為AlN層)沉積在反應器內。
緩衝層形成在成核層(204)上。舉例而言，緩衝層可沉積例如，以作為AlGaN或GaN或上述兩者之層。在一些實施方式中，緩衝層包含超過一個層。AlGaN層經沉積在每一連續層中具有減少量之Al。最後，一或多個GaN層可經沉積。
當緩衝層形成時，烴前驅物經注入至反應器(206)。舉例而言，烴前驅物可在將III族及/或V族前驅物注入至反應器時同時或交替注入至反應器。
溝道層形成在緩衝層(208)上。舉例而言，溝道層可經沉積，例如，以作為無摻雜或無意摻雜(UID)GaN層。在一些實施方式中，溝道層在與緩衝層相同或實質上相同之生長條件下形成。在緩衝層包括最高位準之GaN層之情況下，溝道層可藉由中斷注入烴前驅物及在不改變反應器中之任意其他生長條件之情況下繼續沉積GaN來沉積。換言之，反應器壓力及/或溫度及/或至反應器中之總氣體莫耳流動速率及/或V族前驅物莫耳流動速率與III族前驅物莫耳流動速 率之比率對於溝道層及對於緩衝層之直接鄰近於溝道層之部分而言可能相同，其中烴前驅物在緩衝層之直接鄰近於溝道層之部分之生長期間而不是在溝道層之生長期間注入至反應器。
障壁層形成在溝道層(210)上。舉例而言，障壁層可經沉積(例如)以作為AlGaN層。鄰近於溝道層與障壁層之間的界面誘發二維電子氣(2DEG)主動溝道。障壁層可具有比溝道層大之帶隙，此帶隙又可至少部分地在溝道層中誘發2DEG。為形成電晶體，源極端子、閘極端子及汲極端子隨後形成在III-N材料層結構(212)上。或者，為形成二極體，陽極端子及陰極端子隨後形成在III-N材料層結構(未圖示)上。
第3圖為用於製造具有經碳摻雜之至少一個層之III-N半導體元件之系統300的方塊圖。系統可用於(例如)執行第2圖之方法以製造第1A圖及第1B圖之元件。
系統包括反應器302，例如MOCVD反應器。基板304置入反應器中且III-N層306形成在基板上。反應器控制系統308藉由調節一或多個生長條件來控制層306之形成。反應器控制系統可控制一或多種材料至反應器中之注入，該等材料包括載體氣體316(例如，惰性載體氣體，諸如H2或N2或上述兩者)、V族前驅物氣體318(例如，NH3)、III族前驅物氣體320(例如，TMGa或TMAl或上述兩者)及烴前驅物氣體322(例如，C3H8、CH4及C2H2中之一或多者)。
反應器控制系統可(例如)作為一或多個電腦之系統 實施，該系統自操作者接收輸入及(例如)向反應器及氣體之儲存模組提供輸出控制訊號。例如，反應器控制系統可包括壓力控制模組310(例如，以控制反應器中之壓力)、沉積溫度控制模組312(例如，以控制形成之層之表面溫度)、生長速率模組314及其他模組。生長速率模組314可藉由控制影響生長速率之變數(諸如，反應器壓力、表面溫度及各種前驅物及載體氣體之流動速率)而間接控制生長速率。
在一些實施方式中，反應器控制系統經組態以藉由以III族前驅物莫耳流動速率將III族前驅物注入至反應器中及藉由以烴前驅物莫耳流動速率將烴前驅物注入至反應器來形成III-N半導體層。層中碳摻雜之量可藉由改變烴前驅物莫耳速率與III族前驅物莫耳流動速率之間的比率來至少部分地控制。
已發現，對用於在III-N材料之MOCVD生長期間之III-N材料之碳摻雜的一些烴前驅物而言，特定言之對於丙烷(C3H8)而言，摻雜物併入效率比通常在III-N材料之MOCVD生長期間引入之其他摻雜物之併入效率低得多。舉例而言，對於摻雜物(諸如，矽)而言，在矽烷或二矽烷用作矽前驅物之情況下，當矽前驅物莫耳流動速率與III族前驅物莫耳流動速率之比率為約1/1000(及在一些情況下甚至更低)時，III-N材料中之矽摻雜位準約等於III-N材料中之摻雜物之飽和位準，該位準可為約1×1021cm-3。使矽前驅物莫耳流動速率相對於III族前驅物莫耳流動速率增加至更高值實質上不增加層中之電性主動矽之濃度，及通常導致所得III-N層之更加 不良的結構品質，例如，導致較高差排及點缺陷密度以及不良表面形態。然而，對於在MOCVD生長期間使用丙烷作為碳前驅物之III-N材料之碳摻雜而言，當在不存在丙烷前驅物之情況下在對應於低碳摻雜位準(例如，小於1×1017cm-3)之反應器條件下執行生長時，以III族前驅物莫耳流動速率之約1/1000之莫耳流動速率添加丙烷實質上不增加III-N材料中之碳摻雜，及仍通常獲得小於1×1017cm-3之碳摻雜位準。
在一些系統中，且特定而言當丙烷(C3H8)用作烴前驅物時，可能需要約為或至少為III族前驅物莫耳流動速率之0.02倍之烴前驅物莫耳流動速率，以便層中之碳摻雜位準在約1×1017cm-3與1×1019cm-3之間或超過1×1017cm-3。在一些系統中，當烴前驅物莫耳流動速率約為或至少為III族前驅物莫耳流動速率之0.02倍時，層中之碳摻雜位準可為約1×1018cm-3或超過1×1018cm-3或在約1×1018cm-3與1×1020cm-3之間。在一些系統中，當烴前驅物莫耳流動速率實質上大於III族前驅物莫耳流動速率，例如為III族前驅物莫耳流動速率之2倍或20倍或200倍或2000倍或20,000倍時，層中之碳摻雜位準可為約或超過1×1018cm-3或1×1019cm-3或1×1020cm-3。對於約1e18cm-3或更大之碳摻雜位準而言，用丙烷前驅物形成之碳摻雜層之電阻率可大於1×105Ω.cm，或對於約1×1019cm-3或更大之碳摻雜位準而言大於1×107Ω.cm，或對於約1×1020cm-3或更大之碳摻雜位準而言大於1×108Ω.cm。
在一些實施方式中，反應器控制系統經組態以在1077℃之表面溫度及200mBarr之壓力下形成至少一個層(例如， UID GaN溝道層)。反應器控制系統使氮前驅物(例如，氨(NH3))以0.54mol/min之速率流入反應器中、使三甲基鎵(TMGa)以0.65mmol/min之速率流入反應器中及控制至反應器中之總氣體流量至80公升每分鐘或約80公升每分鐘。反應器控制系統可藉由增加或降低載體氣體流量以補償其他流量之增加或減少而將總氣體流量維持在實質上恆定之速率下。此情況導致此層中之約5×1016cm-3或更低之碳摻雜。
反應器控制系統可藉由使烴前驅物流入反應器中而在相同或實質上相同之生長條件下形成碳摻雜層。舉例而言，對於碳摻雜層而言，若藉由使烴前驅物流入反應器中而將表面溫度維持在1077℃、壓力維持在200mBarr、氨流動速率維持在0.54mol/min、TMGa流動速率維持在0.65mmol/min及流入反應器中之總氣體流動速率維持在約80公升每分鐘，則可實現大於1×1018cm-3、大於5×1018cm-3、大於1×1019cm-3或大於1×1020cm-3之碳摻雜位準。同時，若碳摻雜III-N層形成在異質基板(諸如，矽)上，則碳摻雜III-N層之上部分(亦即，鄰近於碳摻雜III-N層之距離基板最遠之表面之部分)之差排密度可維持在小於2×109cm-2及通常甚至小於1×109cm-2之位準下，即使在結構中之III-N層之總厚度小於6微米、小於5微米、小於4微米或小於3微米之情況下亦如此。
藉助於比較，當烴前驅物不在碳摻雜層之生長期間流入反應器時，反應器控制系統可調節一或多個或全部生長參數以併入足夠碳來使碳摻雜層絕緣至指定程度。舉例而言， 反應器控制系統可降低壓力至50mBarr、降低溫度至1020℃、降低NH3流動速率至0.045mol/min、維持總氣體流量為約80公升每分鐘及維持III族前驅物氣體之流量。
對生長條件之該等調節可導致碳摻雜高達約5×1018cm-3。當層在該等條件下生長時，層之上表面處之差排密度可大於2×109cm-2，且通常在5×109cm-2與6×109cm-2之間。進一步調節反應器條件以進一步增加彼等層中之碳濃度可使材料結構之表面形態實質降級，並通常亦導致甚至更高之差排密度。
現參看第4圖，在許多III-N半導體元件中，元件之主動部分包含在III-N材料結構420之距離基板402最遠之層418內。舉例而言，參看第1A圖及第1B圖之電晶體結構，元件溝道112包含在溝道層108(因此，包含在對應於第4圖之附加層418的第1A圖及第1B圖之溝道層108及障壁層110)內。在此等元件中，在導致附加層418中之最小缺陷及/或阱之條件下形成附加層418時，通常較佳的是使基板402及/或成核層404及/或緩衝層406與附加層418電絕緣。如先前所述，此可如下實現：藉由分別在成核層404及/或緩衝層406之生長期間將烴前驅物注入至反應器，以便在生長一些或全部附加層418以作為無摻雜(或無意摻雜)層時用碳摻雜該等層及使該等層絕緣或半絕緣，其中使用實質上較低位準之碳。在許多情況下，緩衝層406之厚度大於附加層418之厚度，以使得至少一半厚度之III-N材料結構具有實質碳摻雜。相較於成核層及/或緩衝層之碳摻雜藉由其他方法實現的 情況，此類結構可導致在附加層418之表面處之降低差排密度以及使III-N材料結構420之上表面實質上更光滑。該等改良之特徵導致改良之元件效能及較高收益。
舉例而言，當碳摻雜藉由先前所述之其他方法(諸如，在碳摻雜層之生長期間降低反應器壓力及溫度)實現時，已發現在異質基板(諸如，矽基板)上生長之所得III-N膜在表面上具有大目視特徵結構。當該等特徵結構趨於在該等結構之間具有相當大之空間間隔時，直接形成在該等特徵結構上之元件是不實用的抑或性能實質上比晶圓上之其他元件更差。
形成在III-N材料結構520之表面上之目視特徵結構500之示意圖在第5A圖及第5B圖中圖示，該III-N材料結構520在導致此類特徵結構之較高密度之條件下生長。第5A圖為特徵結構500之橫截面視圖，及第5B圖為特徵結構500之平面圖(俯視圖)。如在第5B圖中之平面圖中所示，特徵結構500可具有六邊形形狀。特徵結構之平均直徑502通常大於20微米，且更具體而言，在約20微米至500微米之範圍中，且特徵結構之平均高度504通常大於100奈米，例如約200奈米至500奈米。為作比較，在晶圓之不包括該等目視特徵結構之區域中，表面高度之平均偏差通常遠小於20奈米。
再次參看第4圖，已發現，當成核層404及/或緩衝層406分別具有大於1×1018cm-3之碳摻雜密度時，當碳摻雜藉由調節反應器條件(例如，藉由減低表面溫度及反應器壓力以便將更高濃度之碳併入III-N層)來實現時，III-N材料 結構420之表面具有大於8個特徵結構每平方公分之目視特徵結構500之密度。另一方面，當碳摻雜藉由在層404及/或層406之生長期間注入烴前驅物(諸如，丙烷)來實現時，可使得目視特徵結構500之密度小於5個特徵結構每平方公分，且通常小於2個特徵結構每平方公分。
已描述許多實施方式。然而，將瞭解，可在不脫離本文中所述之技術及元件之精神及範疇之情況下執行各種修改。舉例而言，用於形成碳摻雜III-N層之本文中所述之方法可用於製造需要絕緣或半絕緣層之其他元件(例如，光伏電池、雷射及LED)。因此，其他實施方式在以下申請專利範圍之範疇內。
200‧‧‧示例性方法
202‧‧‧矽基板
204‧‧‧成核層
206‧‧‧反應器
208‧‧‧緩衝層
210‧‧‧溝道層
212‧‧‧III-N材料層結構

Claims (37)

  1. 一種用於製造一半導體元件之方法，該方法包含以下步驟：在一反應器中於一基板上形成一III-N半導體層；及在形成該III-N半導體層時將一烴前驅物注入至該反應器內，從而碳摻雜該III-N半導體層並使該III-N半導體層絕緣或半絕緣。
  2. 如請求項1所述之方法，其中注射該烴前驅物包含注射具有一化學式(CxHy)之一烴前驅物，其中x及y為大於或等於1之整數。
  3. 如請求項1所述之方法，其中於該基板上形成該III-N半導體層包含以下步驟：在一矽基板之上於一III-N成核層上形成該III-N半導體層以作為一III-N緩衝層。
  4. 如請求項3所述之方法，該方法進一步包含以下步驟：在該III-N緩衝層之上形成一III-N溝道層及在該III-N溝道層之上形成一III-N障壁層，從而鄰近該溝道層與該障壁層之間的一界面形成一二維電子氣(2DEG)主動溝道。
  5. 如請求項4所述之方法，其中形成該III-N半導體層以作為一III-N緩衝層包含以下步驟：在複數個生長條件下形成該III-N緩衝層，且其中形成該III-N溝道層包含以下步驟：在 該等相同或實質上相同的生長條件下形成該III-N溝道層。
  6. 如請求項5所述之方法，其中該等複數個生長條件包含一表面溫度及一反應器壓力。
  7. 如請求項6所述之方法，其中該等複數個生長條件進一步包含III族前驅物流動速率與V族前驅物流動速率之一比率。
  8. 如請求項4所述之方法，其中該障壁層包含AlGaN，該溝道層包含無摻雜或無意摻雜(UID)GaN，及該緩衝層包含AlGaN或GaN或上述兩者。
  9. 如請求項1至8中任一項所述之方法，其中於該基板上形成該III-N半導體層包含以下步驟：藉由金屬有機化學氣相沉積(MOCVD)形成該III-N半導體層。
  10. 如請求項1至8中任一項所述之方法，其中形成該III-N半導體層包含以一III族前驅物莫耳流動速率將一III族前驅物注入至該反應器中，及將該烴前驅物注入至該反應器中包含以下步驟：以一烴前驅物莫耳流動速率將該烴前驅物注入至該反應器中，其中該烴前驅物莫耳流動速率至少為該III族前驅物莫耳流動速率之0.02倍。
  11. 如請求項1至8中任一項所述之方法，其中形成該III-N半導體層包含以下步驟：以一III族前驅物莫耳流動速率將一III族前驅物注入至該反應器中，及將該烴前驅物注入至該反應器中包含以下步驟：以一烴前驅物莫耳流動速率將該烴前驅物注入至該反應器中，其中該烴前驅物莫耳流動速率大於該III族前驅物莫耳流動速率。
  12. 如請求項1至8中任一項所述之方法，其中該烴前驅物包含丙烷或甲烷或上述兩者。
  13. 如請求項1至8中任一項所述之方法，該方法進一步包含以下步驟：向該半導體元件添加一閘極端子、一汲極端子及一源極端子，從而形成一III-N高電子遷移率電晶體(HEMT)。
  14. 如請求項1至8中任一項所述之方法，該方法進一步包含以下步驟：向該半導體元件添加一陽極端子及一陰極端子，從而形成一III-N二極體。
  15. 如請求項1至8中任一項所述之方法，其中使該III-N半導體層絕緣或半絕緣包含以下步驟：使該III-N半導體層具有至少1×107Ω.cm之一電阻率。
  16. 如請求項1至8中任一項所述之方法，其中使該III-N半 導體層絕緣或半絕緣包含以下步驟：使該III-N半導體層具有至少1×105Ω.cm之一電阻率。
  17. 如請求項1至8中任一項所述之方法，其中碳摻雜該III-N半導體層導致該III-N半導體層具有大於1×1018cm-3之一碳濃度。
  18. 一種半導體元件，該元件包含：一基板；及一碳摻雜絕緣或半絕緣III-N半導體層，該III-N半導體層係位於該基板上，該III-N半導體層包含在一III-N成核層上之一III-N緩衝層，該III-N緩衝層中之碳摻雜密度大於該III-N成核層之碳摻雜密度，其中該III-N緩衝層中之碳摻雜密度大於5×1018cm-3且該III-N半導體層中之一差排密度小於2×109cm-2。
  19. 如請求項18所述之半導體元件，其中該III-N半導體層具有在該基板遠端之一第一側及在該第一側與該基板之間的一第二側，及該III-N半導體層中之該差排密度為鄰近於該III-N半導體層之該第一側之一差排密度。
  20. 如請求項19所述之半導體元件，其中該基板為一異質基 板。
  21. 如請求項19所述之半導體元件，其中該基板為一矽基板。
  22. 如請求項21所述之半導體元件，該元件進一步包含在該III-N緩衝層上之一III-N溝道層及在該III-N溝道層上之一III-N障壁層，從而鄰近於該溝道層與該障壁層之間的一界面形成一二維電子氣(2DEG)主動溝道。
  23. 如請求項22所述之半導體元件，其中該障壁層包含AlGaN，該溝道層包含無摻雜或無意摻雜(UID)GaN，及該緩衝層包含AlGaN或GaN或上述兩者。
  24. 如請求項18至23中之任一項所述之半導體元件，該元件進一步包含一閘極端子、一汲極端子及一源極端子，其中該半導體元件為一III-N高電子遷移率電晶體(HEMT)。
  25. 如請求項18至23中之任一項所述之半導體元件，該元件進一步包含一陽極端子及一陰極端子，其中該半導體元件為一III-N二極體。
  26. 如請求項18至23中之任一項所述之半導體元件，其中該III-N緩衝層中之該碳摻雜密度小於5×1021cm-3。
  27. 一種用於形成一半導體材料結構之方法，該方法包含以下步驟：在一反應器中於一基板上形成一第一III-N半導體層；在形成該第一III-N半導體層時，將一烴前驅物注入至該反應器內，從而碳摻雜該第一III-N半導體層及使該第一III-N半導體層絕緣或半絕緣；及在該第一III-N半導體層上形成一第二III-N材料層；其中該第二III-N材料層具有一實質上比該第一III-N材料層低之碳濃度。
  28. 如請求項27所述之方法，其中該基板為一異質基板。
  29. 如請求項28所述之方法，其中該第二III-N材料層之與該基板相對之一表面具有小於5個特徵結構每平方公分之一目視特徵結構密度，其中該等目視特徵結構中之每一者具有大於100奈米之一平均高度。
  30. 如請求項27至29中之任一項所述之方法，其中在形成該第一III-N材料層時將該烴前驅物注入至該反應器中，但在形成該第二III-N材料層時不將該烴前驅物注入至該反應器中。
  31. 如請求項30所述之方法，其中該烴前驅物包含丙烷。
  32. 如請求項30所述之方法，其中該第二III-N材料層比該第一III-N材料層薄。
  33. 一種材料結構，該材料結構包含：一第一III-N半導體層，在一異質基板上；及一第二III-N半導體層，在該第一III-N材料結構之與該異質基板相對之一側上，該第二III-N半導體層比該第一III-N半導體層薄；其中該第一III-N半導體層貫穿該層具有大於1×1018cm-3之一碳濃度；貫穿該第二III-N半導體層之一碳濃度小於貫穿該第一III-N半導體層之該碳濃度；及該第二III-N材料層之與該基板相對之一表面具有小於5個特徵結構每平方公分之一目視特徵結構密度，其中該等目視特徵結構中之每一者具有大於100奈米之一平均高度。
  34. 如請求項33所述之材料結構，該第二III-N半導體層包含一III-N障壁層及一III-N溝道層，其中一二維電子氣(2DEG)主動溝道鄰近於該III-N溝道層與該III-N障壁層之間的一界面。
  35. 如請求項33至34中之任一項所述之材料結構，其中該第一III-N半導體層與該第二III-N半導體層之一組合厚度小 於6微米。
  36. 一種材料結構，該材料結構包含：一第一III-N半導體層，在一異質基板上；及一第二III-N半導體層，在該第一III-N材料結構之與該異質基板相對之一側上，該第二III-N半導體層比該第一III-N半導體層薄；其中該第一III-N半導體層為具有大於1×1018cm-3之一碳濃度之一絕緣或半絕緣層；該第二III-N半導體層之一碳濃度小於該第一III-N半導體層之該碳濃度；及在該第二III-N半導體層之與該異質基板相對之一表面處之一差排密度小於2×109cm-2。
  37. 如請求項36所述之材料結構，其中該第一III-N半導體層與該第二III-N半導體層之一組合厚度小於6微米。
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