CN105336769A - 三级管用外延片及其制备方法 - Google Patents

三级管用外延片及其制备方法 Download PDF

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CN105336769A
CN105336769A CN201510725514.8A CN201510725514A CN105336769A CN 105336769 A CN105336769 A CN 105336769A CN 201510725514 A CN201510725514 A CN 201510725514A CN 105336769 A CN105336769 A CN 105336769A
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resilient coating
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王东盛
苗操
李亦衡
魏鸿源
严文胜
张葶葶
朱廷刚
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JIANGSU NENGHUA MICROELECTRONIC TECHNOLOGY DEVELOPMENT Co Ltd
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]

Abstract

<b>本发明提供一种三级管用外延片及其制备方法，其制成的三极管电子器件漏电更低、击穿电压更高、寿命更长。一种三级管用外延片，包括依次层叠的衬底、</b><b>GaN</b><b>成核层、</b><b>GaN</b><b>缓冲层、</b><b>GaN</b><b>沟道层、</b><b>AlN</b><b>插入层、</b><b>AlGaN</b><b>本征层、</b><b>GaN</b><b>盖层，所述衬底为图形化蓝宝石衬底，所述</b><b>GaN</b><b>成核层为</b><b>C</b><b>掺杂的</b><b>GaN</b><b>成核层，所述</b><b>GaN</b><b>缓冲层为</b><b>C</b><b>掺杂的</b><b>GaN</b><b>缓冲层。</b>

Description

三级管用外延片及其制备方法
技术领域
本发明涉及一种三极管用外延片及其制备方法，特别涉及一种使用图像化蓝宝石衬底的三极管用外延片及其制备方法。
背景技术
目前用于三极管的外延片的衬底主要有两种，即蓝宝石衬底和碳化硅衬底。但由于碳化硅的价格昂贵，故蓝宝石衬底的使用更为广泛。现有技术中普遍使用的平片状蓝宝石衬底由于其位错密度较高，制成的三极管电子器件漏电流较高、易击穿。
发明内容
针对上述问题，本发明的目的是提供一种三级管用外延片及其制备方法，由其制成的三极管电子器件漏电较低、击穿电压较高、寿命较长。
为解决上述技术问题，本发明采用的技术方案为：
一种三级管用外延片，包括依次层叠的衬底、GaN成核层、GaN缓冲层、GaN沟道层、AlN插入层、AlGaN本征层、GaN盖层，所述衬底为图形化蓝宝石衬底，所述GaN成核层为C掺杂的GaN成核层，所述GaN缓冲层为C掺杂的GaN缓冲层。
优选地，所述图形化蓝宝石衬底的图形高度、宽度、间隙分别为1.6μm、2.4μm、0.6μm，或分别为1.7μm、2.6μm、0.4μm，或分别为1.2μm、1.8μm、0.1μm。
优选地，所述GaN成核层的厚度为20~50nm；所述GaN缓冲层的厚度为2~3μm；所述GaN沟道层的厚度为80~150nm；所述AlN插入层的厚度为1~3nm；所述AlGaN本征层的厚度为15~30nm；所述GaN盖层的厚度为1~2nm。
优选地，所述GaN成核层和所述GaN缓冲层所采用的C的掺杂源为CCl 4 或C 2 H 2 。
优选地，所述AlGaN本征层中Al的摩尔百分含量为20~30%。
本发明采用的又一技术方案为：
一种所述的三级管用外延片的制备方法，其包括如下步骤：
A将图形化蓝宝石衬底在1050~1100℃的H 2 氛围下高温净化5~10min；
B在H 2 氛围下将步骤A净化后的衬底降温至500~600℃，在衬底上生长C掺杂的GaN成核层；
C温度升高至1040~1080℃，在所述GaN成核层上生长C掺杂的GaN缓冲层；
D在1000~1050℃的温度下，在所述GaN缓冲层上生长GaN沟道层；
E在所述GaN沟道层上生长AlN插入层；
F在所述AlN插入层上生长AlGaN本征层；
G在所述AlGaN本征层上生长GaN盖层。
优选地，步骤B中，采用MOCVD工艺在所述衬底上生长所述GaN成核层。
优选地，所述GaN缓冲层的生长压力为30~50mbar。
优选地，所述AlN插入层、AlGaN本征层、GaN盖层的生长压力均为50~70mbar或70~100mbar或100~133mbar或133~166mbar或166~200mbar。
优选地，所述AlN插入层、AlGaN本征层、GaN盖层的生长温度均为980~1000℃或1000~1020℃或1020~1050℃或1050~1080℃。
本发明采用以上技术方案，相比现有技术具有如下优点：在图形化蓝宝石衬底生长掺C的GaN成核层和掺C的GaN缓冲层制成了更高晶体质量的半绝缘GaN，所制成的三极管外延片晶体质量更好，相较常规平片蓝宝石衬底制作的三极管用外延片，位错密度由1E9cm -3 降低至1E8cm -3 ，且用此外延片制作的三极管电子器件漏电流较低，击穿电压较高，寿命较长。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1为本发明的三级管用外延片的结构示意图。
上述附图中，1、衬底；2、GaN成核层；3、GaN缓冲层；4、外延结构层；41、GaN沟道层；42、AlN插入层；43、AlGaN本征层；44、GaN盖层。
具体实施方式
下面对本发明的较佳实施例进行详细阐述，以使本发明的优点和特征能更易于被本领域的技术人员理解。
图1所示为本发明的一种三级管用外延片。结合图1所示，该三级管用外延片包括依次层叠的衬底1、GaN成核层2、GaN缓冲层3、GaN沟道层41、AlN插入层42、AlGaN本征层43、GaN盖层44。
所述衬底1为图形化蓝宝石衬底（PSS）1。图形化蓝宝石衬底1的图形高度、宽度、间隙分别为1.6μm、2.4μm、0.6μm；或，图形化蓝宝石衬底1的图形高度、宽度、间隙分别为1.7μm、2.6μm、0.4μm；或，图形化蓝宝石衬底1的图形高度、宽度、间隙分别为1.2μm、1.8μm、0.1μm。
成核层2为C掺杂的GaN成核层2，GaN缓冲层3为C掺杂的GaN缓冲层3。GaN成核层2和GaN缓冲层3都是用了C掺杂，共同作为三级管用外延片的绝缘层，与图像化蓝宝石衬底1构成半绝缘GaN。GaN成核层2的厚度为20~50nm，GaN缓冲层3的厚度为2~3μm。GaN成核层2和所述GaN缓冲层3所采用的C的掺杂源为CCl 4 或C 2 H 2 。
沟道层41、AlN插入层42、AlGaN本征层43、GaN盖层44形成三级管用外延片的外延结构层4。其中，GaN沟道层41的厚度为80~150nm，AlN插入层42的厚度为1~3nm，AlGaN本征层43的厚度为15~30nm，GaN盖层44的厚度为1~2nm。AlGaN本征层43中Al的摩尔百分含量为20~30%。
一种上述三级管用外延片的制备方法，包括如下步骤：
A、提供图形化蓝宝石衬底1，将图形化蓝宝石衬底1在1050~1100℃的H 2 氛围下高温净化5~10min；
B、在H 2 氛围下将步骤A净化后的图形化蓝宝石衬底1降温至500~600℃，在图形化蓝宝石衬底1上生长掺C的GaN成核层2；
C、温度升高至1040~1080℃，在所述GaN成核层2上生长掺C的GaN缓冲层3；
D、在1000~1050℃的温度下，在所述GaN缓冲层3上生长非掺杂的GaN沟道层41，GaN沟道层41覆盖于GaN缓冲层3之上；
E、在所述GaN沟道层41上生长AlN插入层42，AlN插入层42覆盖于GaN沟道层41之上；
F、在所述AlN插入层42上生长AlGaN本征层43，AlGaN本征层43覆盖于AlN插入层42之上；
G、在所述AlGaN本征层43上生长GaN盖层44，GaN盖层44覆盖于AlGaN本征层43之上。
步骤B中，采用MOCVD工艺（即金属有机化合物化学气相沉淀工艺，Metal-organicChemicalVaporDeposition）在所述衬底1上生长所述GaN成核层2。
步骤C中，所述GaN缓冲层3的生长压力为30~50mbar。
在生长外延结构层4的步骤E、F、G中，AlN插入层42、AlGaN本征层43、GaN盖层44的生长压力均为50~70mbar；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长压力均为70~100mbar；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长压力均为100~133mbar；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长压力均为133~166mbar；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长压力均为166~200mbar。
插入层42、AlGaN本征层43、GaN盖层44的生长温度均为980~1000℃；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长温度均为1000~1020℃；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长温度均为1020~1050℃；或，AlN插入层42、AlGaN本征层43、GaN盖层44的生长温度均为1050~1080℃。
相比平片蓝宝石衬底制成的三极管外延片，本发明在图像化蓝宝石衬底上沉积掺C的GaN成核层和掺C的GaN缓冲层构成半绝缘GaN，在此基础上制成的三极管外延片的位错密度由现有技术中的1E9cm -3 降低至1E8cm -3 。
上述实施例只为说明本发明的技术构思及特点，是一种优选的实施例，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明的精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (10)

1.一种三级管用外延片，包括依次层叠的衬底、GaN成核层、GaN缓冲层、GaN沟道层、AlN插入层、AlGaN本征层、GaN盖层，其特征在于：所述衬底为图形化蓝宝石衬底，所述GaN成核层为C掺杂的GaN成核层，所述GaN缓冲层为C掺杂的GaN缓冲层。
2.根据权利要求1所述的外延片，其特征在于：所述图形化蓝宝石衬底的图形高度、宽度、间隙分别为1.6μm、2.4μm、0.6μm，或分别为1.7μm、2.6μm、0.4μm，或分别为1.2μm、1.8μm、0.1μm。
3.根据权利要求1所述的外延片，其特征在于：所述GaN成核层的厚度为20~50nm；所述GaN缓冲层的厚度为2~3μm；所述GaN沟道层的厚度为80~150nm；所述AlN插入层的厚度为1~3nm；所述AlGaN本征层的厚度为15~30nm；所述GaN盖层的厚度为1~2nm。
4.根据权利要求1所述的外延片，其特征在于：所述GaN成核层和所述GaN缓冲层所采用的C的掺杂源为CCl4或C2H2。
5.根据权利要求1所述的外延片，其特征在于：所述AlGaN本征层中Al的摩尔百分含量为20~30%。
6.一种如权利要求1-5任一项所述的三级管用外延片的制备方法，其特征在于，包括如下步骤：
A将图形化蓝宝石衬底在1050~1100℃的H2氛围下高温净化5~10min；
B在H2氛围下将步骤A净化后的衬底降温至500~600℃，在衬底上生长C掺杂的GaN成核层；
C温度升高至1040~1080℃，在所述GaN成核层上生长C掺杂的GaN缓冲层；
D在1000~1050℃的温度下，在所述GaN缓冲层上生长GaN沟道层；
E在所述GaN沟道层上生长AlN插入层；
F在所述AlN插入层上生长AlGaN本征层；
G在所述AlGaN本征层上生长GaN盖层。
7.根据权利要求6所述的制备方法，其特征在于：步骤B中，采用MOCVD工艺在所述衬底上生长所述GaN成核层。
8.根据权利要求6所述的制备方法，其特征在于：所述GaN缓冲层的生长压力为30~50mbar。
9.根据权利要求6所述的制备方法，其特征在于：所述AlN插入层、AlGaN本征层、GaN盖层的生长压力均为50~200mbar。
10.根据权利要求6所述的制备方法，其特征在于：所述AlN插入层、AlGaN本征层、GaN盖层的生长温度均为980~1000℃或1000~1020℃或1020~1050℃或1050~1080℃。
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US20170358495A1 (en) * 2016-06-14 2017-12-14 Chih-Shu Huang Epitaxial structure of ga-face group iii nitride, active device, and method for fabricating the same
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CN108695385A (zh) * 2018-07-17 2018-10-23 中山市华南理工大学现代产业技术研究院 一种基于Si衬底的GaN基射频器件外延结构及其制造方法
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