CN1557024B - 绝缘栅铝镓氮化物/氮化钾高电子迁移率晶体管(hemt) - Google Patents
绝缘栅铝镓氮化物/氮化钾高电子迁移率晶体管(hemt) Download PDFInfo
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- CN1557024B CN1557024B CN028185021A CN02818502A CN1557024B CN 1557024 B CN1557024 B CN 1557024B CN 028185021 A CN028185021 A CN 028185021A CN 02818502 A CN02818502 A CN 02818502A CN 1557024 B CN1557024 B CN 1557024B
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
本发明所揭示的AlGaN/GaN HEMT具有一很薄的AlGaN层,以降低陷阱捕捉,而且还具有额外层,以降低栅极漏电流并增加最大驱动电流。依据本发明的一HEMT包括一高电阻半导体层(20),其上具有一势迭半导体层(18)。势迭层(18)具有比高电阻层(20)还宽的能隙,并在各层之间形成一二维电子气(22)。源极和漏极触点(13,14)接触势迭层(18),势迭层(18)的一部分表面未被触点(13,14)覆盖。一绝缘层(24)在势迭层(18)的未覆盖表面上,而一栅极触点(16)在绝缘层(24)上。绝缘层(24)对栅极漏电流形成阻障,并帮助增加HEMT的最大电流驱动力。本发明也包括本发明HEMT的制作方法。在其中一方法中,HEMT及其绝缘层是用金属有机气相沉积(MOCVD)法制作。在另一方法中,所述绝缘层是在一溅镀室内被溅镀到HEMT的上表面上。
Description
本申请要求享有由Parikh等人在2001年7月24日提出的美国临时专利申请号60/307,546之优先权。
技术领域
本发明涉及以氮化铝镓与氮化镓为基的高电子迁移率晶体管。
背景技术
微波系统一般是使用固态晶体管作为放大器与振荡器,使得系统尺寸大幅缩小且可靠度增加。为能适应不断扩展的各种微波系统,重要的是提高操作频率与功率。较高频的信号能承载更多资讯(频宽),使得较小的天线具有很高增益,并改善雷达的解析度。
场效应晶体管(FETs)以及高电子迁移率晶体管(HEMT)一般是固态晶体管类型,是由诸如硅(Si)或砷化镓(GaAs)的半导体材料制成的。Si的一个缺点是具有较低的电子迁移率(约1450cm2/V-s),会产生高电源电阻。该电阻使得可能以Si为基的HEMT高性能增益严重地降级。[CRC Press出版的“The Electrical EngineeringHandbook”(第二版),Dorf,p.994(1997)]
GaAs也是HEMT中常用到的材料,而且已经变成民用和军用雷达、手持式行动电话以及卫星通讯中信号放大的标准。GaAs具有较高的电子迁移率(约6000cm2/V-s)以及比Si还低的电源电阻,可使以GaAs为基的器件能在较高频下运作。然而,GaAs具有很小的能隙(室温下为1.42eV)以及很小的崩溃电压,这会阻碍以GaAs为基的HEMT在高频下提供高功率。
氮化镓(GaN)和氮化铝镓(AlGaN)半导体材料在制作上的改良,使人们将关注力集中在以AlGaN/GaN为基的HEMT开发上。这些器件可以产生较大的功率,这是因为它们独特地结合了材料的特性,这些特性包括高崩溃电场,宽能隙(GaN在室温下为3.36eV),高传导能带差异以及高饱合电漂移速度。若在相同频率下操作,尺寸相同的AlGaN/GaN放大器所产生的功率可以比GaAs放大器的高十倍。
Khan等人的美国专利编号第5,192,987案,揭示了在一缓冲层和一基材上成长出以AlGaN/GaN为基的HEMT,并揭示了其制作方法。Gaska等人在1997年出版的IEEE Electron Device Letters第10期第18卷第492页的″High-TemperaturePerformance of AlGaN/GaN HFET’s on SiC Substrates”一文中;以及Wu等人在″High Al-content AlGaN/GaN HEMTs with Very High Performance″(IEDM-1999 Digest pp.925-927,Washington DC,Dec.1999)一文中揭示了其它HEMT。这些器件经已显示出高达100亿赫兹的增益-频宽乘积(fT)(Lu等人的″AlGaN/GaN HEMTson SiC With Over 100GHz ft and Low Microwave Noise″,IEEE Transactions on Electron Devices,Vol.48,No.3,March 2001,pp.581-585),以及高达10W/mmX频带的高功率密度(Wu等人的″Bias-dependent Performance of High-PowerAlGaN/GaN HEMTs″,IEDM-2001,Washington DC,Dec.2-6,2001)。
尽管有这些发展,以AlGaN/GaN为基的FET与HEMT还是无法产生具高效率和高增益的大的总微波功率。它们会产生具有直流栅极驱动的很高功率增益,但是频率提升却低到毫赫兹至数千赫兹,其放大减弱很多。
据信,交流与直流放大之间的差异主要是由器件沟道内的表面陷阱引起。虽然名称上有些不同,但是如果补捉到一种载流子后最可能的下一步骤是再激发的话,一般把杂质或缺陷中心当作捕获中心(或简称陷阱)。
平衡时,陷阱会提供电子给HEMT内的2维电子气体(2-DEG)。位于深达能隙内的陷阱能阶在释放出捕获的载流子时,比位于接近价带传导的其它能阶还慢。这是因为从接近能隙中间的中心处,要将捕获的电子再激发到传导带需要增加能量的关系。
AlxGa1-xN(X=0~1)具有表面陷阱密度,相当于在深层施体状态带有陷阱的晶体管的沟道电荷,起动能量的范围由0.7至1.8eV(取决于X)。在HEMT操作期间,该陷阱会捕捉沟道电子。较慢的捕捉与释放过程会让晶体管速率降低,将使得微波频率下的功率性能大幅降低。
据信,以AlGaN/GaN为基的HEMT的陷阱密度是取决于AlGaN层的表面以及体积。降低AlGaN层的厚度会降低总陷阱量,进而降低高频时的捕捉效应。然而,降低AlGaN层的厚度会增加栅极漏电流的不需要的效应。正常操作时,偏压将被施加到源极与漏极触点之间,且电流会在触点之间流过,主要是穿过二维区。然而,在具有较薄AlGaN层的HEMT中,电流会代之以漏入栅极,形成从源极到栅极的不需要的电流。而且,较薄的AlGaN层会造成HEMT的可用最大驱动电流降低。
发明内容
本发明是在寻求提供一种解决上述问题的改良的AlGaN/GaN的HEMT,通过具有很薄的AlGaN层来降低陷阱捕捉,并通过具有额外层来降低栅极漏电流以及增加最大驱动电流。本发明还揭示了制作具有这些特性的HEMT的方法。
依据本发明的HEMT包括一高电阻半导体层,其上具有势迭半导体层。势迭层具有比高电阻层还宽的能隙,并在势迭层与高电阻层之间具有二维电子气。包括会接触到势迭层的源极与漏极触点,而部分势迭层表面并未被这些触点覆盖住。绝缘层是包括在势迭层的未覆盖表面上。沉积在绝缘层上的栅极触点具有对栅极漏电流形成势迭并增加HEMT最大电流驱动的绝缘层。
本发明还包括依据本发明制作HEMT的方法。其中一方法是,在金属有机化学气相沉积反应器内,在基材上形成HEMT的活性层。然后,将源气体加到反应器内,而在HEMT的活性层上″在原位″形成一绝缘层。然后,将该HEMT从反应器中移走以做进一步处理。
依据本发明制作HEMT的另一方法是:在基材上形成HEMT的活性层。然后,将该基材置于溅镀室内,在此,将绝缘层溅镀到HEMT活性层的上表面上。然后,可将HEMT从溅镀室中移走做进一步处理。
本发明的这些特点与优点以及其它进一步的特点与优点,对于熟知该技术领域的人士来说,从以下参照附图的详细说明会变得更明白。
附图说明
图1是依据本发明的在AlGaN层和之间具有绝缘层的AlGaN/GaN HEMT的剖视图;
图2是图1中的其表面上具有介电层的HEMT的剖视图;
图3是依据本发明的只在栅极触点下面具有绝缘层的AlGaN/GaN HEMT的剖视图;
图4是依据本发明的在栅极触点和AlGaN层之间具有双绝缘层的AlGaN/GaNHEMT的剖视图;
图5是图4中的HEMT在其表面上具有一介电层的剖视图;
图6是依据本发明的仅在栅极触点下面具有双绝缘层的AlGaN/GaN HEMT剖视图;
图7是依据本发明制作HEMT的方法中所使用的金属有机化学气相沉积(MOCVD)反应器的简图;以及
图8是依据本发明制作HEMT的方法中所使用的溅镀室的简图。
发明的详细说明
图1显示了依据本发明制作的以AlGaN/GaN为基的HEMT10。它包括基材11,该基材既可以是蓝宝石(Al2O3),也可以是碳化硅(SiC),较佳的基材是4H多晶型的碳化硅。也可使用其它的碳化硅多晶型,包括3C,6H和15R多晶型。它还包括在基材11上的AlxGa1-xN缓冲层12(其中x是在0与1之间),该缓冲层在碳化硅基材和HEMT 10的残留物之间提供适当的晶体结构转移。许多不同的材料可用于缓冲层12,用于SiC上的缓冲层的合适材料是AlxGa1-xN,x=1。
针对III族氮化物,碳化硅比起蓝宝石具有更加接近的晶格匹配,使III族氮化物薄膜的品质更高。碳化硅也具有高导热性,使得碳化硅上III族氮化物器件的总输出功率不受限于基材的热逸散(如同在蓝宝石上形成的某些器件)。而且,半绝缘碳化硅基材的可用性提供器件绝缘的能力以及降低寄生电容,使器件商品化变成可能。SiC基材可由美国北卡罗莱纳州达拉谟(Durham)的Cree Research公司购得,制作方法在科学文献以及美国专利号34,861;4,946,547以及5,200,022案中提出。
HEMT 10包括缓冲层12上的高电阻层20以及该电阻层上的势迭层18,使得高电阻层被夹在势迭层18和缓冲层12之间。势迭层18通常的厚度约为0.1至0.3微米,势迭层18、高电阻层20以及缓冲层12最好是利用外延成长或离子注入在基材11上形成。
HEMT还包括在高电阻层20的表面上的源极与漏极触点13,14。势迭层18设置在触点13和14之间,每个触点接触势迭层的边缘。绝缘层24是包括在触点13和14之间的势迭层18上。在所显示的实施例中,绝缘层24覆盖住整个势迭层18,但是在其它实施例(下文将作描述)中,势迭层18并没有被完全覆盖住。绝缘层24可以用许多不同的材料做成,包括但不限于:氮化硅(SiN),氮化铝(AlN),二氧化硅(SiO2)或由上述材料合并成多层的合成物。
对于微波器件来说,触点13和14通常被隔开且间距范围为1.5至10微米。整流萧特基触点(栅极)16位于源极和漏极触点13,14之间的绝缘层24的表面上,而且它的长度范围通常为0.1至2微米。HEMT的总宽度取决于所需的总功率。它可以比30微米还宽,一般的宽度范围是100微米至6毫米。
AlxGa1-xN层18比GaN层20具有更宽的能隙,而且其能隙的不连续性会造成自由电荷从较宽的能隙转移到较低的能隙材料中。电荷会聚集在这两种材料之间的界面处并产生二维电子气(2DEG)22,使得电流在源极和漏极触点13,14之间流动。2DEG具有高电子迁移率,使HEMT在高频下具有很高跨导。施加在栅极16上的电压是以静电的方式控制正好在栅极底下2DEG内的电子数目,从而控制总电子流。
源极和漏极触点13,14最好由钛,铝,镍及金的合金做成,而栅极16最好由钛,铂,铬,镍,钛钨合金以及硅化铂做成。在一实施例中,触点包括镍,硅及钛的合金,是通过将这些材料分别沉积成层,然后进行退火处理而形成。因为该合金系统剔除掉铝,所以当退火温度超过铝的熔点(660℃)时,可避免不需要的铝污染在器件表面上。
操作期间,以特定的电位(n型隧道器件的正漏极电位)加偏压到漏极触点14,而源极接地。这会造成电流流过隧道和2DEG,从漏极流到源极触点13,14。该电流是通过施加到栅极16上的偏压和频率电位来控制,对隧道电流进行调节并提供增益。
如上所述,AlGaN层18的陷阱密度是取决于薄层体积,而且降低AlGaN层18的厚度也会降低陷阱密度,减少陷阱效应。然而,降低AlGaN层的厚度会增加栅极漏电流以及减低器件的最大电流驱动力。
在栅极16与势迭层18之间具有绝缘层,可降低HEMT的栅极漏电流。这对改善器件的长期可靠性来说会有直接的影响,因为栅极漏电流是HEMT变差的其中一个来源。HEMT 10的启动电压取决于绝缘层24所使用的材料种类,而启动电压可以高达3-4伏。然后,HEMT 10可以在较高电流程度以及较高输入驱动程度的聚集模式下操作。绝缘层也当作是HEMT的天然钝化剂,以改善其可靠性。
图2显示了类似于图1中的HEMT 10的以AlGaN为基的HEMT 30。HEMT 30具有类似的薄层,包括基材11,缓冲层12,GaN层20,2DEG 22,AlxGa1-xN势迭层18和绝缘层24。HEMT 30也具有源极,栅极和漏极触点13,14,16,类似于HEMT 10的。HEMT 30包括一额外的介电层32,该介电层设置在源极、栅极和漏极触点13,14,16之间的绝缘层24表面上。介电层保护HEMT免于在处理时会发生不需要的钝化、杂质以及损坏。介电层可以用许多不同的材料或这些材料的合成物来做成,适当的材料是SixNy。SixNy。
绝缘层24用于降低栅极漏电流,并利用夹在栅极16和势迭层18之间的绝缘层24的区段来增加电流驱动力。该区段的绝缘层24延伸到栅极16外,帮助保护触点之间的势迭层的表面,但是对降低漏电流或增加电流驱动力没有帮助。
图3显示了依据本发明的HEMT 40的另一实施例,类似于图1与2中的HEMT 10和30。HEMT 40具有类似的薄层,包括基材11,缓冲层12,GaN层20,2DEG 22和AlxGa1-xN势迭层18。HEMT 30亦有类似于HEMT 10和40上的源极、栅极和漏极触点13,14和16。然而,HEMT 40的绝缘层42只是包括在栅极触点16底下,使得绝缘层只被夹在栅极触点16和势迭层18之间。触点13,14,16之间的势迭层18的表面没有被绝缘层42覆盖。可以保持不覆盖或可以包括一介电材料料层44,来帮助降低陷阱捕捉效应,以及帮助降低任何对HEMT薄层不需要的钝化和损坏。而且还帮助减少杂质被加到HEMT薄层内。
介电层最好是氮化硅(SixNy),其中的硅是施体电子的来源,它会降低陷阱捕捉作用。最有效的是,薄层22和24应该满足以下条件:第一,应该具有提供施体电子高来源的掺杂物。对于氮化硅,该薄层应该具有高百分比的Si。虽然本申请人并不希望被任何操作理论所约束,但目前相信,来自薄层的电子会填满表面陷阱,使得它们变成中性,而不会在操作时捕捉到势迭层电子。
第二,掺杂物的能阶应该比陷阱的能阶高,为了获得最佳结果,该能阶应该比势迭层的导带边缘能阶高。相信这会降低电子来自处于施体状态的栅极金属的可能性,并防止在该能阶下的陷阱捕捉以及解除捕捉。如果掺杂物的能阶稍微低于势迭层的导带的能阶,该薄层也会工作,但是其能阶愈高,其工作将愈佳。
第三,对器件表面的损坏要很小或没有损坏,而且形成介电层时不应增加表面损坏。相信表面的损坏会产生更多的表面陷阱。
第四,涂布层与传导隧道表面之间的键结应在应力下稳定。如果该键结不稳定,相信当电子电场、电压或温度增加而产生应力时,该薄层在实际器件操作下可能会失效。
具有绝缘层的HEMT会经历低崩溃电压,所述绝缘层是利用金属有机化学气相沉积(MOCVD)法在原位沉积而形成。虽然本申请人并不希望受限于任何理论,但相信,低崩溃电压是由于在SiN层成长时AlGaN势迭层的掺杂/劣化造成的。成长条件,比如SiN层的成长温度,也会影响到HEMT片电荷的迁移率。降低绝缘层的成长温度造成较低的HEMT劣化,但是也造成SiN成长率减低。
为了在没有AlGaN势迭层的掺杂或劣化情况下,以正常成长率提供成长出绝缘层,可以使用双绝缘层的设计来替代单一绝缘层。图4显示了HEMT 50,类似于图1、2和3中的HEMT 10、30和40。HEMT 50具有类似的基材11,缓冲层12,GaN层20,2DEG22以及AlxGa1-xN势迭层18。HEMT 50也具有类似的源极,栅极和漏极触点13,14和16。然而,HEMT 50使用双绝缘层设计,而不是单一绝缘层。该双绝缘层包括源极和漏极触点13,14之间的势迭层18上的AlN间隔层52。SiN绝缘层54是包括在AlN间隔层52上,栅极触点16设置在绝缘层54上。
AlN间隔层52当作SiN绝缘层54和活性AlGaN势迭层18之间的隔层或屏障。SiN绝缘层54在正常条件下成长时,AlN间隔层52可防止势迭层18的掺杂/劣化。
间隔层也可以使用其它材料,只要在SiN绝缘层54以正常成长率沉积出来时,该材料能防止AlGaN势迭层18的掺杂/劣化即可。如果可以避免掉掺杂和劣化,则也可使用在没有间隔层情况下,直接在AlGaN层上提供沉积出SiN绝缘层的方法。本发明这些特点的重要特性可以避免HEMT的低崩溃电压。
图5是依据本发明的另一HEMT 60,它类似于图4中的HEMT 50,具有类似的基材11,缓冲层12,GaN层20,2DEG 22,AlxGa1-xN势迭层18,AlN间隔层52以及SiN绝缘层54。HEMT 60也具有类似的源极,栅极和漏极触点13,14和16。HEMT 60也包括一在触点13与16,14与16之间的SiN绝缘层54的曝露表面上的介电层62,类似于图2中HEMT 30的介电层32。如同HEMT 30的介电层32,介电层54帮助保护HEMT 60免于在控制处理期间发生不需要的钝化、杂质以及损坏。介电层可以用许多不同的材料或这些材料的结合来制成,适当的材料是SixNy。
图6是依据本发明的另一HEMT 70,它类似于图3中的HEMT 40,只在栅极触点底下具有一绝缘层。HEMT 70具有类似的基材11,缓冲层12,GaN层20,2DEG 22,AlxGa1-xN势迭层18以及源极,栅极和漏极触点13,14和16。HEMT的SiN绝缘层72以及AlN间隔层74都只在栅极16底下,使得这二层都被夹在栅极16与势迭层18之间。另一实施例(图中未示)中,间隔层74可以延伸到栅极以下,覆盖触点13与16,14与16之间的势迭层的表面。
HEMT 70也包括一介电层76,如图所示,覆盖在触点13与16,14与16之间的势迭层18的表面上。如同图3中HEMT 40的介电层44,介电层76帮助减低陷阱捕捉效应,并帮助降低对HEMT各薄层不需要的钝化和损坏。也帮助减少杂质被加到HEMT各薄层内。介电层76最好是氮化硅(SixNy),硅是施体电子的来源,用来填满所有的陷阱。为了更加有效,介电层76应该满足上述的图3的介电层44的四个条件。
上述HEMT的活性层是由AlGaN/GaN制成,但也可以用其它III族的氮化物材料制成。III族的氮化物是指氮与周期表中III族元素之间所形成的那些半导体化合物,通常是铝(Al)、镓(Ga)以及铟(In)。该用词也是指如AlGaN和AlInGaN的三元和四元化合物。
制作方法
本发明也揭示了制作具有单或双绝缘层的HEMT的方法。可以使用MOCVD法、电浆化学气相沉积(CVD)法、热灯丝裂解法(hot-filament CVD)或溅镀法,将绝缘层沉积在AlGaN/GaN半导体材料上。
图7显示了一MOCVD反应器80,它是在基材上长出AlGaN/GaN活性层以及沉积绝缘层的新方法中使用。反应器80包括一反应室82,该反应室具有由一转轴86支撑的成长平台84。在很多的应用中,如蓝宝石(Al2O3)或是碳化硅(SiC)蓝宝石的基材88是设置在成长平台84上,当然也可以使用其它的基材。
成长期间内,用加热元件90加热平台84,以保持基材88处于预设的温度下。该温度通常是在摄氏400与1200度(℃)之间,但可以更高或更低,视所需的成长类型而定。加热元件90可以是不同的加热器件,但通常是一射频(RF)或电阻线圈。
供应载送气体92给气体管线94,该载送气体是氢或氮。载送气体92也经由质流控制器95a,95b,95c供应给相对应的气泡器96a,96b,96c。气泡器96a具有成长化合物,通常是含有甲基或乙基的烷基化物,比如三甲基镓(TMG),三甲基铝(TMA)或三甲基铟(TMI)。气泡器96b与96c也可以包含类似的金属有机化物,能成长出III族化合物的合金。气泡器96a,96b,96c一般是由恒温槽98a,98b,98c保持在预设温度下,以确保在利用载送气体92传送到反应室82之前,金属有机化物的蒸气压不变。
打开所需组合的阀门100a,100b,100c,让通过气泡器96a,96b,96c的载送气体92与气体管线94内流动的载送气体92混合。然后,经由反应室82上端的气体输入口102,将混合气体注入反应室82内。
诸如氨的含氮气体104,经由质流控制器106供应到气体管线94内。含氮气体的流量是受阀门108控制。如果载送气体92与含氮气体104混合在一起,而且气体管线94内的TMG蒸气被注入到反应室82内,则经由TMG和含氨气体内的分子热分解,会出现元素进而在基材88上成长出氮化镓。
为了对基材88上的氮化镓合金进行掺杂处理,不用于TMG的其中一个气泡器96a、96b、96c可给掺杂材料使用,所述材料通常是镁(Mg)或硅(Si),但可以是其它材料,比如钡,钙,锌或碳。气泡器96b或96c是给合金材料使用,比如硼,铝,铟,磷,砷或其它材料。一旦选定掺杂物与合金,而且打开适当的阀门100a、100b、100c使掺杂物流入装有镓与含氮气体104的气体管线94内,则在基材88上会发生氮化镓掺杂层的成长。
可以经由连接到可液压操作的泵112的气体净化管线110,来清除掉反应室82内的气体。此外,放气阀114可使反应室82内建立气压,或除去压力。
通常是藉关闭阀门110a与100b来阻断镓和掺杂物源,进而停止成长,并保持含氮气体和载送气体流动。另一方式是,可以经由质流控制器118和阀门120来控制气体116,以清洗反应室82。打开阀门114帮助清洗,使用泵112将反应室82内的多余成长气体抽出。通常,净化气体116是氢,但可以是其它气体。关闭加热元件90的电源,以冷却基材88。
依据本发明的一种方法中,在AlGaN/GaN半导体材料成长之后且在冷却反应室82之前(称作在原位)或冷却期间,施加绝缘层/各层。紧接在反应室82中成长出半导体材料之后,藉关闭适当的阀门组合100a,100b,100c使不需要的成长气体流停止。可以完成反应器的短暂清洗,以去除掉上述不需要的气体。然后,让气体流入反应器内以沉积绝缘层,而在一较佳方法中,用于绝缘层的气体由一般的MOCVD源供给。当在AlGaN/GaN半导体材料上沉积Si3N4绝缘层时,二硅甲烷(Si2H6)和氨(NH6)经由气体管线94被注入到反应室82内。现在会有分子出现,经由热分解将Si3N4沉积在AlGaN/GaN材料上。当沉积双绝缘层时,在形成Si3N4层之前,先将适当的气体注入到反应室内,形成AlN层。
在具有介电层的那些HEMT实施例中,介电层也可以在原位沉积出来。在介电层中可以使用到的一些化合物的实例包括Si,Ge,MgOx,MgNx,ZnO,SiNx,SiOx,ScOx,GdOx以及其合金。多重薄层与适当材料的重复薄堆迭的层可用作为势迭层,比如SiNx/Si,MgNx/SiNx或MgNx/MgOx。不同的势迭层可由以下的源气体来形成:来自硅甲烷或二硅甲烷的Si、来自锗化合物的Ge,来自环戊二烯镁或甲基-环戊二烯镁和氨的MgNx,来自环戊二烯镁或甲基-环戊二烯镁和一氧化二氮的MgO,来自二甲基锌或二甲基锌和一氧化二氮或水的ZnO,来自硅甲烷或二硅甲烷和氨或一氧化二氮的SiNx,以及来自硅甲烷或二硅甲烷和一氧化二氮的SiOx。
沉积出绝缘层与介电层后,可以在反应室82内冷却半导体材料。然后,从冷却的反应室82中取出半导体材料。当该结构准备进行额外处理(比如金属化处理)时,可以用一些不同的方法去除掉部分的薄层,包括湿化学氢氟酸(HF)蚀刻,反应性离子蚀刻或电浆蚀刻,但并不受限于此。
依据本发明沉积绝缘层的另一方法是通过溅镀。图8显示了一简化的溅镀室130,可以用它在基材上沉积材料。操作时,半导体器件132是放在阳极134上。然后,将溅镀室136抽空,且将如氩气的惰性气体138注入气体管线140内,并经阀门142排出,以保持背景压力。由待沉积到基材/器件上的材料所做成的阴极144设置在溅镀室136内。当在电极之间加上高电压146时,惰性气体将被离子化,且正离子148会跑到阴极144。当撞击到阴极144时,正离子会与阴极原子150碰撞,使阴极原子获得足够的能量而射出。被溅镀的阴极原子150穿过空间,最后覆盖阳极134和半导体器件132,所述半导体器件具有来自溅镀原子150的涂层133。
其它溅镀装置可以更复杂且更详细,但它们都是在同一基本物理机理下工作。使用更复杂的溅镀系统,有可能溅镀并沉积出某一范围的金属与介电层。
可以使用溅镀法将绝缘层沉积到AlGaN/GaN HEMT上。利用如MOCVD的方法,在半导体晶圆上先形成HEMT。然后,清洗该晶圆(用NH4OH∶H2O(1∶4)冲洗约10至60秒),再将器件132放到溅镀室136中,该溅镀室的阴极144上具有硅源。SixNy绝缘层是以溅镀法沉积到晶圆上。溅镀法包括以下特定的步骤:将反应室抽气,直到压力低至约3×10-7Torr。利用具20-100sccm流率以及约5-10mTorr的源气体,再用200-300W的RF功率约2分钟来起始电浆。这会轰击阴极144上的硅,清洗其表面。然后,改变溅镀条件,使氩气流率为10-12sccm,氮气流率为8-10sccm,反应室压力为2.5-5mTorr以及RF功率为200-300W。保持该条件2分钟,对阴极144的Si进行溅镀。被溅镀的硅与氮起反应,最后的氮化硅被沉积在器件132上。
溅镀后,下个步骤130是要关闭氮气并调高氩气流率至20-100sccm历时2分钟,可以从溅镀室中取出器件132。可以对该器件的薄层再进行蚀刻处理。使用不同的方法,包括但不限于湿化学氢氟酸(HF)蚀刻、反应性离子蚀刻或电浆蚀刻,窗口处于器件薄层中作为源极、栅极与漏极触点。
另一方式是,在溅镀室130内沉积绝缘层之前,可以先在器件上沉积触点与栅极。然后对触点与栅极上的介电层进行蚀刻,提供导线连接。
虽然本发明已经参考某些较佳组合以相当详细的方式来做说明,但是其它的版本是可能的。绝缘层可以应用到不同材料系统的HEMT以及半导体器件上。也可以利用许多上述方法以外的其他方法来使用绝缘层,包括PECVD法、电子束沉积法、感应性耦合电浆法以及ICP沉积法。因此,所附的权利要求的精神和范围并不是限定于说明书中所描述的较佳版本。
器件标号对照表
序号 | 器件标号 | 原文 | 中文 |
1 | 10,30,40,50 | HEMT | 高电子流动率晶体管 |
2 | 12,20 | High resistance layer | 高电阻层 |
3 | 13 | Source contact | 源极触点 |
4 | 14 | Drain contact | 漏极触点 |
序号 | 器件标号 | 原文 | 中文 |
5 | 16 | Gate contact | 栅极触点 |
6 | 18 | Barrier layer | 势迭层 |
7 | 22 | Two-dimensional electron gas | 二维电子气 |
8 | 24 | Insulating layer | 绝缘层 |
9 | 32,44,76 | Dielectric layer | 介电层 |
10 | 52 | Aluminum nitride layer | 氮化铝 |
11 | 54 | Silicon nitride | 氮化硅 |
12 | 80 | Reactor | 反应器 |
13 | 82 | Chamber | 反应室 |
14 | 84 | Growth platform | 成长平台 |
15 | 86 | Shaft | 转轴 |
15 | 86 | Shaft | 转轴 |
16 | 11,88,132 | Substrate | 基材 |
17 | 90 | Heater element | 加热元件 |
18 | 92 | Carrier gas | 载送气体 |
19 | 94,140 | Gas line | 气体管线 |
20 | 95a,95b,95c,106,118 | Mass flow controller | 质流控制器 |
21 | 96a,96b,96c | Bubbler | 气泡器 |
22 | 98a,98b,98c | Temperature bath | 恒温槽 |
23 | 100a,100b,100c,108,114,120,142 | Valve | 阀门 |
24 | 102 | Gas inlet | 气体输入口 |
序号 | 器件标号 | 原文 | 中文 |
25 | 104 | Nitrogen containing gas | 含氮气体 |
26 | 110 | Line | 管线 |
27 | 112 | Pump | 泵 |
28 | 116 | Gas | 气体 |
29 | 130,136 | Sputtering chamber | 溅镀室 |
30 | 132 | Semiconductor d eVice | 半导体器件 |
31 | 133 | Coating | 涂层 |
32 | 134 | Anode | 阳极 |
33 | 138 | Inert gas | 惰性气体 |
34 | 144 | Cathode | 阴极 |
35 | 146 | High voltage | 高电压 |
36 | 150 | Cathode atom | 阴极原子 |
Claims (20)
1.一种高电子迁移率晶体管HEMT,它包括:
一高电阻半导体层;
一在所述高电阻层上的势迭半导体层,所述势迭层具有一比所述高电阻层还宽的能隙;
一在所述势迭层和所述高电阻层之间的二维电子气;
源极和漏极触点,它们和所述势迭层相接触,其中有部分势迭层未被所述源极和漏极触点覆盖;
一在所述势迭层的的至少一部分未被覆盖表面上的绝缘层,所述绝缘层包括一含硅层和一含氮化物层,所述含氮化物层被夹在所述势迭层和所述含硅层之间;以及
一在所述绝缘层上的栅极触点,所述绝缘层形成对栅极漏电流的障碍并增加所述高电子迁移率晶体管的最大电流驱动力。
2.如权利要求1所述的高电子迁移率晶体管,其特征在于,所述高电阻层和所述势迭半导体层由III族氮化物半导体材料制成。
3.如权利要求1所述的高电子迁移率晶体管,其特征在于,所述多重堆叠的绝缘层包括氮化硅SiN、氮化铝AlN、二氧化硅SiO2中的至少两种薄层。
4.如权利要求1所述的高电子迁移率晶体管,其特征在于,所述绝缘层包括一氮化硅层和一氮化铝层,所述氮化铝层被夹在所述势迭层和所述氮化硅层之间。
5.如权利要求1所述的高电子迁移率晶体管,其特征在于,所述晶体管还包括一介电层,该介电层覆盖在所述源极和漏极触点之间的所述势迭层或绝缘层的曝露表面上。
6.如权利要求1所述的高电子迁移率晶体管,其特征在于,所述绝缘层覆盖所述源极和漏极触点之间的所述势迭层的表面。
7.一种高电子迁移率晶体管HEMT,它包括:
一高电阻半导体层;
一在所述高电阻层上的势迭半导体层,所述势迭层具有一比所述高电阻层还宽的能隙;
一在所述势迭层和所述高电阻层之间的二维电子气;
源极和漏极触点,它们和所述势迭层相接触,其中有部分势迭层未被所述源极和漏极触点覆盖;
一在所述势迭层的未被覆盖表面上的绝缘层;以及
一在所述绝缘层上的栅极触点,所述绝缘层形成对栅极漏电流的障碍并增加所述高电子迁移率晶体管的最大电流驱动力,
其中所述绝缘层只在所述栅极触点底下并被夹在所述栅极触点和所述势迭层之间。
8.如权利要求7所述的高电子迁移率晶体管,其特征在于,所述绝缘层包括一氮化硅层以及一氮化铝层。
9.如权利要求7所述的高电子迁移率晶体管,其特征在于,所述晶体管还包括一介电层,该介电层覆盖所述源极和漏极触点之间的势迭层的曝露表面以及所述栅极触点下缘和所述势迭层之间的所述绝缘层的曝露表面。
10.一种对栅极漏电流形成障碍的高电子迁移率晶体管HEMT的制作方法,该方法包括以下步骤:
将一基材放入MOCVD反应器中;
使源气体流入所述反应器的反应室内,以在所述基材上形成一高电阻GaN层;
使源气体流入所述反应器的反应室内,在所述高电阻GaN层上形成一AlGaN层,所述AlGaN层具有比所述GaN层还宽的能隙;
使源气体流入所述反应器的反应室内,以在所述AlGaN层上形成一绝缘层,所述绝缘层包括一含硅层和一含氮化物层,所述含氮化物层被夹在所述势迭层和所述含硅层之间;
冷却所述反应室;以及
将具有沉积层的基材从所述反应器的反应室取出。
11.一种对栅极漏电流形成障碍的高电子迁移率晶体管HEMT的制作方法,该方法包括以下步骤:
在一基材上制作出所述高电子迁移率晶体管的活性层;
将所述基材放入一溅镀室内;
在所述溅镀室内在基材上溅镀一多重堆叠的绝缘层,所述绝缘层包括一含硅层和一含氮化物层,所述含氮化物层被夹在所述势迭层和所述硅层之间;以及
将所述基材从所述溅镀室取出。
12.一种晶体管,它包括:
一高电阻半导体层;
一在所述高电阻层上的势迭半导体层;
源极和漏极触点,它们和所述势迭层相接触,其中有部分势迭层未被所述源极和漏极触点覆盖;
一在所述势迭层的的至少一部分未被覆盖表面上的多重堆叠的绝缘层,所述绝缘层包括一含硅层和一含氮化物层,所述含氮化物层被夹在所述势迭层和所述含硅层之间;以及
一在所述绝缘层上的栅极触点,所述绝缘层对栅极漏电流形成障碍。
13.如权利要求12所述的晶体管,其特征在于,所述绝缘层增加所述晶体管的最大电流驱动力。
14.如权利要求12所述的晶体管,其特征在于,所述势迭层的厚度可使所述晶体管在微波频率下产生有效的增益。
15.如权利要求12所述的晶体管,其特征在于,所述高电阻半导体层和所述势迭半导体层由III族氮化物半导体材料制成。
16.如权利要求12所述的晶体管,其特征在于,所述绝缘层包括氮化硅SiN、氮化铝AlN、二氧化硅SiO2中的至少两种薄层。
17.如权利要求12所述的晶体管,其特征在于,所述晶体管还包括一介电层,该介电层覆盖所述源极和漏极触点之间的所述势迭层的表面,而所述触点未被所述绝缘层覆盖。
18.如权利要求12所述的晶体管,其特征在于,所述势迭层具有比所述高电阻层还宽的能隙,所述晶体管还包括一在所述势迭层和所述高电阻层之间的二维电子气。
19.一种晶体管,它包括:
一高电阻半导体层;
一在所述高电阻层上的势迭半导体层;
源极和漏极触点,它们和所述势迭层相接触,其中有部分势迭层未被所述源极和漏极触点覆盖;
一在所述势迭层的未被覆盖表面上的绝缘层;以及
一在所述绝缘层上的栅极触点,所述绝缘层对栅极漏电流形成障碍,
其中,所述绝缘层只在所述栅极触点底下并被夹在所述栅极触点和所述势迭层之间。
20.如权利要求19所述的晶体管,其特征在于,所述晶体管还包括一在所述源极和漏极触点之间的所述绝缘层的表面上的介电层。
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CA2454269A1 (en) | 2003-04-17 |
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JP2010021582A (ja) | 2010-01-28 |
JP2010021581A (ja) | 2010-01-28 |
WO2003032397A2 (en) | 2003-04-17 |
TW552712B (en) | 2003-09-11 |
AU2002357640A1 (en) | 2003-04-22 |
JP2005527102A (ja) | 2005-09-08 |
US10224427B2 (en) | 2019-03-05 |
KR100920434B1 (ko) | 2009-10-08 |
US20090315078A1 (en) | 2009-12-24 |
EP1410444A2 (en) | 2004-04-21 |
KR20040018502A (ko) | 2004-03-03 |
EP2267783A3 (en) | 2011-03-09 |
US9419124B2 (en) | 2016-08-16 |
EP1410444B1 (en) | 2012-08-22 |
EP2267784A2 (en) | 2010-12-29 |
EP2267783B1 (en) | 2017-06-21 |
EP2267783A2 (en) | 2010-12-29 |
US20060138456A1 (en) | 2006-06-29 |
CA2454269C (en) | 2015-07-07 |
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