CN105556678B - 具有高阈值电压和低导通电阻的常关型iii族氮化物晶体管 - Google Patents

具有高阈值电压和低导通电阻的常关型iii族氮化物晶体管 Download PDF

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CN105556678B
CN105556678B CN201380079683.8A CN201380079683A CN105556678B CN 105556678 B CN105556678 B CN 105556678B CN 201380079683 A CN201380079683 A CN 201380079683A CN 105556678 B CN105556678 B CN 105556678B
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CN105556678A (zh
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楚荣明
大卫·F·布朗
亚当·J·威廉姆斯
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Abstract

一种III族氮化物晶体管包括III族氮化物沟道层、在沟道层上方的势垒层、在势垒层的顶部上的介电层、接触沟道层的源极、接触沟道层的漏极、延伸通过介电层和势垒层并且其底部位于沟道层内的栅极沟槽、内衬栅极沟槽并在介电层上方延伸的栅极绝缘体,和在栅极沟槽中并部分地朝向源极和漏极延伸以形成集成的栅场板的栅极，所述势垒层具有1‑10纳米的厚度，其中沟道层和势垒层的界面与栅极沟槽的底部之间的距离大于0nm且小于或等于5nm。

Description

具有高阈值电压和低导通电阻的常关型III族氮化物晶体管
相关申请的交叉引用
本申请涉及于2012年4月25日提交的美国专利申请号13/456,039,该申请整体地并入本文。本申请还涉及于2013年9月30日提交的美国专利申请号14/041,667并要求其优先权，该申请整体地并入本文。
技术领域
本公开涉及III族氮化物场效应晶体管(FETs)且具体地涉及常关型(normally-off)FET。
背景技术
对于高速和高功率应用来说，III族氮化物晶体管是很有希望的，所述高速和高功率应用诸如电源开关，除了其他应用以外，其可用于电机驱动器和电源。这些应用中的许多需要晶体管以常关模式操作。常关模式操作可通过许多方式来实现，但典型地要以较高的导通电阻和较低的输出电流为代价。
于2012年4月25日提交的美国专利申请号13/456,039描述了一种常关型III族氮化物场效应晶体管以及制备常关型FET的方法。
所需要的是常关型FET，其在导通电阻方面具有最小的代价。具体所期望的是高阈值电压，优选地大于1伏特，低导通电阻，对于具有大于600V击穿电压的器件来说优选地小于20ohm-mm，以及在阈值电压和导通电阻方面的优异均一性，所述均一性具有优选小于10％的标准差。本公开的实施方案回答了这些和其他的需求。
发明内容
在本文公开的第一个实施方案中，一种III族氮化物晶体管包括III族氮化物沟道层、在沟道层上方的势垒层、在势垒层的顶部上的介电层、接触沟道层的源极、接触沟道层的漏极、延伸通过介电层和势垒层并且其底部位于沟道层内的栅极沟槽、内衬栅极沟槽并在介电层上方延伸的栅极绝缘体,和在栅极沟槽中并部分地朝向源极和漏极延伸以形成集成的栅场板的栅极，所述势垒层具有1-10纳米的厚度，其中沟道层和势垒层的界面与栅极沟槽的底部之间的距离大于0nm且小于或等于5nm。
在本文公开的另一个实施方案中，一种III族氮化物晶体管，包括：III族氮化物沟道层；在所述沟道层上方的势垒层；在所述势垒层的顶部上的介电层；接触所述沟道层的源极；接触所述沟道层的漏极；延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，所述栅极绝缘体包括在所述栅极沟槽的底部处的单晶AlN层、在所述单晶AlN层上的多晶AlN层、和在所述多晶AlN层上的包含Al2O3、AlON或SiN的绝缘层；和在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
在本文公开的又一个实施方案中，一种制造III族氮化物晶体管的方法，包括：形成III族氮化物沟道层；形成在所述沟道层上方的势垒层，所述势垒层具有1-10纳米的厚度；形成在所述势垒层的顶部上的介电层；形成接触所述沟道层的源极；形成接触所述沟道层的漏极；形成延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽使得所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离为大于0纳米且小于或等于5纳米；形成内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体；和形成在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
在本文公开的再又一个实施方案中，一种制造III族氮化物晶体管的方法，包括：形成III族氮化物沟道层；形成在所述沟道层上方的势垒层；形成在所述势垒层的顶部上的介电层；形成接触所述沟道层的源极；形成接触所述沟道层的漏极；形成延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；形成内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，所述栅极绝缘体包括在所述栅极沟槽的底部处的单晶AlN层、在所述单晶AlN层上的多晶AlN层、和在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；和在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
从后面的具体实施方式和附图中，这些和其他特征以及优势将变得进一步显而易见。在附图和说明书中，数字指示各种特征，在整个附图和说明书中相同的数字指代相同的特征。
附图说明
图1显示根据本公开的III族氮化物场效应晶体管的图解；
图2显示制造根据本公开的III族氮化物场效应晶体管的工艺流程；和
图3A-3C显示根据本公开的III族氮化物场效应晶体管的典型电流-电压曲线的图。
具体实施方式
在下面的描述中，给出大量具体的细节以清楚地描述本文公开的各种具体的实施方案。然而，本领域技术人员将理解在此要求保护的发明可以在不需要下面所讨论的所有具体细节的情况下实施。在其他情况下，没有描述公知的特征以便不使本发明难以理解。
图1显示了根据本公开的FET10的器件结构的立体剖面图。FET具有在基板12上形成的缓冲层14。沟道层16在缓冲层14上形成和势垒层18在沟道层16上形成。
基板12材料可以是硅(Si)、碳化硅(SiC)、蓝宝石、氮化镓(GaN)或氮化铝(AlN)。
缓冲层14可以是通过化学气相沉积或分子束外延在基板12上生长的III族氮化物材料的堆叠。
沟道层16可以是通过化学气相沉积或分子束外延在缓冲层14上生长的III族氮化物材料，诸如GaN。
典型地，沟道层16是厚度范围为5纳米至几微米的未掺杂的GaN层。
势垒层18可以为1-10纳米厚并且可以典型地为仅5nm厚。势垒层18可以是AlGaN，具有25％Al成分。
介电层26在势垒层18的顶部上形成，并且可以是SiN并且具有10-200纳米的厚度，并且可以典型地为100nm厚。介电层26可以通过MOCVD和LPCVD沉积。
源极20和漏极22与沟道层16接触并且通过介电层26和势垒层18延伸。源极20和漏极22在沟道层16的对侧端部上。
如在图2步骤3中所见，形成栅极沟槽32通过介电层26和势垒层18。栅极沟槽32的底部位于沟道层16内，并且在势垒层18的下方延伸并且进入到沟道层16中达垂直距离d30。此距离d 30在势垒层和沟道层界面34与栅极沟槽32的底部36之间，并且典型地为0-5纳米(nm)。对于常关操作，距离d 30需要大于0nm，并且需要尽可能小以便最小化导通电阻。
栅极绝缘体28在栅极沟槽32中和在电介质26上方形成。栅极绝缘体28可以包括下列的堆叠：在栅极沟槽32的底部处的单晶AlN层，其为至多2nm厚并且典型地为1nm厚；在单晶AlN层上的多晶AlN层，其为5nm-50nm厚并且典型地为25nm厚；和在多晶AlN层上形成的绝缘层，诸如AL2O3、AlON或SiN，其为1nm-50nm厚并且典型地为5nm厚。
单晶AlN优选地在大于600℃且小于1100℃的温度下生长。生长单晶AlN的优选温度为900℃。多晶AlN优选在大于300℃且小于900℃的温度下生长，且优选温度为600℃。
栅极绝缘体28堆叠使得FET 10成为常关型FET。在正栅偏置下，FET具有非常低的栅极漏，并且在栅极绝缘体18和沟道层16之间的界面处形成高迁移率电子通道。
栅极绝缘体堆叠28的单晶AlN层为沟道层16中的电子传输提供高质量界面，而不会导致二维电子气(2DEG)在沟道中的积累。此外，单晶AlN层提供了能障以防止电子俘获进入到多晶AlN层中。
多晶AlN层是支持栅偏置的主要层，并且氧化的AlN层充当对通过多晶AlN层的晶界的漏电路径的阻挡层。
栅极绝缘体在电介质26的上方形成并且延伸到源极20和漏极22。
栅极24在栅极沟槽32中栅极绝缘体28的上方形成，并且可以部分地朝向源极20以及部分地朝向漏极22延伸以形成集成的栅场板。
控制栅极沟槽32的深度实现了常关操作，同时使与势垒层/沟道层界面和栅极沟槽32的底部之间的垂直距离相关的电阻分量最小化。如上所讨论的，对于常关操作，距离d30需要大于0nm，并且需要尽可能小以便最小化导通电阻。
典型地为5nm的势垒层18允许以高的一致性精确地控制栅极沟槽32深度30。当蚀刻栅极沟槽通过势垒层时，结果总是有一些过蚀刻，并且一般有约10％过蚀刻。因此如果势垒层18为50nm厚，则过蚀刻将为约5nm，这将是相对大的过蚀刻。采用仅约5nm厚度的势垒层18，更好地控制了过蚀刻，且10％过蚀刻将仅为0.5nm。因此，仅约5nm的势垒层18允许更好地控制距离d 30。
图2显示了制造根据本公开的III族氮化物场效应晶体管的工艺流程。在步骤1中，为沟道层16和势垒层18生长epi层。在步骤2中，将介电层26沉积在势垒层18上。然后在步骤3中，将栅极沟槽32蚀刻通过介电层26和势垒层18，然后蚀刻入沟道层16中达距离d 30。在步骤4中，形成栅极绝缘体28堆叠。然后在步骤5中，通过蚀刻通过栅极绝缘体28、电介质26和势垒层18，然后形成用于源极20和漏极22的金属来形成源极20和漏极22。下一步在步骤6中，将栅极24金属化。
图3A-3C显示根据本公开的III族氮化物场效应晶体管的典型电流-电压曲线的图。该图指示了阈值电压为至少1V，导通电阻位20ohm-mm或更小，并且击穿电压为至少600V。
现在已经根据专利法规的要求描述了本发明，本领域技术人员将理解如何对本发明进行改变和修改以便满足其具体的要求或条件。这样的改变和修改可以在不背离如在本文公开的本发明的范围和精神的前提下做出。
提出上面对示例性和优选的实施方案的详细描述用于举例说明和根据法律要求公开的目的。其不意在是穷尽的或将本发明限于所述的准确形式，而是仅仅使得本领域其他技术人员能够理解本发明如何可以适合于特殊的用途或实施方式。对于本领域专业技术人员来说改型和变化的可能性将是显而易见的。不意在限制对可能已经包括公差、部件尺寸、具体工作条件、工程规范等并且可能在实施方式之间发生变化或对现有技术状态有所改变的示例性实施方案的描述，并且不应当由此暗示任何限制。申请人已经关于现有技术状态做出了本公开，而且考虑了许多进展并且未来的适应性改动可以考虑那些进展，主要根据当时的现有技术状态。本发明的范围意在由书面的权利要求以及可适用的等效形式限定。除非明确那样说明，否则提及单数的权利要求要素不意在表示“一个和仅一个”。而且，本公开中的任何要素、组件或方法或过程步骤不意在贡献给公众，无论在权利要求中是否明确地表述该要素、组件或步骤。本文的任何权利要求要素不应按照35U.S.C.Sec.112，第六段的规定解释，除非该要素专门地使用短语“用于……的装置”表述，并且本文的方法或过程步骤不应按照那些规定解释，除非该步骤或多个步骤专门地使用短语“包括下列的一个或多个步骤……”表述。
优选地包括本文所述的所有要素件、部件和步骤。要理解的是这些要素、部件和步骤中的任一个都可以被其他要素、部件和步骤代替或一起去掉，如对于本领域技术人员显而易见的那样。
概念
已经公开了至少下列的概念。
概念1.一种III族氮化物晶体管，包括：
III族氮化物沟道层；
在所述沟道层上方的势垒层，所述势垒层具有1-10纳米的厚度；
在所述势垒层的顶部上的介电层；
接触所述沟道层的源极；
接触所述沟道层的漏极；
延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；
内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体；和
在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极；
其中所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离大于0纳米且小于或等于5纳米。
概念2.概念1所述的晶体管，其中所述栅极绝缘体包括：
在所述栅极沟槽的底部处的单晶AlN层；
在所述单晶AlN层上的多晶AlN层；和
在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层。
概念3.一种III族氮化物晶体管，包括：
III族氮化物沟道层；
在所述沟道层上方的势垒层；
在所述势垒层的顶部上的介电层；
接触所述沟道层的源极；
接触所述沟道层的漏极；
延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；
内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，所述栅极绝缘体包括在所述栅极沟槽的底部处的单晶AlN层、在所述单晶AlN层上的多晶AlN层、和在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；和
在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
概念4.概念1或3所述的晶体管，其中：
所述单晶AlN层为至多2nm厚；
所述多晶AlN层为5nm-50nm厚；且
所述绝缘层为1nm-50nm厚。
概念5.概念1或3所述的晶体管，其中：
所述势垒层具有1-10纳米的厚度；和
所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离大于0纳米且小于或等于5纳米。
概念6.概念1或3所述的晶体管，其中：
所述沟道层是GaN；且
所述势垒层是AlGaN。
概念7.概念1或3所述的晶体管，其中：
所述晶体管的阈值电压为至少1V；
所述晶体管的导通电阻为20ohm-mm或更少；且
所述晶体管的击穿电压为至少600V。
概念8.概念1或3所述的晶体管，其中：
所述介电层为10-200纳米厚；且
所述沟道层为5纳米-2微米厚。
概念9.概念1或3所述的晶体管，进一步包括：
在所述势垒层和所述沟道层之间的至多1纳米厚的AlN分隔层。
概念10.一种制造III族氮化物晶体管的方法，包括：
形成III族氮化物沟道层；
形成在所述沟道层上方的势垒层，所述势垒层具有1-10纳米的厚度；
形成在所述势垒层的顶部上的介电层；
形成接触所述沟道层的源极；
形成接触所述沟道层的漏极；
形成延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽使得所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离为大于0纳米且小于或等于5纳米；
形成内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体；和
形成在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
概念11.概念10所述的方法，其中形成所述栅极绝缘体包括：
形成在所述栅极沟槽的底部处的单晶ALN层；
形成在所述单晶ALN层上的多晶ALN层；和
形成在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层。
概念12.一种制造III族氮化物晶体管的方法，包括：
形成III族氮化物沟道层；
形成在所述沟道层上方的势垒层；
形成在所述势垒层的顶部上的介电层；
形成接触所述沟道层的源极；
形成接触所述沟道层的漏极；
形成延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；
形成内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，所述栅极绝缘体包括在所述栅极沟槽的底部处的单晶AlN层、在所述单晶AlN层上的多晶AlN层、和在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；和
形成在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
概念13.概念10或12所述的方法，其中：
所述单晶AlN层为至多2nm厚；
所述多晶AlN层为5nm-50nm厚；且
所述绝缘层为1nm-50nm厚。
概念14.概念12所述的方法，其中：
所述势垒层具有1-10纳米的厚度；和
所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离大于0纳米且小于或等于5纳米。
概念15.概念10或12所述的方法，其中：
所述沟道层是GaN；且
所述势垒层是AlGaN。
概念16.概念10或12所述的方法，进一步包括：
形成在所述势垒层和所述沟道层之间的至多1纳米厚的AlN分隔层。
概念17.概念10或12所述的方法，其中:
在大于600℃且低于1100℃的温度下形成所述单晶AlN层；且
在大于300℃且低于900℃的温度下形成所述多晶AlN层。

Claims (24)

1.一种III族氮化物晶体管，包括：
III族氮化物沟道层；
在所述沟道层上方的势垒层，所述势垒层具有1-10纳米的厚度；
在所述势垒层的顶部上的介电层；
接触所述沟道层的源极；
接触所述沟道层的漏极；
延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；
内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体；和
在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极；
其中，所述栅极绝缘体包括：
在所述栅极沟槽的底部处的单晶AlN层；
在所述单晶AlN层上的多晶AlN层；和
在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；并且
其中，所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离大于0纳米且小于或等于5纳米。
2.根据权利要求1所述的晶体管，其中：
所述沟道层是GaN；且
所述势垒层是AlGaN。
3.根据权利要求1所述的晶体管，其中：
所述单晶AlN层为至多2nm厚；所述多晶AlN层为5nm-50nm厚；且
所述绝缘层为1nm-50nm厚。
4.根据权利要求1所述的晶体管，其中：
所述晶体管的阈值电压为至少1V；所述晶体管的导通电阻为20ohm-mm或更少；和
所述晶体管的击穿电压为至少600V。
5.根据权利要求1所述的晶体管，其中：
所述介电层为10-200纳米厚；且
所述沟道层为5纳米-2微米厚。
6.根据权利要求1所述的晶体管，进一步包括：
在所述势垒层和所述沟道层之间的至多1纳米厚的AlN分隔层。
7.一种III族氮化物晶体管，包括：
III族氮化物沟道层；
在所述沟道层上方的势垒层；
在所述势垒层的顶部上的介电层；
接触所述沟道层的源极；
接触所述沟道层的漏极；
延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；
内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，所述栅极绝缘体包括在所述栅极沟槽的底部处的单晶AlN层、在所述单晶AlN层上的多晶AlN层、和在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；和
在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
8.根据权利要求7所述的晶体管，其中：
所述单晶AlN层为至多2nm厚；
所述多晶AlN层为5nm-50nm厚；且
所述绝缘层为1nm-50nm厚。
9.根据权利要求7所述的晶体管，其中：
所述势垒层具有1-10纳米的厚度；和
所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离大于0纳米且小于或等于5纳米。
10.根据权利要求7所述的晶体管，其中：
所述沟道层是GaN；且
所述势垒层是AlGaN。
11.根据权利要求7所述的晶体管，其中：
所述晶体管的阈值电压为至少1V；
所述晶体管的导通电阻为20ohm-mm或更少；且
所述晶体管的击穿电压为至少600V。
12.根据权利要求7所述的晶体管，其中：
所述介电层为10-200纳米厚；且
所述沟道层为5纳米-2微米厚。
13.根据权利要求7所述的晶体管，进一步包括：
在所述势垒层和所述沟道层之间的至多1纳米厚的AlN分隔层。
14.一种制造III族氮化物晶体管的方法，包括：
形成III族氮化物沟道层；
形成在所述沟道层上方的势垒层，所述势垒层具有1-10纳米的厚度；
形成在所述势垒层的顶部上的介电层；
形成接触所述沟道层的源极；
形成接触所述沟道层的漏极；
形成延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽，使得所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离为大于0纳米且小于或等于5纳米；
形成内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，其中形成所述栅极绝缘体包括：形成在所述栅极沟槽的所述底部处的单晶AlN层，形成在所述单晶ALN层上的多晶ALN层，和形成在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；和
形成在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
15.根据权利要求14所述的方法，其中：
所述沟道层是GaN；且
所述势垒层是AlGaN。
16.根据权利要求14所述的方法，其中：
所述单晶AlN层为至多2nm厚；所述多晶AlN层为5nm-50nm厚；且
所述绝缘层为1nm-50nm厚。
17.根据权利要求14所述的方法，进一步包括：
形成在所述势垒层和所述沟道层之间的至多1纳米厚的AlN分隔层。
18.根据权利要求14所述的方法，其中：
在大于600℃且低于1100℃的温度下形成所述单晶AlN层；且在大于300℃且低于900℃的温度下形成所述多晶AlN层。
19.一种制造III族氮化物晶体管的方法，包括：
形成III族氮化物沟道层；
形成在所述沟道层上方的势垒层；
形成在所述势垒层的顶部上的介电层；
形成接触所述沟道层的源极；
形成接触所述沟道层的漏极；
形成延伸通过所述介电层和势垒层并且具有位于所述沟道层内的底部的栅极沟槽；
形成内衬所述栅极沟槽并在所述介电层上方延伸的栅极绝缘体，所述栅极绝缘体包括在所述栅极沟槽的底部处的单晶AlN层、在所述单晶AlN层上的多晶AlN层、和在所述多晶AlN层上的包含AL2O3、AlON或SiN的绝缘层；和
形成在所述栅极沟槽中并部分地朝向所述源极和所述漏极延伸以形成集成的栅场板的栅极。
20.根据权利要求19所述的方法，其中：
所述单晶AlN层为至多2nm厚；所述多晶AlN层为5nm-50nm厚；且
所述绝缘层为1nm-50nm厚。
21.根据权利要求19所述的方法，其中：
所述势垒层具有1-10纳米的厚度；和
所述沟道层和所述势垒层的界面与所述栅极沟槽的底部之间的距离大于0纳米且小于或等于5纳米。
22.根据权利要求19所述的方法，其中：
所述沟道层是GaN；且
所述势垒层是AlGaN。
23.根据权利要求19所述的方法，进一步包括：
形成在所述势垒层和所述沟道层之间的至多1纳米厚的AlN分隔层。
24.根据权利要求19所述的方法，其中:
在大于600℃且低于1100℃的温度下形成所述单晶AlN层；且在大于300℃且低于900℃的温度下形成所述多晶AlN层。
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