CN107851612B - Iii族氮化物互补式晶体管 - Google Patents

Iii族氮化物互补式晶体管 Download PDF

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CN107851612B
CN107851612B CN201580081442.6A CN201580081442A CN107851612B CN 107851612 B CN107851612 B CN 107851612B CN 201580081442 A CN201580081442 A CN 201580081442A CN 107851612 B CN107851612 B CN 107851612B
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nitride
mesa
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储荣明
曹雨
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HRL Laboratories LLC
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Abstract

一种半导体装置，包括：基板；位于基板上的III族氮化物缓冲层；N沟道晶体管，其包括位于缓冲层的一部分上的III族氮化物N沟道层，和位于N沟道层的顶部用于提供电子的III族氮化物N势垒层，其中，N势垒层具有比N沟道层更宽的带隙；P沟道晶体管，其包括位于缓冲层的另一部分上的用于协助空穴积累的III族氮化物P势垒层，在P势垒层上的III族氮化物P沟道层，其中，P势垒层具有比P沟道层更宽的带隙，和位于P沟道层顶部的掺杂有P型掺杂物的III族氮化物覆盖层。

Description

III族氮化物互补式晶体管
相关申请的交叉引用
本申请要求2015年8月31日提交的申请号为14/841,258的美国专利申请的优先权及权益，其全部内容通过引用并入本文。本申请还涉及2015年8月28日提交的申请号为14/838,958的美国专利申请、2013年9月30日提交的申请号为14/041,667的美国专利申请和2014年10月7日公告的专利号为8,853,709的美国专利，它们如同全文阐述般通过引用并入本文。
关于联邦资助的声明
无
技术领域
本公开涉及氮化镓(GaN)互补金属氧化物半导体(CMOS)技术。
背景技术
在现有技术中，已知GaN N沟道晶体管具有优异的高功率和高频率性能。但是，在一些应用中，希望具有可以在同一集成电路或基板上与GaN N沟道晶体管一起工作的P沟道GaN晶体管，这样可以实现高性能互补金属氧化物半导体(CMOS)集成电路(IC)。本公开的实施例回答了这些需求和其他需求。
发明内容
在本公开第一实施例中，半导体装置包括：基板；位于基板上的III族氮化物缓冲层；包括位于缓冲层的一部分上III族氮化物N沟道层和位于N沟道层的顶部用于提供电子的III族氮化物N势垒层的N沟道晶体管，其中N势垒层具有比N沟道层更宽的带隙；和P沟道晶体管，其包括位于另一部分缓冲层上用于协助空穴积累的III族氮化物P势垒层，位于P势垒层的顶部的III族氮化物P沟道层，其中，P势垒层具有比P沟道层更宽的带隙，和位于P沟道层的顶部的掺杂有P类型掺杂剂的III族氮化物覆盖层。
在本公开的另一实施例中，一种提供半导体装置的方法包括：在基板上形成III族氮化物(III-N)层缓冲层；在缓冲层上形成III族氮化物N沟道层；在N沟道层上形成III族氮化物N势垒层；在N势垒层的顶部形成第一介电层；蚀刻第一介电层、N势垒层和N沟道层，以为N沟道晶体管形成第一台面并暴露缓冲层的一部分；在第一台面上和缓冲层的暴露部分的第一区域上形成第二介电层，其中，第一区域邻近第一台面，并且，缓冲层的剩余部分是暴露的；在缓冲层的剩余的暴露部分的顶部形成III族氮化物P势垒层；在III族氮化物P势垒层的顶部形成III族氮化物P沟道层；在III族氮化物P沟道层的顶部形成III族氮化物P覆盖层，其中，III族氮化物P势垒层、III族氮化物P沟道层和III族氮化物P覆盖层为P沟道晶体管形成第二台面，并且第一台面和第二台面通过缓冲层上的第一区域分隔离开；去除所述第二介电层；和在第一台面和第二台面之间的缓冲层中注入离子，以在N沟道晶体管和P沟道晶体管之间提供隔离。
从后面的具体描述和附图中，这些和其他特征及优点将变得进一步清楚的。在附图和描述中，数字指示各种特征，整个附图和说明书中相同的数字代表相同的特征。
附图说明
图1示出了根据本公开的具有N沟道和P沟道晶体管的GaN基互补金属氧化物半导体(CMOS)集成电路的横截面；
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J、2K、2L、2M、2N、2O示出了根据本公开的制造具有N沟道和P沟道晶体管的GaN基互补金属氧化物半导体(CMOS)集成电路的工艺流程。
详细描述
在下面的描述中，阐述了大量具体的细节以清楚地描述本文公开的各种具体的实施方式。但是，本领域技术人员将理解，在此要求的发明可以在不需要下面所讨论的所有具体细节的情况下实施。其他情况下，没有描述公知的特征以避免遮掩本发明。
本公开描述了在同一晶圆中集成了N沟道和P沟道GaN晶体管的GaNCMOS技术。结果是高性能GaN基互补金属氧化物半导体(CMOS)集成电路。由于其高抗干扰度和低耗电量，CMOS集成电路是许多电路应用的优选的拓扑结构。
通过参考文献并入的2015年8月28日提交的申请号为14/838,958的美国专利申请描述了一种P沟道晶体管。本公开的GaN集成电路在共同的基板上集成了N沟道和P沟道晶体管，并且由于利用更低的耗电量可以获得更多的功能，因此具有比单独的氮化镓N沟道和/或P沟道晶体管的电路更好的性能。由于使用了高性能的N沟道和P沟道GaN晶体管，本公开的GaN集成电路的优点是它们的性能比硅CMOS获得的性能更好。
图1示出了根据本公开具有N沟道和P沟道晶体管的GaN基互补金属氧化物半导体(CMOS)集成电路的横截面。基板10可为GaN、AlN、蓝宝石、SiC、Si或其他适当的基底材料。后面参照图2O进一步描述了图1。
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J、2K、2L、2M、2N和2O示出了根据本公开的制造具有N沟道和P沟道晶体管的GaN基互补金属氧化物半导体(CMOS)集成电路的工艺流程。图2O与图1相同，但是为了完整性仍在工艺流程中示出。
现在参照图2A，缓冲层12位于基板10上，并可通过化学气相沉积(MOCVD)或者分子束外延(MBE)生长。缓冲层12可以是GaN。位于缓冲层12的顶部的是III族氮化物N-沟道层14，它可以是GaN，并可通过MOCVD或者MBE生长。位于III族氮化物N-沟道层14的顶部的是III族氮化物N-势垒层16，它可通过MOCVD或者MBE生长。N-势垒层16可为AlGaN、AlInN、AlInGaN、AlN或者这些层的组合。N-势垒层16具有比N-沟道层14更宽的带隙，并且N-势垒层16的厚度通常在1-100nm范围内。
一层介电质18沉积在N-势垒层16的顶部。介电层18可是SiN、SiO2、SiON、AlN或者它们的任何组合，并可具有1-500nm的厚度。
接下来参照图2B，刻蚀介电层18、N-势垒层16和N-沟道层14以创造N-沟道层14、N-势垒层16和介电层18的台面52，并暴露缓冲层12的一部分。
然后如图2C所示，在台面52上和缓冲层12的暴露部分的区域54上形成了介电层60。
接下来，参照图2D，在缓冲层12的剩余部分56的顶部，III族氮化物P-势垒层20可通过MOCVD或MBE生长。P-势垒层20可为AlGaN、AlInN、AlInGaN、AlN或者这些的组合。P-势垒层20的厚度通常在1-100nm范围内。P-势垒层20协助空穴积累。在III族氮化物P-势垒层20的顶部，III族氮化物P-沟道层22可通过MOCVD或MBE生长。P-沟道层22通常为GaN，具有比P-势垒层20更窄的带隙。P-沟道层22的厚度通常在1-100nm范围内。
在III族氮化物P-沟道层22的顶部，III族氮化物P-覆盖层24可通过MOCVD或MBE生长。III族氮化物P-覆盖层24通常为掺杂Mg的GaN。Mg的浓度在P-覆盖层24各处可以不同。P-覆盖层24的厚度通常为1-100nm。
然后，如图2E所示，形成P势垒层、P沟道层和P覆盖层的期间，去除掩盖台面52和缓冲层12的区域54的介电层60。如图2E所示，结果是N沟道晶体管的台面52和P沟道晶体管的台面58。
接下来，如图2F所示，凭借在区域54及台面52和台面58的侧边的离子注入50，可以将台面52与台面58隔离。
然后，如图2G所示，在台面58的P-覆盖层24上及台面52和台面58之间的区域54的一部分上沉积介电层26。
接下来，如图2H所示，在介电层26中形成P-栅极沟槽62。P-栅极沟槽62的底部可部分地或完全地延伸穿过P-覆盖层24，并且也可部分地延伸穿过P-沟道层22。
然后，如图2I所示，在介电层18中形成N-栅极沟槽64。N-栅极沟槽64的底部可部分地或完全地延伸穿过介电层18，部分地或完全地延伸穿过N-势垒层16及部分地或完全地延伸穿过N-沟道层14，因此，N栅极沟槽停在介电层18的顶表面和缓冲层12的顶表面之间的任何地方。
接下来，如图2J所示，在装置顶部形成介电层28，因此，介电层28位于介电层18和介电层26的顶部，覆盖了N-栅极沟槽64的底部和侧边及P-栅极沟槽62的底部和侧边。介电层28通常是AlN/SiN层的堆积，通过MOCVD生长。介电层28也可仅在N-栅极沟槽64和P-栅极沟槽62内沉积以分别隔离N-栅极电极32和P-栅极电极42来降低栅极漏电流。
然后，如图2K所示，N-欧姆开口70和N-欧姆开口72被制作为位于N-栅极沟槽64的相对两侧。N-欧姆开口70和N-欧姆开口72被制作为穿过介电层28，并可被制作为部分地或完全地穿过介电层18，并且在一些情况下部分地或完全地穿过N-势垒层16。
接下来，如图2L所示，用金属填满N-欧姆开口70和N-欧姆开口72以形成N-欧姆电极74和N-欧姆电极76，为N沟道晶体管分别形成源极接触和漏极接触。
然后，如图2M所示，P-欧姆开口80和P-欧姆开口82形成于P-栅极沟槽62的相对两侧。P-欧姆开口80和P-欧姆开口82被制作为穿过介电层28、穿过介电层26，并在一些情况下部分地或完全地穿过P-覆盖层24。
接下来，如图2N所示，用金属填满P-欧姆开口80和P-欧姆开口82以形成P-欧姆电极84和P-欧姆电极86，为P沟道电极管分别形成源极接触和漏极接触。
最后，如图2O所示，用金属32填满N-栅极沟槽64，以为N沟道晶体管形成栅极接触，用金属42填满P-栅极沟槽62，以为P沟道晶体管形成栅极接触。
如图1所示，结果是具有N沟道和P沟道晶体管的GaN基互补金属氧化物半导体(CMOS)集成电路，图1与图2O相同。
现在参照图1，基板10可以是但不限于，GaN、AlN、蓝宝石、SiC或者Si。III族氮化物缓冲层12位于基板10上。如图1所示，在缓冲层12的一部分的顶部，III族氮化物N-沟道层14位于缓冲层12上，并且III族氮化物N-势垒层16位于N-沟道层14上。在缓冲层12的另一部分的顶部，III族氮化物P-势垒层20位于缓冲层12上，III族氮化物P-沟道层22位于P-势垒层20上，并且III族氮化物P-覆盖层24位于P-沟道层22上。
如上所述，介电层28覆盖N-栅极沟槽64的底部和侧边，以及P-栅极沟槽62的底部和侧边。金属32填满N-栅极沟槽64，以为N沟道晶体管形成栅极接触，金属42填满P-栅极沟槽62，以为P沟道晶体管形成栅极接触。
N-欧姆电极74和N-欧姆电极76分别为N沟道晶体管提供源极接触和漏极接触，以及P-欧姆电极84和P-欧姆电极86为P沟道晶体管分别提供源极接触和漏极接触。
在N沟道晶体管和P沟道晶体管之间区域54内的离子注入50为N沟道晶体管和P沟道晶体管提供隔离。
本领域技术人员将理解，图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J、2K、2L、2M、2N和2O工艺流程的步骤的顺序可以是另一种顺序，来获得图1所示的氮化镓基互补金属氧化物半导体(CMOS)集成电路。本领域技术人员还将理解，在工艺流程中可使用公知的构图和刻蚀步骤，诸如例如去除层或层的部分。由于这些公知的工艺在半导体工艺中被广泛的应用，因此没有具体描述这些公知的工艺。
现在已经根据专利法规的要求描述了本发明，本领域技术人员将理解如何对本发明进行改变和修改来满足他们具体的要求或条件。这样的改变和修改可在不背离如本文公开的本发明的范围和精神的前提下做出。
所提出的上面对示例性和优选的实施例的详细描述是为了根据法律要求的说明和公开的目的。其不意图穷尽本发明或将本发明限于所述的确切形式，而是仅仅意图使本领域其他技术人员能够理解本发明如何可以适合于具体的用途或实施方式。对于本领域技术人员来说，改变和变化的可能性将是显而易见的。不意图在限制对可能已经包括公差、特征尺寸、具体操作条件、工程规范等并且可能在实施方式之间发生变化或对现有技术的状态有所改变的示例性实施方式的描述，并且不应当由此暗示任何限制。申请人已经关于现有技术状态做出了本公开，但是也考虑到了进展，和这些进展未来的适应性可以考虑，即根据当时的现有技术状态。本发明的范围意在通过书面的和可实施的等同的权利要求限定。除非明确的规定，以单数形式提及的权利要求要素不意在表示“一个和仅一个”。此外，无论在权利要求中是否明确地叙述要素、组件或步骤，本公开中的任何要素、组件或方法或工艺步骤不意在贡献给公众。本文中的权利要求要素不应该按照35U.S.C.Sec.112第六段的规定解释，除非该要素清楚地使用短语“方法用于…”表述，并且本文中的方法和工艺步骤不按照那些规定解释，除非一个步骤或多个步骤清楚地使用短语“包括一个或多个步骤…”表述。
优选地包括本文描述的所有要素、部件和步骤。要理解的是这些要素、部件和步骤中的任何一个可由其他元素、部件和步骤代替或一起删除，这对本领域技术人员是显而易见的。
概念
本文公开了至少以下概念。
概念1.一种半导体装置，所述半导体装置包括：
基板；
位于所述基板上的III族氮化物缓冲层；
N沟道晶体管，所述N沟道晶体管包括：
位于所述缓冲层的一部分上的III族氮化物N沟道层；和
位于所述N沟道层顶部用于提供电子的III族氮化物N势垒层，其中，所述N沟道势垒层具有比N沟道层更宽的带隙；
P沟道晶体管，所述P沟道晶体管包括：
位于所述缓冲层的另一部分上的用于协助空穴积累的III族氮化物P势垒层；
位于所述P势垒层顶部的III族氮化物P沟道层，其中，所述P势垒层具有比所述P沟道层更宽的带隙；和
位于所述P沟道层顶部的掺杂有P类型掺杂剂的III族氮化物P覆盖层。
概念2.如概念1所述的半导体装置，其中：
所述N沟道晶体管包括在所述缓冲层上的第一台面；和
所述P沟道晶体管包括在所述缓冲层上的第二台面。
概念3.如概念2所述的半导体装置，进一步包括：
在所述缓冲层法人在所述第一台面和所述第二台面之间的一区域中的离子注入，所述离子注入用于在所述N沟道晶体管和所述P沟道晶体管之间提供隔离。
概念4.如概念1所述的半导体装置，其中，
所述基板包括GaN、AlN、蓝宝石、SiC、或Si。
概念5.如概念1所述的半导体装置，其中，
所述III族氮化物缓冲层包括GaN。
概念6.如概念1所述的半导体装置，其中，
所述III族氮化物N沟道层包括GaN。
概念7.如概念1所述的半导体装置，其中，
所述III族氮化物N势垒层包括AlGaN、AlInGaN、或AlN中的一种或多种；和
所述N势垒层具有比所述N沟道层更宽的带隙。
概念8.如概念1所述的半导体装置，其中，
所述P势垒层包括AlGaN、AlInGaN、或AlN中的一种或多种。概念9.如概念1所述的半导体装置，其中，
所述P沟道层包括GaN；和
所述P沟道层具有比所述P势垒层更窄的带隙。
概念10.如概念1所述的半导体装置，其中，
所述P覆盖层包括Mg。
概念11.如概念1所述的半导体装置进一步包括：
部分地或完全地延伸穿过所述N势垒层并且部分地或完全地延伸穿过所述N沟道层的N栅极沟槽，使得所述N栅极沟槽的底部停在所述N势垒层的顶表面和所述缓冲层的顶表面之间的任何地方；
部分地或完全地延伸穿过所述P覆盖层并且部分地延伸穿过所述P沟道层的P栅极沟槽，使得所述P栅极沟槽的底部停在所述P覆盖层的顶表面和所述P沟道层内部之间的任何地方；
内衬于所述N栅极沟槽和所述P栅极沟槽的介电层；和
位于所述N栅极沟槽中用于N栅极接触的第一金属；
位于所述P栅极沟槽中用于P栅极接触的第二金属；
位于所述N势垒层或所述N沟道层上的位于所述N栅极的相对侧上的源极接触和漏极N欧姆接触；和
位于所述P覆盖层或所述P沟道层上的位于所述P栅极的相对侧上的源极接触和漏极P欧姆接触。
概念12.一种用于制造半导体装置的方法，所述方法包括：
在基板上形成III族氮化物(III-N)层缓冲层；
在所述缓冲层上形成III族氮化物N沟道层；
在所述N沟道层上形成III族氮化物N势垒层；
在所述N势垒层的顶部形成第一介电层；
刻蚀所述第一介电层、所述N势垒层和所述N沟道层，以为N沟道晶体管形成第一台面并暴露所述缓冲层的一部分；
在所述第一台面和所述缓冲层的所述暴露部分的第一区域上形成第二介电层，其中，所述第一区域邻近所述第一台面，以及其中，所述缓冲层的剩余部分是暴露的；
在所述缓冲层的所述剩余的暴露部分的顶部形成III族氮化物P势垒层；
在所述III族氮化物P势垒层的顶部形成III族氮化物P沟道层；
在所述III族氮化物P沟道层的顶部形成III族氮化物P覆盖层，其中，所述III族氮化物P势垒层、III族氮化物P沟道层和III族氮化物P覆盖层，以为P沟道晶体管形成第二台面，及其中所述第一台面和所述第二台面通过所述缓冲层上的所述第一区域隔离开；
去除所述第二介电层；和
在所述第一台面和所述第二台面之间的所述缓冲层中注入离子，以在所述N沟道晶体管和所述P沟道晶体管之间提供隔离。
概念13.如概念12所述的方法，还包括：
在所述P覆盖层上和在所述第一台面和所述第二台面之间的所述第一区域的一部分上形成第三介电层；
在所述第三介电层中形成P栅极沟槽62，其中，所述P栅极沟槽的底部部分地或完全地延伸穿过所述P覆盖层，或部分地延伸穿过所述P沟道层；和
在所述第一介电层中形成N栅极沟槽，其中，所述N栅极沟槽的底部部分地或完全地延伸穿过所述第一介电层，部分地或完全地延伸穿过所述N势垒层，或部分地或完全地延伸穿过所述N沟道层，以使所述N栅极沟槽停在所述第一介电层的顶表面和所述缓冲层的顶表面之间的任何地方；和
在所述第一介电层的顶部、所述N栅极沟槽的底部和侧部上、所述第三介电层的顶部以及所述P栅极沟槽的底部和侧部上，形成第四介电层。
概念14.如概念13所述的方法还包括：
在所述N栅极沟槽的相对侧刻蚀第一开口和第二开口；
用金属填充所述第一开口和所述第二开口，以为N沟道晶体管分别形成源极接触的N欧姆电极和漏极接触的N欧姆电极；
在所述P栅极沟槽的相对侧蚀刻第三开口和第四开口；和
用金属填充所述第三开口和所述第四开口，以为P沟道晶体管分别形成源极接触的P欧姆电极和漏极接触的P欧姆电极；
概念15.如概念13所述的方法还包括：
用金属填充所述N栅极沟槽，以为所述N沟道晶体管形成栅极接触；
用金属填充所述P栅极沟槽，以为所述P沟道晶体管形成栅极接触。
概念16.如概念12所述的方法，其中，
所述基板包括GaN、AlN，蓝宝石、SiC或Si。
概念17.如概念12所述的方法，其中，
所述III族氮化物缓冲层包含GaN。
概念18.如概念12所述的方法，其中，
所述III族氮化物N沟道层包含GaN。
概念19.如概念12所述的方法，其中，
其中，所述III族氮化物N势垒层包含AlGaN、AlInN、AlInGaN或AlN中的一个或更多个；和
其中，所述N势垒层具有比N沟道层更宽的带隙。
概念20.如概念12所述的方法，其中，
所述P势垒层包含AlGaN、AlInN、AlInGaN或AlN中的一个或更多个。
概念21.如概念12所述的方法，其中，
所述P沟道层包含GaN；和
所述P沟道层具有比P势垒层更窄的带隙。
概念22.如概念12所述的方法，其中，
所述P覆盖层包含Mg。

Claims (11)

1.一种制造半导体装置的方法，所述方法包括：
在基板上形成III族氮化物(III-N)层缓冲层；
在所述缓冲层上形成III族氮化物N沟道层；
在所述N沟道层上形成III族氮化物N势垒层；
在所述N势垒层的顶部形成第一介电层；
刻蚀所述第一介电层、所述N势垒层和所述N沟道层，以为N沟道晶体管形成第一台面并形成所述缓冲层的暴露部分；
在所述第一台面上和在所述缓冲层的所述暴露部分的第一区域上形成第二介电层，其中，所述第一区域邻近所述第一台面，并且，所述缓冲层的剩余部分是暴露的；
在所述缓冲层的剩余的暴露部分的顶部形成III族氮化物P势垒层；
在所述III族氮化物P势垒层的顶部形成III族氮化物P沟道层；
在所述III族氮化物P沟道层的顶部形成III族氮化物P覆盖层，其中，所述III族氮化物P势垒层、III族氮化物P沟道层和III族氮化物P覆盖层为P沟道晶体管形成第二台面，并且所述第一台面和所述第二台面通过所述缓冲层上的所述第一区域隔离开；
去除所述第二介电层；和
在所述第一台面和所述第二台面之间的所述缓冲层中注入离子，以在所述N沟道晶体管和所述P沟道晶体管之间提供隔离。
2.如权利要求1所述的方法，还包括：
在所述P覆盖层上和在所述第一台面和所述第二台面之间的所述第一区域的一部分上形成第三介电层；
在所述第三介电层中形成P栅极沟槽，
其中，所述P栅极沟槽的底部部分地或完全地延伸穿过所述P覆盖层，或部分地延伸穿过所述P沟道层；和
在所述第一介电层中形成N栅极沟槽，其中，所述N栅极沟槽的底部部分地或完全地延伸穿过所述第一介电层，部分地或完全地延伸穿过所述N势垒层，或部分地或完全地延伸穿过所述N沟道层，以使所述N栅极沟槽停在所述第一介电层的顶表面和所述缓冲层的顶表面之间的任何地方；和
在所述第一介电层的顶部、所述N栅极沟槽的底部和侧部上、所述第三介电层的顶部以及所述P栅极沟槽的底部和侧部上，形成第四介电层。
3.如权利要求2所述的方法，还包括：
在所述N栅极沟槽的相对侧刻蚀第一开口和第二开口；
用金属填充所述第一开口和所述第二开口，以为N沟道晶体管分别形成源极接触的N欧姆电极和漏极接触的N欧姆电极；
在所述P栅极沟槽的相对侧蚀刻第三开口和第四开口；和
用金属填充所述第三开口和所述第四开口，以为P沟道晶体管分别形成源极接触的P欧姆电极和漏极接触的P欧姆电极。
4.如权利要求2所述的方法，还包括：
用金属填充所述N栅极沟槽，以为所述N沟道晶体管形成栅极接触；
用金属填充所述P栅极沟槽，以为所述P沟道晶体管形成栅极接触。
5.如权利要求1所述的方法，其中，
所述基板包括GaN、AlN、蓝宝石、SiC或Si。
6.如权利要求1所述的方法，其中，
所述III族氮化物缓冲层包含GaN。
7.如权利要求1所述的方法，其中，
所述III族氮化物N沟道层包含GaN。
8.如权利要求1所述的方法，其中，
其中，所述III族氮化物N势垒层包含AlGaN、AlInN、AlInGaN或AlN中的一个或更多个；和
其中，所述N势垒层具有比N沟道层更宽的带隙。
9.如权利要求1所述的方法，其中，
所述P势垒层包含AlGaN、AlInN、AlInGaN或AlN中的一个或更多个。
10.如权利要求1所述的方法，其中，
所述P沟道层包含GaN；和
所述P沟道层具有比P势垒层更窄的带隙。
11.如权利要求1所述的方法，其中，
所述P覆盖层包含Mg。
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