TWI487107B - 用於半導體電晶體之垂直鰭狀結構及其製造方法 - Google Patents

用於半導體電晶體之垂直鰭狀結構及其製造方法 Download PDF

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TWI487107B
TWI487107B TW099125304A TW99125304A TWI487107B TW I487107 B TWI487107 B TW I487107B TW 099125304 A TW099125304 A TW 099125304A TW 99125304 A TW99125304 A TW 99125304A TW I487107 B TWI487107 B TW I487107B
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Chih Hsin Ko
Clement Hsingjen Wnn
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Description

用於半導體電晶體之垂直鰭狀結構及其製造方法
本發明係關於積體電路，且特別是關於鰭型場效應電晶體(FinFET)裝置及/或具有一鰭型結構(fin structure)之多重閘場效應電晶體(multigate FET)裝置。
隨著積體電路裝置尺寸的更為降低，目前存在有數個方法以持續地改善半導體裝置的表現。方法之一採用應變工程(strain engineering)。其可藉由調變位於電晶體之通道內的應變而達成其表現之改善情形，例如為改善了電子遷移率(或電洞遷移率)且進而改善了通過該通道之導電率(conductivity)。
互補型金氧半導體(下稱CMOS)技術中，對於不同類型之應變，P型金氧半導體(下稱PMOS)與N型金氧半導體(NMOS)表現出不同之反應。更明確地，於通道處施加壓縮應變(compressive strain)時，可得到PMOS之最佳表現，而NMOS則由拉伸應變(tensile strain)而得到改善。舉例來說，由例如Si0.3 Ge0.7 之任一莫爾比率之矽與鍺所組成之矽鍺(Si1-x Gex )材料通常可用於積體電路內，以作為用於CMOS電晶體之應變矽之應變誘導膜層(即應變體stressor)。
應變矽為一矽膜層，其內之矽原子係經過伸展至其正常原子距以外之範圍。舉例來說，上述情形可藉由將一矽層放置於一矽鍺層之上。當矽層內之原子對準於下方之矽鍺層之後，由於矽鍺層內之原子相較塊狀矽結晶物之原子將更為分開，因此矽層內原子間的連結情形將更為延展，進而形成了應變矽。
另一方法為採用多重閘(multigate)裝置。多重閘裝置或多重閘場效應電晶體(MuGFET)係指於單一裝置內使用了多於一個閘極(gate)之金氧半導體電晶體。此些多重閘極可為一單一閘電極(gate electrode)所控制且此多重閘極的表面則電性地扮演了單一閘極，或者其亦可藉由各別之閘電極所控制。採用了獨立閘電極之多重閘裝置則有時可稱之為多重獨立閘場效應電晶體(MIGFET)。
於一多重閘結構內，通道為位於多重表面上之多於一個之閘極所環繞，因而表現出了對於”關狀態(off-state)”漏電流之較佳有效抑制情形。多重閘亦有助於增加於”開”狀態(on state)之電流，即所謂之驅動電流(drive current)。介於開/關狀態間之越高對比與更較低漏電流導致了較低之能量損耗與較佳之裝置表現。非平面裝置亦可較習知平面電晶體來的更小，因而有助於更小之整體積體電路內形成更高之電晶體密度。
除了上述方法之外，仍需要包括更高載子遷移率之其他更佳改善與更佳表現。特別地，需要藉由矽鍺/矽應變裝置所達成之更高應變情形，然而高應變之鍺裝置的製作極為不易。此外，介於閘介電物與NMOS裝置內之鍺材料間之不良介面情形亦為問題之一。
如此，便需要用於較佳裝置之包括較高之載子遷移率與介於閘介電物與NMOS裝置之鍺材料間之較佳介面之新的結構與方法。
有鑑於此，本發明提供了一種半導體電晶體之垂直鰭狀結構及其製造方法，藉以解決上述習知問題。
依據一實施例，本發明提供了一種半導體電晶體之垂直鰭狀結構，包括：一半導體基板；一鰭型層，位於該半導體基板之頂部；以及一上蓋層，覆蓋該鰭型層，其中該半導體基板包括一IV族半導體材料，該鰭型層包括一IV族半導體材料，該上蓋層包括一III-V族半導體化合物，該鰭型層作為該半導體電晶體之通道層，而該通道層施加應變至該鰭型層之上以增加通過該通道區之遷移率。
依據另一實施例，本發明提供了一種半導體電晶體之垂直鰭狀結構之製造方法，包括：提供一半導體基板，其中該半導體基板包括一IV族半導體材料；沈積一鰭型層於該半導體基板之頂部上，其中該鰭型層包括了IV族半導體材料且作為該半導體電晶體之一通道；以及沈積一上蓋層於該鰭型層之上，其中該上蓋層包括III-V族半導體化合物且施加應變於該鰭型層之上以增加通過該通道之遷移率。
依據又一實施例，本發明提供了一種半導體電晶體之垂直鰭狀結構，包括：一半導體基板；一鰭型層，位於該半導體基板之頂部；以及一上蓋層，覆蓋該鰭型層，其中該半導體基板包括Si、Ge、SiGe或SiC，該鰭型層包括Ge、SiGe、SiC或上述材料之組合，該上蓋層包括GaAs、InGaAs、InAs、InSb、GaSb、GaN、InP或上述材料之組合，該上蓋層與該半導體基板之間具有多於4%之晶格不相稱情形，該鰭型層作為該半導體電晶體之通道層，而該通道層施加應變至該鰭型層之上以增加通過該通道區之遷移率。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
本發明提供了製作如於矽基板上具有III-V族上蓋層之雙重閘場效應電晶體或三重閘場效應電晶體之高遷移率之應變鍺或應變矽鍺之鰭型場效應電晶體與多重閘場效應電晶體之方法與結構。本發明將透過下文與相關圖式以解說之，其中相同符號代表了相同之元件。
第1圖顯示了具有應變鍺或應變矽鍺之鰭型場效應電晶體及/或多重閘場效應電晶體之一垂直型鰭狀結構之一電晶體閘極區域的製程過程中之一剖面圖。在此，半導體基板102包括了IV族半導體材料，例如Si、Ge、SiGe或SiC，或其他其他材料。而鰭型層104包括IV族半導體材料，例如Ge、SiGe、SiC或上述材料之組合，或其他之適當材料。淺溝槽隔離物106則提供了相鄰裝置間之隔離情形，且可避免了鄰近之半導體裝置構件間之漏電流情形。
於半導體裝置製程中，淺溝槽隔離物106可早於電晶體形成前先形成。淺溝槽隔離製程之主要步驟係關於蝕刻出數個溝槽之圖案、沈積一或多個介電材料(例如二氧化矽)以填滿此些溝槽，以及採用如化學機械研磨之技術以移除過量之介電材料。於第1圖中，淺溝槽隔離物106係首先形成，且接著蝕刻形成用於鰭型層104(例如Ge、SiGe、SiC或上述材料之組合)沈積之空間。或者，可於形成鰭型層104之後，接著蝕刻出溝槽，並接著填入介電材料於溝槽內以形成淺溝槽隔離物106。
第2圖顯示了於具有III-V上蓋層之具有應變鍺或應變矽鍺之鰭型場效應電晶體及/或多重閘場效應電晶體之一垂直型鰭狀結構之一電晶體閘極區域的製程過程中之一剖面圖。相較於第1圖，淺溝槽隔離物106係經過蝕刻而露出鰭型層104，以利後續之裝置製作。接著沈積上蓋層202以覆蓋鰭型層104。上蓋層202環繞了電晶體之閘極區內之電晶體通道周圍的鰭型層104。上蓋層202包括了一III-V族半導體之化合物，例如為GaAs、InGaAs、InAs、InSb、GaSb、GaN、InP或上述材料之組合，或其他之適當材料。更特別地，基於晶格不匹配(lattice matching)之情形，可使用如InGaAs材質之上蓋層202於如Ge材質之鰭型層104之上，或使用如GaAs材質之上蓋層202於如SiGe材質之鰭型層104之上。
介於上蓋層202與基板102間之晶格不匹配情形係高於介於鰭型層104與基板102間之晶格不匹配情形。舉例來說，介於如InGaAs材質之上蓋層202與如矽材質之基板102間之晶格不匹配情形較如Ge材質之鰭型層104與如矽材質之基板102間之晶格不匹配情形高出了約4%。基於上述之較高不匹配情形係起因於III-V族化合物上蓋層202的採用，上蓋層202將施加應變至鰭型層104。而當鰭型層104係作為半導體電晶體之通道時，上述應變可增加通過經拉伸應變之鰭型層(例如為Ge材料)104之遷移率(mobility)，因此達成了通道的較高遷移率。
舉例來說，相較鍺之4000 cm2 /V‧s、矽之1400 cm2 /V‧s或GaAs之8500 cm2 /V‧s之電子遷移率，經1.5%拉伸應變之Ge可表現出了約為12000 cm2 /V‧s之電子遷移率。此外，相較於鍺之2000 cm2 /V‧s，矽之450 cm2 /V‧s或GaAs之400 cm2 /V‧s之電子遷移率，1.5%之經拉伸應變之Ge可表現出了約為20000 cm2 /V‧s之電子遷移率。因此，如第2圖所示結構可藉由於鰭型層104之頂部上具有一III-V半導體化合物上蓋層202而提供了一高速CMOS通道。
再者，可於上蓋層202之上沈積一高介電常數介電層(未顯示)。相較於介於高介電常數介電層與鍺材質之鰭型層104間之習知不良介面，此III-V族半導體化合物之上蓋層202可作為緩衝之用並提供了介於高介電常數介電層與鰭型層104間之較佳介面。上述功效係基於材料特性，即位於InGaAs上之閘介電層較位於Ge上閘介電層可表現出較低之介面缺陷密度(interface defect density)。
本發明之優點包括了基於前述之較高晶格不匹配情形所形成之高拉伸應變鰭型場效應電晶體(FinFET)裝置與多重閘場效應電晶體裝置，藉由採用較高晶格不匹配常數材料可造成極高遷移率之通道。此外，可於Ge材質以及高Ge含量之SiGe裝置內採用III-V族上蓋層以改善閘介電物之介面。熟悉此技藝者可以理解本發明之實施例皆可視實際情形而稍作改變。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102．．．基板
104．．．鰭型物
106．．．淺溝槽隔離物
202．．．上蓋層
第1圖顯示了於具有應變鍺或應變矽鍺之鰭型場效應電晶體及/或多重閘場效應電晶體之一垂直型鰭狀結構之一電晶體閘極區域的製程過程中之一剖面圖；以及
第2圖顯示了於具有III-V上蓋層之具有應變鍺或應變矽鍺之鰭型場效應電晶體及/或多重閘場效應電晶體之一垂直型鰭狀結構之一電晶體閘極區域的製程過程中之一剖面圖。
102．．．基板
104．．．鰭型物
106．．．淺溝槽隔離物
202．．．上蓋層

Claims (10)

  1. 一種用於半導體電晶體之垂直鰭狀結構，包括：一半導體基板；一鰭型層，位於該半導體基板之頂部；以及一上蓋層，覆蓋該鰭型層且直接接觸該鰭型層，其中該半導體基板包括一IV族半導體材料，該鰭型層包括一IV族半導體材料，該上蓋層包括一III-V族半導體化合物，該鰭型層作為該半導體電晶體之通道層，而該上蓋層施加應變至該鰭型層之上以增加通過該通道層之遷移率。
  2. 如申請專利範圍第1項所述之用於半導體電晶體之垂直鰭狀結構，其中該鰭型層包括Ge、SiGe、SiC或上述材料之組合，該半導體基板包括Si、Ge、SiGe或SiC，該上蓋層包括GaAs、InGaAs、InAs、InSb、GaSb、GaN、InP或上述材料之組合。
  3. 如申請專利範圍第1項所述之用於半導體電晶體之垂直鰭狀結構，其中該上蓋層與該半導體基板之間具有多於4%之晶格不相稱情形。
  4. 如申請專利範圍第1項所述之用於半導體電晶體之垂直鰭狀結構，其中該鰭型層係位於用於形成鄰近裝置間之隔離情形之數個淺溝槽隔離層之間。
  5. 一種用於半導體電晶體之垂直鰭狀結構之製造方法，包括：提供一半導體基板，其中該半導體基板包括一IV族半導體材料； 沈積一鰭型層於該半導體基板之頂部上且直接接觸該鰭型層，其中該鰭型層包括了IV族半導體材料且作為該半導體電晶體之一通道；以及沈積一上蓋層於該鰭型層之上，其中該上蓋層包括III-V族半導體化合物且施加應變於該鰭型層之上以增加通過該通道之遷移率。
  6. 如申請專利範圍第5項所述之用於半導體電晶體之垂直鰭狀結構之製造方法，其中該鰭型層包括Ge、SiGe、SiC或上述材料之組合，該半導體基板包括Si、Ge、SiGe或SiC，該上蓋層包括GaAs、InGaAs、InAs、InSb、GaSb、GaN、InP或上述材料之組合。
  7. 如申請專利範圍第5項所述之用於半導體電晶體之垂直鰭狀結構之製造方法，其中該上蓋層與該半導體基板之間具有多於4%之晶格不相稱情形。
  8. 如申請專利範圍第5項所述之用於半導體電晶體之垂直鰭狀結構之製造方法，更包括：早於沈積該鰭型層之前，沈積用於隔離鄰近裝置之一淺溝槽隔離層；以及蝕刻該淺溝槽隔離層以形成用於該鰭型層之空間。
  9. 一種用於半導體電晶體之垂直鰭狀結構，包括：一半導體基板；一鰭型層，位於該半導體基板之頂部；以及一上蓋層，覆蓋該鰭型層且直接接觸該鰭型層，其中該半導體基板包括Si、Ge、SiGe或SiC，該鰭型層包括Ge、SiGe、SiC或上述材料之組合，該上蓋層 包括GaAs、InGaAs、InAs、InSb、GaSb、GaN、InP或上述材料之組合，該上蓋層與該半導體基板之間具有多於4%之晶格不相稱情形，該鰭型層作為該半導體電晶體之通道層，而該上蓋層施加應變至該鰭型層之上以增加通過該通道層之遷移率。
  10. 如申請專利範圍第9項所述之用於半導體電晶體之垂直鰭狀結構，其中該鰭型層係位於用於形成鄰近裝置間之隔離之數個淺溝槽隔離層之間。
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