TWI514580B - 半導體元件與其形成方法 - Google Patents
半導體元件與其形成方法 Download PDFInfo
- Publication number
- TWI514580B TWI514580B TW102129758A TW102129758A TWI514580B TW I514580 B TWI514580 B TW I514580B TW 102129758 A TW102129758 A TW 102129758A TW 102129758 A TW102129758 A TW 102129758A TW I514580 B TWI514580 B TW I514580B
- Authority
- TW
- Taiwan
- Prior art keywords
- source
- fin
- drain
- lattice constant
- region
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 100
- 239000004065 semiconductor Substances 0.000 title claims description 96
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000463 material Substances 0.000 claims description 82
- 239000000758 substrate Substances 0.000 claims description 49
- 238000002955 isolation Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 4
- 229910001257 Nb alloy Inorganic materials 0.000 claims description 3
- 230000000881 depressing effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 61
- 230000008569 process Effects 0.000 description 60
- 229910052732 germanium Inorganic materials 0.000 description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910001152 Bi alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 2
- 229910001362 Ta alloys Inorganic materials 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910001922 gold oxide Inorganic materials 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- GPMBECJIPQBCKI-UHFFFAOYSA-N germanium telluride Chemical compound [Te]=[Ge]=[Te] GPMBECJIPQBCKI-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本發明係關於半導體元件，更特別關於鰭狀場效電晶體與其形成方法。
半導體積體電路(IC)產業呈指數成長。IC材料與設計的技術進步，使每一代的IC比前一代的IC更小且其電路更複雜。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線元件數目)，與較小的尺寸(比如製程形成的最小構件或連線)。製程尺寸縮小往往有利於增加製程效率並降低相關成本。
製程尺寸縮小會增加製程複雜度，但製程尺寸縮小的優點顯而易見，因此需要更小的IC製程。舉例來說，三維電晶體如鰭狀場效電晶體(FinFET)可用以取代平面電晶體。雖然現有的FinFET元件與其形成方法適用於特定目的，但仍無法適用於所有領域。舉例來說，施加應力至FinFET的閘極通道仍需改良製程。
本發明一實施例提供一種半導體元件，包括：基板；鰭狀物位於基板上，且鰭狀物係由具有第一晶格常數之第一半導體材料組成；閘極區形成於基板上的部份鰭狀物上；源
極區與汲極區，被基板上的閘極區隔開；以及具有第一厚度之源極/汲極堆疊位於源極區與汲極區上，其中源極/汲極堆疊之下半部為具有第二晶格常數之第二半導體材料，源極/汲極堆疊之下半部接觸閘極區中的鰭狀物的下半部，且第二晶格常數實質上小於第一晶格常數；其中源極/汲極堆疊之上半部為具有第三晶格常數之第三半導體材料，源極/汲極堆疊之上半部接觸閘極區中的鰭狀物的上半部，第三半導體材料位於第二半導體材料的頂部上，第三半導體材料具有第二厚度，且第三晶格常數大於或等於第一晶格常數。
本發明一實施例提供一種半導體元件，包括：基板，具有第一鰭狀物；第二鰭狀物位於第一鰭狀物之頂部上，且第二鰭狀物為磊晶成長鍺；閘極區形成於部份第二鰭狀物上；源極區與汲極區，被基板上的閘極區隔開；以及源極/汲極堆疊位於源極區與汲極區上，源極/汲極堆疊與閘極區中的第二鰭狀物相鄰，且源極/汲極堆疊具有第一厚度；其中源極/汲極堆疊之下半部接觸第二鰭狀物的下半部，且源極/汲極堆疊之下半部為磊晶成長矽鍺合金；其中源極/汲極堆疊之上半部接觸閘極區中第二鰭狀物的上半部，源極/汲極堆疊之上半部為磊晶成長鍺，且源極/汲極堆疊之上半部位於源極/汲極堆疊之下半部的頂部上並具有第二厚度。
本發明一實施例提供一種鰭狀物場效電晶體元件的形成方法，包括：提供基板，且基板具有多個第一鰭狀物與位於第一鰭狀物之間的多個隔離區；使第一鰭狀物凹陷；磊晶成長具有第一晶格常數之第一半導體材料，以形成多個第二鰭
狀物於凹陷的第一鰭狀物上；形成虛置閘極堆疊於部份第二鰭狀物上，其中部份第二鰭狀物被定義為閘極區；使虛置閘極堆疊附近的部份第二鰭狀物凹陷，以形成源極/汲極區；磊晶成長具有第二晶格常數之第二半導體材料於源極/汲極區中，以形成源極/汲極堆疊的下半部，其中第二半導體材料接觸閘極區中的第二鰭狀物的下半部，且第二晶格常數實質上小於第一晶格常數；以及磊晶成長具有第三晶格常數之第三半導體材料於源極/汲極區中，以形成源極/汲極堆疊的上半部，其中第三半導體材料接觸閘極區中的第二鰭狀物的上半部，且第三晶格常數實質上大於第二晶格常數。
t、T‧‧‧厚度
100‧‧‧方法
102、104、106、108、110、112、114、116‧‧‧步驟
200‧‧‧FinFET元件
210‧‧‧基板
220‧‧‧第一鰭狀物
230‧‧‧隔離區
310‧‧‧凹陷溝槽
320‧‧‧第一半導體材料層
410‧‧‧第二鰭狀物
412‧‧‧源極/汲極區
413‧‧‧閘極區
510‧‧‧閘極堆疊
512‧‧‧介電層
514‧‧‧多晶矽層
520‧‧‧側壁間隔物
610‧‧‧第二半導體材料層
615‧‧‧第一界面
616‧‧‧第二界面
620‧‧‧第三半導體材料層
630‧‧‧源極/汲極堆疊
第1圖係本發明多種實施例中，製作FinFET元件的方法流程圖；第2至5圖係根據第1圖中的方法，不同製程階段中FinFET元件的剖視圖；第6圖係本發明多種實施例中，FinFET元件的透視圖；以及第7至10圖係沿著第6圖中A-A切線的FinFET元件其剖視圖。
下述揭露內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含
兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例將重複標號及/或符號以簡化並清楚說明。然而不同實施例中，具有相同標號的元件並不必然具有相同的對應關係及/或排列。
本發明係關於但不限定於鰭狀場效電晶體(FinFET)元件，比如互補式金氧半(CMOS)元件，其包括p型金氧半(PMOS)FinFET元件與n型金氧半(NMOS)FinFET元件。下述內容將以FinFET為例說明本發明的多種實施例。可以理解的是，本發明除了特別申請專利範圍的部份外，並不限定於特定種類的元件。
第1圖係本發明中製作FinFET元件200之方法100的流程圖。第2至10圖係根據第1圖之方法100，在不同製程階段中FinFET元件200的圖式。方法100與FinFET元件200將搭配第1至10圖說明。可以理解的是，在方法100之前、之中、或之後可進行額外步驟。在其他實施例中，可將這些步驟取代為其他步驟或省略這些步驟。
如第1及2圖所示，方法100之起始步驟102為提供基板210。基板210可為基體矽基板。在另一實施例中，基板210可為半導體元素如結晶矽或結晶鍺、半導體化合物如矽化鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦、或上述之組合。基板210亦可包含絕緣層上矽(SOI)基板，其形成方法可為佈植氧加以分離(SIMOX)、晶圓接合、及/或其他合適方法。
某些實施例中，基板210亦包含絕緣層。絕緣層
包含任何合適的材料，比如氧化矽、氧化鋁、及/或上述之組合。在一實施例中，絕緣層可為埋置氧化層(BOX)。絕緣層之形成方法可為任何合適製程，比如SIMOX、氧化、沉積、及/或其他合適製程。在某些FinFET前驅結構的實施例中，絕緣層為絕緣層上矽基板的某一構件(如層狀物)。
如本技術領域中具有通常知識者所知，基板210可依需包含多種掺雜區。掺雜區可掺雜p型掺質如硼或BF2，n型掺質如磷或砷、或上述之組合。掺雜區可直接形成於基板210上、p型井結構中、n型井結構中、或雙重井結構中，或採用凸起的結構。基板210可進一步包含多種主動區，比如n型金氧半電晶體元件的區域或p型金氧半電晶體元件的區域。
第一鰭狀物220係形成於基板210上。在某些實施例中，基板210包含多個第一鰭狀物220。第一鰭狀物220可由任何合適的製程形成，比如多種沉積、微影、及/或蝕刻製程。舉例來說，微影製程包含形成光阻層於基板(如矽基板)上，以光罩圖案曝光光阻層，進行曝光後烘烤，以及顯影光阻層以形成含有光阻的遮罩單元。接著以遮罩單元蝕刻基板210以形成鰭狀結構。以反應性離子蝕刻(RIE)製程及/或其他合適製程，蝕刻未受遮罩單元保護的部份基板。在一實施例中，第一鰭狀物220的形成方法為圖案化與蝕刻部份矽基板210。在另一實施例中，第一鰭狀物220之形成方法為圖案化與蝕刻沉積於絕緣層上的矽層，比如SOI基板之矽-絕緣-矽堆疊中較上方的矽層。除了習知的微影製程外，第一鰭狀物220之形成方法可為雙重圖案化微影(DPL)製程。DPL製程將圖案分為兩個
交錯的圖案，並以此作為基板上的圖案。DPL製程可增加結構如鰭狀物的密度。DPL的方法理論包括雙重曝光(比如兩個光罩組)、形成鄰近結構的間隔物後移除結構以提供間隔物圖案、光阻凍結、及/或其他合適製程。可以理解的是，類似方法可用以形成多個平行的第一鰭狀物220。
多種隔離區230係形成於基板210上以隔離主動區。舉例來說，隔離區230分隔多個第一鰭狀物220。隔離區230的形成方法可為習知的隔離技術，比如以淺溝槽隔離(STI)以定義並電性隔離多個區域。隔離區230包含氧化矽、氮化矽、氮氧化矽、氣隙、其他合適材料、或上述之組合。隔離區230之形成方法可為任何合適製程。在一實施例中，STI的形成方法包括微影製程、蝕刻基板以形成溝槽於其中(比如乾蝕刻及/或濕蝕刻)、以及將一或多種介電材料填入溝槽中(比如化學氣相沉積製程)。在此實施例中，可填滿部份溝槽，使溝槽之間的基板維持鰭狀結構。在某些實施例中，填入溝槽中的層狀物為多層結構，比如熱氧化襯墊層上填有氮化矽或氧化矽層。在一實施例中，以化學機械研磨(CMP)製程移除多餘的介電材料，並平坦化隔離區230之上表面與第一鰭狀物220之上表面。
如第1及3圖所示，方法100之步驟104使第一鰭狀物220凹陷，以形成凹陷溝槽310。上述凹陷製程可為乾蝕刻製程、濕蝕刻製程、及/或上述之組合。凹陷製程亦可為選擇性濕蝕刻或選擇性乾蝕刻。濕蝕刻包含氫氧化四甲基銨(TMAH)溶液、HF/HNO3
/CH3
COOH溶液、或其他合適溶液。乾蝕刻與濕蝕刻製程的可調參數包括蝕刻品種類、蝕刻溫度、
蝕刻溶液濃度、蝕刻壓力、蝕刻源功率、射頻偏壓、射頻偏壓功率、蝕刻品流速、與其他合適參數。舉例來說，濕蝕刻溶液可包含氨水(NH4
OH)、氫氧化鉀(KOH)、氫氟酸(HF)、氫氧化四甲基銨(TMAH)、其他合適的濕蝕刻溶液、或上述之組合。乾蝕刻製程可為採用含氯化學品的偏壓電漿蝕刻製程。其他乾蝕刻氣體可為四氟化碳、三氟化氮、六氟化硫、及氦氣。乾蝕刻亦可為非等向蝕刻，其機制為深反應性離子蝕刻(DRIE)。
如第1及4圖所示，方法100之步驟106沉積第一半導體材料層320於凹陷的第一鰭狀物220的頂部上，且第一半導體材料層320填入凹陷溝槽310中。第一半導體材料層320之沉積方法可為磊晶成長製程。第一半導體材料層320之材料可為單一半導體元素如鍺或矽，半導體化合物如砷化鎵(GaAs)或砷化鋁鎵(AlGaAs)，或半導體合金如矽鍺合金(SiGe)或砷磷化鎵(GaAsP)。磊晶製程可為CVD沉積技術如氣相磊晶(VPE)及/或超高真空CVD(UHV-CVD)、分子束磊晶(MBE)、及/或其他合適製程。
在一實施例中，第一半導體材料層320包含磊晶成長的鍺層。在另一實施例中，第一半導體材料層320包含磊晶成長的矽鍺合金(Si1-x
Gex
，x指的是Ge組成的原子比例)。藉由調整磊晶成長製程的條件如壓力、氣體流量、及溫度，可控制第一半導體材料層320如SiGe層中的Ge比例。此外，可進行CMP製程以移除多餘的第一半導體材料層320，並平坦化第一半導體材料320與隔離區230之上表面。
如第1及5圖所示，方法100之步驟108使圍繞
第一半導體材料層320之隔離區230凹陷，以露出第一半導體材料層320的上半部，進而形成第二鰭狀物410於凹陷的第一鰭狀物220上。上述凹陷製程可為乾蝕刻製程、濕蝕刻製程、及/或上述之組合。
如第6圖所示，某些實施例中的第二鰭狀物410具有源極/汲極區412與閘極區413。在某些實施例中，源極/汲極區412中的一者為源極區，且另一者為汲極區。閘極區413係位於源極/汲極區412之間。
如第1及7圖所示，方法100之步驟110形成閘極堆疊510於閘極區413上，而側壁間隔物520係沿著閘極堆疊510。在先形成閘極的製程中，閘極堆疊510可為部份或全部的功能性閘極。相反地，在後形成閘極的製程中，閘極堆疊510可為虛置閘極。在此實施例中，閘極堆疊為虛置閘極。在高溫製程如形成源極/汲極的熱製程後，可將虛置的閘極堆疊510置換為高介電常數之閘極介電層與金屬閘極。上述置換製程包含移除虛置閘極堆疊以形成閘極溝槽，以及形成高介電常數的閘極介電層/金屬閘極於閘極溝槽中。虛置的閘極堆疊510可包含介電層512與多晶矽層514。虛置的閘極堆疊510之形成方法可為任何合適製程。舉例來說，閘極堆疊510之形成方法可包含沉積、微影圖案化、與蝕刻製程。沉積製程可為CVD、PVD、ALD、其他合適方法、及/或上述之組合。微影圖案化製程包含塗佈光阻(比如旋轉塗佈法)、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影光阻、潤濕、乾燥(硬烘烤)、其他合適製程、及/或上述之組合。蝕刻製程包括乾蝕刻、濕蝕刻、及/或其他
蝕刻方法(比如反應性離子蝕刻)。介電層512可為氧化矽、氮化矽、或其他合適材料。
側壁間隔物520可為介電材料如氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合。側壁間隔物520可為多層結構。一般形成側壁間隔物520的方法包括沉積介電材料於閘極堆疊510上，再非等向回蝕刻介電材料。回蝕刻製程可為多重步驟蝕刻，以達蝕刻選擇性、製程彈性、與所需的過蝕刻控制。
如第1及8圖所示，方法100之步驟112移除源極/汲極區412中至少部份的第二鰭狀物410。部份第二鰭狀物410的移除方法為乾蝕刻製程、濕蝕刻製程、及/或上述之組合。
如第1及9圖所示，方法100之步驟114沉積第二半導體材料層610於源極/汲極區412中，以形成源極/汲極堆疊630的下半部。在源極/汲極區412中的第二半導體材料610，其側表面與閘極區413中的第二鰭狀物410的下半部接觸的部份為第一界面615。第二半導體材料層610可為Ge、Si、SiGe、GaAs、AlGaAs、GaAsP、或其他合適的半導體材料。第二半導體材料層610之沉積法可為磊晶製程。
如第1及10圖所示，方法100之步驟116沉積第三半導體材料層620於源極/汲極區412中的第二半導體材料層610上，以形成源極/汲極堆疊630的上半部。第三半導體材料層620可為Ge、Si、SiGe、GaAs、AlGaAs、GaAsP、或其他合適的半導體材料。第三半導體材料層620之形成方法與第9圖中類似材料之形成方法類似。在源極/汲極區412中的
第三半導體材料620，其側表面與閘極區413中的第二鰭狀物410的上半部接觸的部份為第二界面616。
在第10圖中，本實施例的源極/汲極堆疊630中的第三半導體材料層620之晶格常數(稱為第三晶格常數)，實質上大於第二半導體材料層610之晶格常數(稱為第二晶格常數)。第三晶格常數大於或等於第一半導體材料層320之晶格常數(稱為第一晶格常數)。舉例來說，第二半導體材料層610為Si1-y
Gey
，其中y為Ge之原子比百分比，第二晶格常數介於約5.526至約5.549之間，且y介於0.45至0.55之間。第三半導體材料層620與第一半導體材料層320類似，亦為Si1-x
Gex
，其中第三晶格常數介於約5.645至約5.658之間，且x介於0.95至1.0之間。同樣在本實施例的源極/汲極堆疊630中，第三半導體材料層620之厚度(t)與源極/汲極堆疊630之總厚度(T)的比例需符合元件效能的標準如通道遷移率。舉例來說，t/T介於約0.1至約0.8之間。可以相信的是，當不匹配的第一、第二、與第三晶格常數搭配t/T厚度比例，可引發多種程度的應力至閘極區413中的閘極通道。如此一來，源極/汲極堆疊630可作為源極/汲極應力源。
FinFET元件200可進一步進行閘極置換製程，將虛置的閘極堆疊510置換為高介電常數的閘極介電層與金屬閘極。FinFET元件200可進一步搭配CMOS或MOS製程以形成多種本技術領域所熟知的結構與區域。舉例來說，後續製程可形成多種接點/通孔/線路與多層內連線結構(比如金屬層與層間介電層)於基板210上，以連接FinFET元件之多種結構。舉
例來說，多層內連線包含垂直內連線如習知通孔或接點，與水平內連線如金屬線路。多種內連線結構可採用多種導電材料如銅、鎢、及/或金屬矽化物。在一實施例中，可採用鑲嵌及/或雙鑲嵌製程以形成銅的多層內連線結構。
在方法100之前、之中、或之後可進行額外步驟，且某些實施例可將某些步驟取代為其他步驟或省略某些步驟。
綜上所述，本發明提供之半導體元件具有源極/汲極堆疊應力源，以提供有效應力至閘極通道。藉由選擇源極/汲極堆疊應力源之材料的晶格常數與厚度比例，可引發不同程度的應力至半導體元件的閘極通道，進而改善元件效能。源極/汲極堆疊應力源亦具有製程彈性，即可視情況採用承受較高熱預算的材料。舉例來說，源極/汲極堆疊應力源可採用矽鍺合金而非錫鍺合金，因矽鍺合金之熔點高於錫鍺合金。
本發明提供多種半導體元件的不同實施例，其源極/汲極堆疊比現有技術相較有許多改良。半導體元件包括：基板；鰭狀物結構位於基板上，且鰭狀物結構係由具有第一晶格常數之第一半導體材料組成。閘極區形成於基板上的部份鰭狀物上，而源極區與汲極區，被基板上的閘極區隔開。具有厚度(T)之源極/汲極堆疊位於源極區與汲極區上。源極/汲極堆疊之下半部為具有第二晶格常數之第二半導體材料，源極/汲極堆疊之下半部接觸閘極區中鰭狀物的下半部，且第二晶格常數實質上小於第一晶格常數。源極/汲極堆疊之上半部為具有第三晶格常數之第三半導體材料，源極/汲極堆疊之上半部接觸閘極區中鰭狀物上半部，第三半導體材料位於第二半導體材料
的頂部上，第三半導體材料具有厚度(t)，且第三晶格常數大於或等於第一晶格常數。
在另一實施例中，FinFET元件包括基板，具有第一鰭狀物。第二鰭狀物位於第一鰭狀物之頂部上，且第二鰭狀物為磊晶成長鍺。閘極區形成於部份第二鰭狀物上。源極區與汲極區，被基板上的閘極區隔開。源極/汲極堆疊位於源極區與汲極區上，源極/汲極堆疊與閘極區中的第二鰭狀物相鄰，且源極/汲極堆疊具有厚度(T)。源極/汲極堆疊之下半部接觸第二鰭狀物的下半部，且源極/汲極堆疊之下半部為磊晶成長矽鍺合金。源極/汲極堆疊之上半部接觸閘極區中第二鰭狀物的上半部，該源極/汲極堆疊之上半部為磊晶成長鍺，且源極/汲極堆疊之上半部位於源極/汲極堆疊之下半部的頂部上。
在又一實施例中，FinFET元件的形成方法包括提供基板，且基板具有多個第一鰭狀物與位於第一鰭狀物之間的多個隔離區。使第一鰭狀物凹陷，磊晶成長具有第一晶格常數之第一半導體材料，以形成多個第二鰭狀物於凹陷的第一鰭狀物上。形成虛置閘極堆疊於部份第二鰭狀物上，使虛置閘極堆疊附近的其他部份第二鰭狀物凹陷，以形成源極/汲極區。磊晶成長具有第二晶格常數之第二半導體材料於源極/汲極區中，以形成源極/汲極堆疊的下半部，其中第二半導體材料接觸閘極區中的第二鰭狀物的下半部，且第二晶格常數實質上小於第一晶格常數。磊晶成長具有第三晶格常數之第三半導體材料於源極/汲極區中，以形成源極/汲極堆疊的上半部，其中第三半導體材料接觸閘極區中的第二鰭狀物的上半部，且第三晶
格常數實質上大於第二晶格常數。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
t、T‧‧‧厚度
210‧‧‧基板
320‧‧‧第一半導體材料層
412‧‧‧源極/汲極區
413‧‧‧閘極區
512‧‧‧介電層
514‧‧‧多晶矽層
520‧‧‧側壁間隔物
610‧‧‧第二半導體材料層
615‧‧‧第一界面
616‧‧‧第二界面
620‧‧‧第三半導體材料層
630‧‧‧源極/汲極堆疊
Claims (10)
- 一種半導體元件，包括：一基板；一鰭狀物位於該基板上，且該鰭狀物係由具有一第一晶格常數之一第一半導體材料組成；一閘極區形成於該基板上的部份該鰭狀物上；一源極區與一汲極區，被該基板上的該閘極區隔開；以及一具有第一厚度之一源極/汲極堆疊位於該源極區與該汲極區上；其中該源極/汲極堆疊之下半部為具有一第二晶格常數之一第二半導體材料，該源極/汲極堆疊之下半部接觸該閘極區中的該鰭狀物的下半部，且該第二晶格常數實質上小於該第一晶格常數；其中該源極/汲極堆疊之上半部為具有一第三晶格常數之一第三半導體材料，該源極/汲極堆疊之上半部接觸該閘極區中的該鰭狀物的上半部，該第三半導體材料位於該第二半導體材料的頂部上，該第三半導體材料具有一第二厚度，且該第三晶格常數大於或等於該第一晶格常數。
- 如申請專利範圍第1項所述之半導體元件，其中該鰭狀物的該第一半導體材料包括一磊晶成長材料，該源極/汲極堆疊之下半部的該第二半導體材料包括一磊晶成長材料，及/或該源極/汲極堆疊之上半部的該第三半導體材料包括一磊晶成長材料。
- 如申請專利範圍第1項所述之半導體元件，其中該第二晶 格常數介於約5.526至約5.549之間，且該第三晶格常數介於約5.645至約5.658之間。
- 如申請專利範圍第1項所述之半導體元件，其中該第二厚度/該第一厚度之比例介於約0.1至約0.8之間。
- 一種半導體元件，包括：一基板，具有一第一鰭狀物；一第二鰭狀物位於該第一鰭狀物之頂部上，且該第二鰭狀物為磊晶成長鍺；一閘極區形成於部份該第二鰭狀物上；一源極區與一汲極區，被該基板上的該閘極區隔開；以及一源極/汲極堆疊位於該源極區與該汲極區上，該源極/汲極堆疊與該閘極區中的該第二鰭狀物相鄰，且該源極/汲極堆疊具有一第一厚度；其中該源極/汲極堆疊之下半部接觸該第二鰭狀物的下半部，且該源極/汲極堆疊之下半部為磊晶成長矽鍺合金；其中該源極/汲極堆疊之上半部接觸該閘極區中該第二鰭狀物的上半部，該源極/汲極堆疊之上半部為磊晶成長鍺，且該源極/汲極堆疊之上半部位於該源極/汲極堆疊之下半部的頂部上並具有一第二厚度。
- 如申請專利範圍第5項所述之半導體元件，其中該第二厚度/該第一厚度之比例介於約0.1至約0.8之間。
- 一種半導體元件的形成方法，包括：提供一基板，且該基板具有多個第一鰭狀物與位於該些第一鰭狀物之間的多個隔離區； 使該些第一鰭狀物凹陷；磊晶成長具有一第一晶格常數之一第一半導體材料，以形成多個第二鰭狀物於凹陷的該些第一鰭狀物上；形成一虛置閘極堆疊於部份該些第二鰭狀物上，其中部份該些第二鰭狀物被定義為一閘極區；使該虛置閘極堆疊附近的部份該些第二鰭狀物凹陷，以形成一源極/汲極區；磊晶成長具有一第二晶格常數之一第二半導體材料於該源極/汲極區中，以形成一源極/汲極堆疊的下半部，其中該第二半導體材料接觸該閘極區中的該第二鰭狀物的下半部，且該第二晶格常數實質上小於該第一晶格常數；以及磊晶成長具有一第三晶格常數之一第三半導體材料於該源極/汲極區中，以形成該源極/汲極堆疊的上半部，其中該第三半導體材料接觸該閘極區中的該第二鰭狀物的上半部，且該第三晶格常數實質上大於該第二晶格常數。
- 如申請專利範圍第7項所述之半導體元件的形成方法，其中該第一晶格常數介於約5.645至約5.658之間，且該第二晶格常數介於約5.526至約5.549之間。
- 如申請專利範圍第7項所述之半導體元件的形成方法，其中該第三半導體材料之厚度與該源極/汲極堆疊之厚度之間的比例介於約0.1至約0.8之間。
- 如申請專利範圍第7項所述之半導體元件的形成方法，更包括：移除該虛置閘極堆疊以形成一閘極溝槽；以及 形成一高介電常數之閘極介電層與一金屬閘極於該閘極溝槽中。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/631,688 US8633516B1 (en) | 2012-09-28 | 2012-09-28 | Source/drain stack stressor for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201413967A TW201413967A (zh) | 2014-04-01 |
| TWI514580B true TWI514580B (zh) | 2015-12-21 |
Family
ID=49919233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102129758A TWI514580B (zh) | 2012-09-28 | 2013-08-20 | 半導體元件與其形成方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8633516B1 (zh) |
| KR (1) | KR101438290B1 (zh) |
| CN (1) | CN103715258B (zh) |
| TW (1) | TWI514580B (zh) |
Families Citing this family (88)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9553012B2 (en) | 2013-09-13 | 2017-01-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and the manufacturing method thereof |
| US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
| US9653461B2 (en) | 2014-03-28 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with low source/drain contact resistance |
| KR102216511B1 (ko) | 2014-07-22 | 2021-02-18 | 삼성전자주식회사 | 반도체 소자 |
| US9306067B2 (en) | 2014-08-05 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nonplanar device and strain-generating channel dielectric |
| KR102230198B1 (ko) | 2014-09-23 | 2021-03-19 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
| US9735256B2 (en) | 2014-10-17 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features |
| US9391201B2 (en) | 2014-11-25 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain structure and manufacturing the same |
| US9349652B1 (en) | 2014-12-12 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor device with different threshold voltages |
| US9780214B2 (en) | 2014-12-22 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including Fin- FET and manufacturing method thereof |
| US9768301B2 (en) | 2014-12-23 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Short channel effect suppression |
| US10141310B2 (en) | 2014-12-23 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Short channel effect suppression |
| US10134871B2 (en) | 2014-12-23 | 2018-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of high-K dielectric oxide by wet chemical treatment |
| US9515071B2 (en) | 2014-12-24 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Asymmetric source/drain depths |
| US9601574B2 (en) * | 2014-12-29 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | V-shaped epitaxially formed semiconductor layer |
| US9425250B2 (en) | 2014-12-30 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor with wurtzite channel |
| US9647090B2 (en) | 2014-12-30 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface passivation for germanium-based semiconductor structure |
| US9601626B2 (en) | 2015-01-23 | 2017-03-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structure with two channel layers and manufacturing method thereof |
| US9443729B1 (en) | 2015-03-31 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming FinFET devices |
| US9590102B2 (en) | 2015-04-15 | 2017-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9680014B2 (en) | 2015-04-17 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including Fin structures and manufacturing method thereof |
| US10026830B2 (en) * | 2015-04-29 | 2018-07-17 | Stmicroelectronics, Inc. | Tunneling field effect transistor (TFET) having a semiconductor fin structure |
| US9570557B2 (en) | 2015-04-29 | 2017-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Tilt implantation for STI formation in FinFET structures |
| US9461110B1 (en) | 2015-04-30 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETs and methods of forming FETs |
| US9773786B2 (en) | 2015-04-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETs and methods of forming FETs |
| US10269968B2 (en) | 2015-06-03 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
| US9449975B1 (en) | 2015-06-15 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices and methods of forming |
| US9647071B2 (en) | 2015-06-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFET structures and methods of forming the same |
| EP3314644B1 (en) | 2015-06-24 | 2023-12-20 | Intel Corporation | Replacement channel etch for high quality interface |
| US9425313B1 (en) | 2015-07-07 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9953881B2 (en) | 2015-07-20 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a FinFET device |
| US9472620B1 (en) | 2015-09-04 | 2016-10-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including fin structures and manufacturing method thereof |
| US9680017B2 (en) | 2015-09-16 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including Fin FET and manufacturing method thereof |
| KR102323943B1 (ko) | 2015-10-21 | 2021-11-08 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
| US10121858B2 (en) | 2015-10-30 | 2018-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Elongated semiconductor structure planarization |
| US9960273B2 (en) | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
| US9620503B1 (en) * | 2015-11-16 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor and method for fabricating the same |
| US10032627B2 (en) | 2015-11-16 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming stacked nanowire transistors |
| US9887269B2 (en) | 2015-11-30 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
| US9564317B1 (en) | 2015-12-02 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a nanowire |
| US9716146B2 (en) | 2015-12-15 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure and method with solid phase diffusion |
| US9899269B2 (en) | 2015-12-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-gate device and method of fabrication thereof |
| US9660033B1 (en) | 2016-01-13 | 2017-05-23 | Taiwan Semiconductor Manufactuing Company, Ltd. | Multi-gate device and method of fabrication thereof |
| US9876098B2 (en) | 2016-01-15 | 2018-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a gate spacer |
| US10038095B2 (en) | 2016-01-28 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | V-shape recess profile for embedded source/drain epitaxy |
| US10453925B2 (en) | 2016-01-29 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth methods and structures thereof |
| US10141426B2 (en) * | 2016-02-08 | 2018-11-27 | International Business Macahines Corporation | Vertical transistor device |
| US10340383B2 (en) | 2016-03-25 | 2019-07-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having stressor layer |
| US10249501B2 (en) | 2016-03-28 | 2019-04-02 | International Business Machines Corporation | Single process for liner and metal fill |
| CN107275216A (zh) * | 2016-04-08 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
| US10164061B2 (en) | 2016-05-19 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating non-volatile memory device array |
| US10734522B2 (en) | 2016-06-15 | 2020-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure with gate stacks |
| US10008414B2 (en) | 2016-06-28 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for widening Fin widths for small pitch FinFET devices |
| US9620628B1 (en) | 2016-07-07 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming contact feature |
| US10269938B2 (en) | 2016-07-15 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure having a doped passivation layer |
| US10217741B2 (en) | 2016-08-03 | 2019-02-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure and method of forming same through two-step etching processes |
| US9853150B1 (en) | 2016-08-15 | 2017-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating epitaxial gate dielectrics and semiconductor device of the same |
| CN107799409B (zh) * | 2016-08-31 | 2020-12-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
| CN107799410A (zh) * | 2016-09-05 | 2018-03-13 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法、电子装置 |
| US9865589B1 (en) | 2016-10-31 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method of fabricating ESD FinFET with improved metal landing in the drain |
| US11152362B2 (en) * | 2016-11-10 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure |
| US9847334B1 (en) | 2016-11-18 | 2017-12-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with channel layer |
| US10879240B2 (en) | 2016-11-18 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device structure |
| US10134870B2 (en) | 2016-11-28 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and method of manufacturing the same |
| US10290546B2 (en) | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Threshold voltage adjustment for a gate-all-around semiconductor structure |
| US10062782B2 (en) | 2016-11-29 | 2018-08-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device with multilayered channel structure |
| US11011634B2 (en) | 2016-11-30 | 2021-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Elongated source/drain region structure in finFET device |
| US9865595B1 (en) | 2016-12-14 | 2018-01-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same |
| US9899273B1 (en) | 2016-12-15 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with dopants diffuse protection and method for forming the same |
| US10134915B2 (en) * | 2016-12-15 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | 2-D material transistor with vertical structure |
| US10522643B2 (en) | 2017-04-26 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate |
| US10522417B2 (en) | 2017-04-27 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET device with different liners for PFET and NFET and method of fabricating thereof |
| US10453753B2 (en) | 2017-08-31 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET |
| US10276697B1 (en) | 2017-10-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Negative capacitance FET with improved reliability performance |
| US10522557B2 (en) | 2017-10-30 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Surface topography by forming spacer-like components |
| US10366915B2 (en) | 2017-11-15 | 2019-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET devices with embedded air gaps and the fabrication thereof |
| US10510894B2 (en) | 2017-11-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structure having different distances to adjacent FinFET devices |
| US10854615B2 (en) | 2018-03-30 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET having non-merging epitaxially grown source/drains |
| US10665697B2 (en) | 2018-06-15 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
| US11302535B2 (en) | 2018-06-27 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Performing annealing process to improve fin quality of a FinFET semiconductor |
| US10388771B1 (en) | 2018-06-28 | 2019-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device for forming cut-metal-gate feature |
| US10790352B2 (en) | 2018-06-28 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | High density capacitor implemented using FinFET |
| US10886226B2 (en) | 2018-07-31 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co, Ltd. | Conductive contact having staircase barrier layers |
| US10998241B2 (en) | 2018-09-19 | 2021-05-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective dual silicide formation using a maskless fabrication process flow |
| US10971605B2 (en) | 2018-10-22 | 2021-04-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dummy dielectric fin design for parasitic capacitance reduction |
| US11728344B2 (en) | 2019-06-28 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid SRAM design with nano-structures |
| US11469238B2 (en) | 2019-09-26 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-interleaving N-well and P-well pickup region design for IC devices |
| US12046479B2 (en) | 2020-08-13 | 2024-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-containing STI liner for SiGe channel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200843107A (en) * | 2007-04-27 | 2008-11-01 | Taiwan Semiconductor Mfg | Semiconductor device |
| CN100449783C (zh) * | 2005-11-29 | 2009-01-07 | 台湾积体电路制造股份有限公司 | 具有体接触窗的鳍状场效应晶体管及其制造方法 |
| TW200919726A (en) * | 2007-10-16 | 2009-05-01 | Taiwan Semiconductor Mfg | Fin field-effect transistors |
| US20110237046A1 (en) * | 2010-03-29 | 2011-09-29 | Globalfoundries Inc. | Method of manufacturing a finned semiconductor device structure |
| US8084309B2 (en) * | 2009-08-17 | 2011-12-27 | International Business Machines Corporation | Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
| JP4310399B2 (ja) * | 2006-12-08 | 2009-08-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US7674669B2 (en) * | 2007-09-07 | 2010-03-09 | Micron Technology, Inc. | FIN field effect transistor |
| US7902009B2 (en) * | 2008-12-11 | 2011-03-08 | Intel Corporation | Graded high germanium compound films for strained semiconductor devices |
| US8623728B2 (en) * | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
| US8264032B2 (en) * | 2009-09-01 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accumulation type FinFET, circuits and fabrication method thereof |
| US8313999B2 (en) * | 2009-12-23 | 2012-11-20 | Intel Corporation | Multi-gate semiconductor device with self-aligned epitaxial source and drain |
| US8361847B2 (en) * | 2011-01-19 | 2013-01-29 | International Business Machines Corporation | Stressed channel FET with source/drain buffers |
-
2012
- 2012-09-28 US US13/631,688 patent/US8633516B1/en active Active
- 2012-12-26 KR KR1020120153330A patent/KR101438290B1/ko active IP Right Grant
-
2013
- 2013-01-18 CN CN201310020026.8A patent/CN103715258B/zh active Active
- 2013-08-20 TW TW102129758A patent/TWI514580B/zh active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100449783C (zh) * | 2005-11-29 | 2009-01-07 | 台湾积体电路制造股份有限公司 | 具有体接触窗的鳍状场效应晶体管及其制造方法 |
| TW200843107A (en) * | 2007-04-27 | 2008-11-01 | Taiwan Semiconductor Mfg | Semiconductor device |
| TW200919726A (en) * | 2007-10-16 | 2009-05-01 | Taiwan Semiconductor Mfg | Fin field-effect transistors |
| US8084309B2 (en) * | 2009-08-17 | 2011-12-27 | International Business Machines Corporation | Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask |
| US20110237046A1 (en) * | 2010-03-29 | 2011-09-29 | Globalfoundries Inc. | Method of manufacturing a finned semiconductor device structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103715258A (zh) | 2014-04-09 |
| KR20140042622A (ko) | 2014-04-07 |
| TW201413967A (zh) | 2014-04-01 |
| CN103715258B (zh) | 2016-08-17 |
| KR101438290B1 (ko) | 2014-09-04 |
| US8633516B1 (en) | 2014-01-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI514580B (zh) | 半導體元件與其形成方法 | |
| US11670717B2 (en) | Structure of S/D contact and method of making same | |
| US10468408B2 (en) | Fin-like field effect transistor (FinFET) device and method of manufacturing same | |
| TWI648856B (zh) | 半導體結構及其製造方法 | |
| US10090300B2 (en) | Fin-like field effect transistor (FinFET) device and method of manufacturing same | |
| CN107424933B (zh) | Finfet及形成finfet的方法 | |
| KR101376451B1 (ko) | ＦｉｎＦＥＴ 디바이스의 제조 방법 | |
| US8497177B1 (en) | Method of making a FinFET device | |
| US9153670B2 (en) | Semiconductor device and fabricating the same | |
| US8486770B1 (en) | Method of forming CMOS FinFET device | |
| US9349866B2 (en) | Structure and method for FinFET device | |
| CN106548944B (zh) | 半导体装置的制造方法 | |
| US9276117B1 (en) | Structure and method and FinFET device | |
| US9847329B2 (en) | Structure of fin feature and method of making same | |
| TWI569329B (zh) | 半導體裝置之製造方法 | |
| US11646238B2 (en) | Dual crystal orientation for semiconductor devices | |
| US20230067587A1 (en) | Semiconductor devices and methods of manufacturing thereof |