TWI642181B - Iii-v族環繞式閘極半導體元件及其製造方法 - Google Patents

Iii-v族環繞式閘極半導體元件及其製造方法 Download PDF

Info

Publication number
TWI642181B
TWI642181B TW104109930A TW104109930A TWI642181B TW I642181 B TWI642181 B TW I642181B TW 104109930 A TW104109930 A TW 104109930A TW 104109930 A TW104109930 A TW 104109930A TW I642181 B TWI642181 B TW I642181B
Authority
TW
Taiwan
Prior art keywords
nanostructure
semiconductor material
semiconductor
gate
crystalline semiconductor
Prior art date
Application number
TW104109930A
Other languages
English (en)
Other versions
TW201601308A (zh
Inventor
尼姆 瓦德羅
賽曼特 馬克林
奈丁 克拉特
Original Assignee
比利時商愛美科公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 比利時商愛美科公司 filed Critical 比利時商愛美科公司
Publication of TW201601308A publication Critical patent/TW201601308A/zh
Application granted granted Critical
Publication of TWI642181B publication Critical patent/TWI642181B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/413—Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明揭示一種環繞式閘極半導體元件及一種用於製造一環繞式閘極半導體元件之方法。該方法包括：在一半導體基板上，於淺溝渠隔離(STI)區域之間，提供由一源極及一汲極區域錨固之至少一經懸置奈米結構，該經懸置奈米結構包括不同於該半導體基板之一結晶半導體材料。提供圍繞該至少一經懸置奈米結構之一閘極堆疊。

Description

III-V族環繞式閘極半導體元件及其製造方法
本發明係關於一種半導體元件之製造方法，更具體言之，本發明係關於一種環繞式閘極(GAA)半導體元件之製造方法。本發明亦關於一種環繞式閘極(GAA)半導體元件，更具體言之，本發明亦關於一種環繞式閘極(GAA)奈米結構半導體元件。
對於在先進技術節點(10奈米及以上)處之CMOS，高遷移率材料(諸如III-V族材料)正備受關注。為滿足此等先進節點在短通道控制(諸如亞臨限值斜率及汲極引發之障壁降低)方面之所需規格，需要一個三閘極量子井結構或一環繞式閘極結構/奈米線(GAA/NW)結構來維持靜電控制。
迄今為止所知的III-V族GAA元件已藉由在一整個III-V族晶圓(通常2"或4"基板)上生長毯覆層來製作，如(例如)揭示於如IEEE IEDM 2011第769-772頁中公開的Gu等人所著的「First experimental demonstration of gate-all-around III-V MOSFETs by top-down approach」中。接著，圖案化異構層且經由一濕式蝕刻來移除虛設緩衝層以釋放奈米線。
然而，在300毫米或更大晶圓上以超大規模整合(VLSI)位準整合此等結構係一相當的技術挑戰。為具競爭性，III-V族材料應與Si單體 地整合以受益於現有基於Si之半導體處理。使用Si作為一基板亦將實現若干功能區塊在相同平台上的整合，諸如(例如)邏輯、高頻及I/O電路。
一第一態樣係關於一種環繞式閘極(GAA)半導體元件之製造方法。
一第二態樣係關於一種環繞式閘極(GAA)半導體元件。
本發明之一目的係提供一種環繞式閘極(GAA)半導體元件及一種此環繞式閘極(GAA)半導體元件之製造方法，其與當前及未來技術節點(1X技術節點及以下)相容，其中III-V族通道材料與基於半導體之基板(較佳地基於Si之基板)整合。
本發明揭示一種環繞式閘極(GAA)半導體元件之製造方法，該方法包括以下步驟：提供一第一結晶半導體材料之一半導體基板；在該半導體基板中形成淺溝渠隔離(STI)區域；在該半導體基板上形成複數個半導體鰭；該複數個半導體鰭包括在該第一結晶半導體材料上之一第二結晶半導體材料，該第二結晶半導體材料與該第一結晶半導體材料晶格失配，該複數個半導體鰭之各者形成於STI區域對之間，其中該複數個半導體鰭藉由該等STI區域彼此隔離；該複數個半導體鰭及該等STI區域鄰接於一共同平坦頂面上；在該複數個半導體鰭之各者之該第二結晶半導體材料上提供一第三結晶半導體材料之至少一奈米結構；在該至少一奈米結構上之虛設閘極之兩側處提供一源極及一汲極區域；移除該虛設閘極且其後移除該第二結晶半導體材料，藉此使由該源極及汲極區域錨固之該至少一奈米結構懸置；在移除該第二結晶半導體材料之後圍繞該至少一奈米結構提供一最終閘極堆疊。
較佳地，該第一結晶半導體材料包括矽。較佳地，該第二結晶半導體材料包括一III-V族材料。較佳地，該第三結晶半導體材料包括 不同於該第二結晶半導體材料之該III-V族材料之另一III-V族材料。
根據該第一態樣之實施例，提供至少一奈米結構包含提供僅一奈米結構。
根據該第一態樣之實施例，提供至少一奈米結構包含在該複數個半導體鰭之各者上提供兩個分離奈米結構。
根據該第一態樣之實施例，提供僅一奈米結構包括在該複數個半導體鰭之各者之該第二結晶半導體材料上磊晶生長該第三結晶半導體材料。歸因於該磊晶生長，該僅一奈米結構具有一錐形刻面。
根據該第一態樣之實施例，提供兩個奈米結構包括：自各鰭之一頂面，在該半導體鰭與該半導體鰭之相對側上之STI區域之間之介面處之該第二結晶半導體材料中提供兩個分離凹槽或間隙；在該第二結晶半導體材料上之該等凹槽或間隙中磊晶生長該第三結晶半導體材料；平坦化該第三結晶半導體材料，藉此顯露該等凹槽中該第三結晶半導體材料之兩個分離奈米結構。
根據該第一態樣之實施例，提供兩個分離凹槽或間隙包括執行該第二結晶半導體材料之一熱處理。較佳地，在500攝氏度與600攝氏度之間之一溫度下進行該熱處理。藉由該第二半導體材料之刻面來產生該兩個凹槽或間隙。
根據該第一態樣之實施例，該兩個奈米結構彼此相距一距離D，其中D大於該最終閘極堆疊之一厚度且小於該半導體鰭之寬度。
根據該第一態樣之實施例，藉由蝕刻完成移除該第二結晶半導體材料。
根據該第一態樣之實施例，形成半導體鰭包括使用ART在該等STI區域之間之該第一結晶半導體材料上磊晶生長該第二結晶半導體材料。
根據該第一態樣之實施例，該方法進一步包括：在移除該第二結晶半導體材料之前，蝕刻該等STI區域之一頂部部分使得該等STI區域之一各自頂面之一高度變得低於該等半導體鰭之一各自頂面之一高度。
根據一第二態樣，揭示一種環繞式閘極(GAA)半導體元件，其包括：一半導體基板，其包括一第一結晶半導體材料；至少一經懸置奈米結構，其等至少部分位於一對鄰近STI區域上方且位於該對STI區域之間，且該至少一經懸置奈米結構係由該至少一經懸置奈米結構之兩端處之一源極區域及一汲極區域固持於適當位置，該至少一經懸置奈米結構包括不同於該第一結晶半導體材料之一第三結晶半導體材料，其中一腔存在於該至少一經懸置奈米結構、該等STI區域之相對側壁與該半導體基板之一頂面部分之間，該頂面部分在該STI區域對之間延伸，其中該經懸置奈米結構係由一最終閘極堆疊包覆且其中該等STI區域之該頂面及該等側壁及來自該腔之該半導體基板之曝露表面亦由該最終閘極堆疊覆蓋。
較佳地，該第一結晶半導體材料係Si且較佳地該第三結晶半導體材料包括一III-V族材料。
根據該第二態樣之實施例，該至少一奈米結構包含具有實質上等於該腔之寬度之一寬度之僅一經懸置奈米結構。
根據該第二態樣之實施例，該至少一奈米結構由具有一錐形刻面之一經懸置奈米結構組成。
根據該第二態樣之實施例，該至少一奈米結構由彼此相距一距離D之兩個經懸置奈米結構組成，其中D大於該最終閘極堆疊之厚度且小於該腔之該寬度。
根據該第二態樣之實施例，該等經懸置奈米結構具有10奈米以下之一寬度，較佳地介於2奈米與10奈米之間。
本發明之實施例之一優點係可使用一全晶圓方法(即，使用至少300奈米(亦稱為「12英寸」)晶圓大小之晶圓)來製造III-V族Si上GAA元件。
本發明之實施例之一優點係可在不使用昂貴及且小的III-V族晶圓及/或不使用昂貴且厚的基於應變鬆弛緩衝層(SRB)之基板之情況下將III-V族材料整合於Si上。因此，本發明之實施例之一優點係形成III-V族GAA半導體元件之方法相較於熟習此項技術者已知之方法較不昂貴。
本發明之實施例之一優點係III-V族半導體元件藉由基板偏壓可具有一較佳靜電控制及Vt控制。
本發明之實施例之一優點係可形成極窄奈米結構(即，小於10奈米)而無需蝕刻。
100‧‧‧半導體基板
101‧‧‧淺溝渠隔離(STI)區域
103‧‧‧凹槽
104‧‧‧第二結晶半導體材料/半導體鰭/線
104a‧‧‧第二結晶半導體材料
105‧‧‧奈米結構
105a‧‧‧奈米結構
105b‧‧‧奈米結構
106‧‧‧間隙
107‧‧‧虛設閘極
108‧‧‧間隔件
110‧‧‧凹面/淺溝渠隔離(STI)區域
111‧‧‧STI頂面/刻面
112‧‧‧STI側壁
114‧‧‧空的溝渠/腔/空的空間
116‧‧‧頂面
117‧‧‧頂面
119‧‧‧鎢閘極填充
120‧‧‧介電層/介電材料/夾層介電(ILD)層
121‧‧‧源極區域
122‧‧‧汲極區域
D‧‧‧距離
H‧‧‧高度
L‧‧‧長度
W‧‧‧寬度
將經由以下描述及附圖進一步闡述本發明。
圖1至圖6示意地繪示來自根據本發明之實施例之包括一奈米結構之一環繞式閘極半導體元件之一製造方法之不同步驟。
圖7至圖10及圖14示意地繪示來自根據本發明之實施例之包括兩個奈米結構之一環繞式閘極半導體元件之一製造方法之不同步驟。
圖11至圖13及圖16示意地繪示來自根據本發明之實施例之包括至少一奈米結構之一環繞式閘極半導體元件之一製造方法之不同步驟。
圖15示意地繪示在執行來自根據本發明之實施例之包括至少一奈米結構之一環繞式閘極半導體元件之一製造方法之一些步驟之後之一環繞式閘極半導體元件之一俯視圖。
圖17及圖29示意地繪示根據本發明之實施例之包括一奈米結構之一環繞式閘極半導體元件。
圖18示意地繪示根據本發明之實施例之包括兩個奈米結構之一 環繞式閘極半導體元件。
圖19及圖20展示根據本發明之實施例之包括一奈米結構之一環繞式閘極半導體元件之一二次電子顯微鏡(SEM)影像。
圖21至25展示關於根據本發明之實施例之包括至少一奈米結構之一環繞式閘極半導體元件之元件特性之實驗結果。
圖26示意地繪示來自根據本發明之實施例之包括至少一奈米結構之一環繞式閘極半導體元件之一製造方法之不同程序步驟。
圖27展示根據本發明之實施例之包括兩個奈米結構之一環繞式閘極半導體元件之一二次電子顯微鏡(SEM)影像。
圖28展示關於根據本發明之實施例之包括兩個奈米結構之一環繞式閘極半導體元件之元件特性之實驗結果。
圖30展示關於根據本發明之實施例之一環繞式閘極半導體元件之元件特性之模擬結果。
該等圖式係僅示意性的且非限制性的。在該等圖式中，可誇大一些元件之大小且為闡釋性目的而不按比例繪製。該等尺寸及相對尺寸並不對應於本發明之實踐之實際減小程度。
在該等技術方案中之任何參考符號不應理解為限制範疇。
在不同圖式中，相同參考符號係指相同或類似元件。
將經由揭示內容之若干實施例之以下詳細描述及隨附圖式來進一步闡明本發明。
在以下詳細描述中，闡述數個特定細節以提供所揭示內容之一徹底理解及如何以特定實施例來實踐所揭示內容。然而，將瞭解所揭示內容可在無此等特定細節的情況下實踐。在其他例項中，未詳細描述眾所周知的方法、程序，及技術，以不混淆所揭示內容。儘管將參考特定實施例及參考特定圖式描述所揭示內容，但所揭示內容並不限 於此。本文中所包含及描述之圖式係示意性且並不限制所揭示內容之範疇。亦應注意，在該等圖式中，可誇大一些元件之大小，且因此為繪示性目的而不按比例繪製。
在申請專利範圍中使用之術語「包括」不應解釋為限制於此後所列出之含義；其並不排除其他元件或步驟。需要解釋為指定存在如所指之經陳述特徵、整數、步驟或組件，但不排除存在或增加一或多個其他特徵、整數、步驟或組件或其等之群組。因此，「一裝置包括構件A及B」所表達之範疇不應限於裝置僅由組件A及B組成。
III-V族材料作為用於先進縮放節點之一潛在高遷移率通道材料已吸引許多關注。然而，歸因於低效狀態質量及密度(DOS)，基於InGaAs之通道元件經預期比Si將經受更差短通道效應(SCE)。此使得極關注針對III-V族的環繞式閘極架構，這是因為環繞式閘極架構對平面或鰭式場效電晶體元件提供增加之靜電控制，且經製造於小InP基板上之InGaAs GAA電晶體顯示前景可期。
每當稱作一奈米結構時，此可被視為其中具有小於20奈米(宜小於10奈米)之一高度及/或寬度之一橫截面之一結構。一奈米結構之一實例可為一長形奈米結構，諸如一奈米線。
參考圖1，提供包括一第一結晶半導體材料之一半導體基板100。基板100可為一塊狀矽(Si)晶圓、一塊狀鍺(Ge)晶圓、一絕緣體上半導體(SOI)基板(諸如(例如)Si-O-I或Ge-O-I基板)或甚至一經應變的絕緣體上半導體(SSOI)基板。半導體基板100包括一第一結晶半導體材料或由一第一結晶半導體材料組成。該第一結晶半導體材料係選自一IV族元素(諸如Si或Ge)。
參考圖2，淺溝渠隔離(STI)區域101係形成於半導體基板100中。可藉由蝕刻溝渠且以一絕緣材料(諸如(例如)氧化物(SiO2))填充該等溝渠來形成STI區域101。STI區域101界定將被形成於隨後(相鄰)STI區 域101之間的主動區域。
STI區域101可介於100奈米深與500奈米深之間，且可具有自500奈米直至20奈米之範圍內之一寬度。對於更先進的STI模組，STI區域之深度可甚至低於100奈米，且STI區域之寬度可直至5奈米。根據經驗法則，STI區域之縱橫比(其係深度與寬度之間的比率)應至少為2。
參考圖3至圖5，在形成STI區域101之後，形成半導體鰭或線104。參考圖3，移除STI區域101之間之半導體基板100之部分第一結晶半導體材料。藉此在STI區域101之間產生具有一凹面110之凹槽103。根據用於移除該第一結晶半導體材料之蝕刻化學性質，凹面110可具有一不同形狀。宜使用對第一結晶半導體材料具有一選擇性之一各向異性蝕刻化學性質，且因此不蝕刻STI區域101之絕緣材料。可藉由濕式蝕刻或乾式蝕刻來完成該凹陷蝕刻。宜使用濕式蝕刻。濕式蝕刻之一實例係TMAH蝕刻或HCI蒸汽蝕刻。乾式蝕刻之一實例係SF6。參考圖4，一第二結晶半導體材料104經提供於凹槽103中之STI區域101之間之該第一結晶半導體材料上。該第二結晶材料104與該第一結晶半導體材料晶格失配。第二結晶材料104宜係一高能帶隙材料。該高能帶隙材料宜係一III-V族材料，諸如(例如)InP、AlAs、GaAs、GaP、InAs、GaSb、AlSb或其類似物或其等之一組合(諸如由其等製成之三元化合物(例如InGaAs、InGaP))。第二結晶半導體材料104自STI區域101之間之凹面110開始磊晶生長於第一結晶半導體材料100上。第二結晶半導體材料104亦可生長於STI區域101之頂面111上方104a。可使用化學機械拋光(CMP)來平坦化第二結晶半導體材料104a之過度生長。在CMP之後，包括第二結晶半導體材料104之半導體鰭及STI區域101鄰接於一共同平坦頂面111上(圖5)。
該等鰭可為具有一寬度、一長度及一高度之長方體結構，其中該寬度及該長度平行於該基板且該高度垂直於該基板。該寬度沿著該 鰭之該高度保持相等。所以在該鰭之頂部及底部或基部處之寬度係相等。該鰭之基部之底部係該鰭最接近基板之部分。該鰭之頂部係在該鰭之底部之相對側處。
可錐形化該等鰭(如圖式中所展示)。該鰭之頂部處之一寬度略短於該鰭之底部或基部處之寬度。
此等半導體鰭或線104具有等於STI區域101之高度H之一高度及自100奈米變化直至20奈米或甚至直至5奈米之一寬度W。根據經驗法則，該等鰭之縱橫比(其係深度與寬度之間之比率)應至少為2。半導體鰭或線104係長形的且位於與共同平坦頂面相同之一平面中(圖15)。該等半導體鰭或線之長度L可為若干奈米，較佳地遠大於(例如10倍大於)鰭之寬度。
其中半導體鰭或線介於STI區域之間且由該等STI區域隔離之結構通常亦稱為一STI模板結構。
參考圖6及圖7，一第三結晶半導體材料之至少一奈米結構105、105a、105b係提供於半導體鰭104之第二結晶半導體材料上。諸如圖6中，一奈米結構105可提供於半導體鰭104上，或兩個奈米結構105a、105b可提供於半導體鰭104上。如圖8中所展示，其繪示圖7中所展示之一鰭104之頂部部分之一放大部分視圖，兩個奈米結構105a、105b彼此分離一距離D。距離D大於0奈米且小於半導體鰭之寬度，更佳地，小於半導體鰭之寬度之一半。該至少一奈米結構105、105a、105b之第三結晶半導體材料包括一高能帶隙材料，較佳地一III-V族材料InP、AlAs、GaAs、GaP、InAs、GaSb、AlSb或其類似物或其等之一組合(諸如由其等製成之三元化合物(例如InGaAs、InGaP))，然而，該第三結晶半導體材料不同於第二結晶半導體材料。
該至少一奈米結構係一橫向奈米結構，即，與基板頂面或與STI頂面位於相同平面之一奈米結構。此與可在半導體基板表面上垂直延 伸之一垂直奈米結構形成對比。
而提供一奈米結構(圖6)，此可藉由在半導體鰭104之第二結晶半導體材料上磊晶生長第三結晶半導體材料來完成。因此，第三結晶半導體材料係生長於STI區域101之間之第二結晶半導體材料上之共同頂面111上方。根據生長條件，奈米結構105之形狀可改變。該奈米結構可具有類似於一錐體形狀之一<111>刻面。
而提供兩個奈米結構(圖7、圖8)，此可使用以下製造步驟來完成(參考圖9、圖10)。在提供半導體鰭(包括第二結晶半導體材料)之後，執行一熱處理且因此該半導體鰭(包括第二結晶半導體材料)經受一熱處理步驟。較佳地，該熱處理步驟在500攝氏度與600攝氏度之間之一溫度下。該熱處理步驟可為(例如)處於使用包括氫氣H2之一載氣中之TBA或TBP之一環境中達1至5分鐘。該熱處理可為一預烘乾步驟且可導致第二結晶半導體材料之一回流或第二結晶半導體材料之一熱蝕刻。歸因於第二結晶半導體材料之回流，在STI側壁112與第二結晶半導體材料之現經刻削之頂面116之間產生一間隙106(圖9)。較佳地，半導體鰭之第二結晶半導體材料之頂面117之中間部分將升高於STI頂面111上方。因此，間隙106彼此相距一距離D。距離D大於0奈米且小於半導體鰭之寬度，最好小於半導體鰭之寬度之一半。
在預熱處理(熱處理)步驟之後，以第三結晶半導體材料至少部分填充間隙106(圖10)。間隙106可被完全填充。第三結晶半導體材料宜磊晶生長於第二結晶半導體材料上，藉此此生長將自第二結晶半導體材料之(經回流)經刻削頂面開始。第三結晶半導體材料將生長於間隙106中但亦可生長於第二結晶半導體材料之頂面117上方。可藉由一CMP步驟移除過度生長之第三結晶半導體材料，藉此導致包括彼此相距一距離D之第三結晶半導體材料之兩個奈米結構之一結構，如圖8中示意性展示。必須進行該CMP步驟至少一直到頂面117為止，但亦 可繼續該CMP步驟直至到達低於頂面117之初始高度之一高度為止。
若兩個奈米結構之間的距離D小於閘極堆疊層的厚度，則兩個奈米結構將合併。
若第二結晶半導體材料之頂面117並未延伸至STI頂面111上方，則為確保奈米結構將被懸置的不同可能性係可行的。一可能性係執行一CMP步驟至僅低於頂面117，藉此在兩個奈米結構之間產生一中斷。另一可能性係在熱處理步驟之前執行一部分STI氧化物蝕刻，使得降低STI頂面111。在熱處理之後，第二半導體材料之頂面117將在經降低之STI頂面111上方。藉由使用一CMP步驟來移除部分第三半導體材料(其選擇性地停止於STI氧化物上)，可使兩個奈米結構懸置。
參考圖11，一虛設閘極107經提供於至少一奈米結構105上，及一源極/汲極區域經形成於該虛設閘極旁之至少一奈米結構上。
圖15展示在已提供虛設閘極之後之半導體元件之一俯視圖或一平面圖。圖中展示至少一奈米結構(左105)(右105a、105b)之不同實施例。一虛設閘極107經提供於至少一奈米結構105之頂部。亦提供一介電層120。圖1至圖10係指沿著A-A'橫截面之側視圖，而圖11至圖12係指沿著B-B'橫截面之側視圖。可使用此項技術者已知之技術，藉由在至少一奈米結構上提供一閘極層且圖案化此閘極層以形成一虛設閘極107來提供一虛設閘極107。間隔件108經處理或經提供於虛設閘極107之側表面處。在形成虛設閘極及間隔件之後，可提供源極區域121及汲極區域122。此可(例如)藉由在至少一奈米結構上磊晶生長一第四半導體材料來完成。為使虛設閘極與源極/汲極區域隔離，在該結構上提供一介電材料120(夾層介電ILD)。
在提供虛設閘極107、間隔件108及源極/汲極區域121、122之後，移除虛設閘極107(圖12)。可藉由蝕刻來完成虛設閘極107之移除。藉由移除該虛設閘極，顯露至少一奈米結構之中間部分，而使該 至少一奈米結構之外部分連接至/接觸源極及汲極區域121、122。
因此，奈米結構係未由STI區域懸置，而是由源極/汲極區域懸置且亦可由ILD層120懸置。藉此，ILD層120包住源極/汲極區域。
在移除虛設閘極107之後，移除第二結晶半導體材料104，藉此使至少一奈米結構懸置(圖13、圖14)。因此，至少一奈米結構105、105a、105b被懸置於一空的溝渠114上方，且藉由源極及汲極區域121、122將至少一奈米結構105、105a、105b固持於適當位置。可藉由蝕刻來完成第二結晶半導體材料之移除。宜使用對第三半導體材料具選擇性之一蝕刻化學性質，例如，可使用對InGaAs通道(奈米結構)具高度選擇性之HCI來蝕刻InP緩衝層。圖13展示沿著線B-B'之一橫截面及圖14展示在移除第二結晶半導體材料104之後沿著線A-A'之一橫截面圖。因此，在至少一奈米結構105下方產生一腔或空的空間114。
藉由移除在第三結晶半導體材料下方之第二結晶半導體材料105來消除主漏電路徑。此外，可藉由曝露該奈米結構來製造一GAA元件。
在移除第二結晶半導體材料104且藉此使至少一奈米結構懸置之後，可提供一最終閘極堆疊，該閘極堆疊將圍繞該至少一奈米結構覆蓋或圍繞各奈米結構之一部分在不同周向上延伸。提供該最終閘極堆疊包括在至少一奈米結構上或圍繞至少一奈米結構提供一閘極介電層及一最終閘極電極層。參考圖16(沿著B-B'橫截面之一側視圖)、圖17(各鰭104上兩個奈米結構)及圖18(各鰭104上一個奈米結構)(沿著A-A'橫截面之一側視圖)，展示最終閘極堆疊117。宜使用一沈積技術(諸如原子層沈積(ALD))來提供該最終閘極堆疊，使得層保形地提供於不同元件組件上。自圖16及圖17可見，最終閘極堆疊係形成於腔114中之STI區域110之所曝露側壁處，圍繞至少一奈米結構105、105a、105b，在間隔件108之側壁處及在介電層120之頂面處。
在提供最終閘極堆疊117之後，可用包括鎢閘極填充119及CMP、接觸件形成及進一步後段製程(BEOL)處理之金屬化步驟來完成元件(參見圖20)。
實驗結果
已根據本發明之實施例製造InGaAs GAA及橫向奈米線元件。替代鰭程序已用於300毫米Si基板。對於60奈米之一閘極長度(LG)，在0.5V之一汲極/源極電壓(Vds)處達成1030μS/μm之一非本質跨導(gm)，此相較於替代鰭鰭式場效電晶體程序增加近2倍。此增加係歸因於消除GAA流程中之Mg逆摻雜。具有6nm之直徑之奈米線經演示而展示由量子化引發之對導致85nm LG元件之65mV/dec之一飽和亞臨限值斜率(SSSAT)之介面陷阱密度(Dit)之免疫性。
GAA元件製造及元件結果
製造一InGaAs GAA元件之程序流程包括以下概括順序：
- InGaAs鰭形成
- 虛設閘極圖案化
- 間隔件處理
- 摻雜Si之InAs S/D沈積
- ILD0沈積及CMP
- 虛設閘極移除
- InP緩衝層移除
- 高k及金屬閘極沈積
- 鎢閘極填充及CMP
- 接觸件及金屬1
首先，使用一替代鰭方法形成InGaAs鰭直至300毫米Si基板上之替代金屬閘極(RMG)模組。在移除虛設閘極之後，僅顯露直接在閘極線之下之部分鰭(圖12)。圖12及圖7中分別展示在移除InP之前沿著(B- B')及跨(A-A')之一橫截面，及圖14及圖13中分別展示在移除InP之後溝渠沿著(B-B')及跨(A-A')之一橫截面。
對於替代鰭方法，金屬有機氣相磊晶(MOVPE)係用於III-V族生長以與高產出量處理相容。然而，固有地存在於金屬有機前驅體(TBP、TBAs、TMIn及TMGa)中之碳引起InP及InGaAs層之非故意n-型摻雜。為抵消此背景摻雜，開發一種p-型Mg摻雜解決方案。當Mg摻雜有效地抑制關斷狀態之源極汲極洩漏電流時，在Mg摻雜位準與通道遷移率之間建立一折衷。最終，摻雜引發之遷移率減少限制可達成之元件效能。由此觀點，一GAA架構對InP/InGaAs系統極具吸引力。藉由自InGaAs通道下方移除n-型InP緩衝層來消除主漏電路徑而無需付出遷移率減少之代價。
STI鰭凹槽係足夠深以曝露InP緩衝層及HCl：H2O係用以相對於InGaAs通道選擇性地蝕刻InP。此導致一InGaAs通道層被懸置於現空的溝渠上方且由N+ InAs源極/汲極(SD)層(其由層間介電(ILD)堆疊包住)固持於適當位置(圖19、圖20)。藉由ALD來沈積2奈米Al2O3/2奈米HfO2/3奈米TiN之高k閘極堆疊。高k閘極堆疊具有1.5奈米之一等效氧化物厚度(EOT)。接著，藉由鎢閘極填充及CMP及接著進行標準鎢插塞接觸件及金屬1(M1)模組來完成處理。圖20中展示一完成的95奈米寬GAA InGaAs元件之一TEM，其可與圖18中之示意呈現相比較。此處清晰可見InP緩衝層已被完全移除且通道包括由閘極堆疊圍繞包覆之一InGaAs塊。圖21A中展示具有95奈米之一通道寬度及30奈米之一最大厚度之一60奈米LG元件在不同閘極電壓(0.2V下線以0.2V為步級至1V上線)下之I-V特性。歸因於InGaAs沈積之預烘乾步驟期間InP之回流，該InGaAs形狀係圓形。在Vds=0.5V處以125mV/dec之一SS達成1030之一峰值非本質gm(圖21B)。圖22至圖24中展示SCE依據通道寬度及閘極長度而變。圖22展示飽和亞臨限值斜率(SSat)依據閘極長度 Lg及寬度W而變。圖23展示飽和臨限值電壓(VTsat)依據閘極長度Lg及寬度W而變。VT經界定在一汲極電流Id處等於1μA/μm。圖24展示汲極引發之障壁降低DIBL依據閘極長度Lg及寬度W而變。在圖22、圖23及圖24中，寬度W自55奈米(矩形)變化至75奈米(圓形)至95奈米(三角形)。隨著LG自長通道縮放至短通道，觀察到臨限值電壓(VT)下降(roll-off)及SS及DIBL之降級。通道寬度相對於通道厚度(15-27奈米)太大而不能具有一大影響。期望寬度之更主動縮放及EOT將產生進一步改良。在125奈米之一閘極長度及55奈米之一相同鰭寬度處，將GAA元件(矩形)之效能與在圖25A至25D中之鰭式場效電晶體(圓形)元件之效能進行比較。儘管未採用通道之逆摻雜，但GAA架構之增加的靜電控制導致一較低關斷狀態漏電。如所預期，亦顯著改良SSSAT及DIBL兩者。以GAA流程獲得之gm接近2x之提高指示通道歸因於缺少Mg逆摻雜而改良之傳導性質。
圖26中展示根據本發明之實施例之鰭程序之一修改。圖中展示一雙重奈米線通道及用於製造此雙通奈米線之程序步驟。在形成一淺的填充InP之凹槽104之後(a)，在InGaAs沈積之前之一預烘乾導致InP緩衝層104之一回流(及圓化)(b)。隨後以InGaAs 105填充STI 101側壁與現經刻削之InP 104之間產生之間隙(c)。在InGaAs 105之一CMP程序之後(d)，STI 101凹陷及InP 104經蝕刻(e)以顯露被懸置的奈米線105a、105b。若在通道CMP步驟之後InP凹槽足夠淺，則將僅保持InGaAs之此等兩個小區域(e)，接著在移除InP之後該兩個區域將變為被懸置的奈米線(圖26)。此程序係用於產生具有僅6奈米之直徑之線。在使奈米線懸置之後，如圖29中所展示般提供一閘極堆疊(其係一個奈米結構之一實例且可與圖16及圖18中之示意圖相比較)。圍繞該InGaAs奈米結構且在STI側壁上之間隙中提供一高k/TiN閘極堆疊。圖27中展示根據本發明之一方法製造之一雙重奈米線之一SEM影像。 一4奈米及6.5奈米寬InGaAs奈米線經製造以由一TiN/HfO2/Al2O3閘極堆疊包圍。明顯地，相較於較厚GAA元件之典型值120mV/dec及100-120mV/V，可使短通道元件之SSSAT減少至具有可忽略的DIBL之低為65mV/dec之值(圖28)。此改良歸因於一量子化引發之對Dit之免疫性。然而，量子化亦增加高k層中之邊緣陷阱，突顯通道與高k堆疊之間對一寬帶隙夾層之需要。表面狀態陷阱對超大(ultra-scaled)GAA結構之SS應具有一可忽略的影響且此相較於較大塊狀元件已連結至小奈米線之更優閘極控制。為探究帶結構對SS之效應，吾人使用一8k.p帶解算器來研究量子化效應對介面陷阱之熱電子發射率(en)。該等模擬展示高度受限結構之低DOS相較於具有鬆弛尺寸之線之DOS有效地限制陷阱之發射率(圖30)。此較低en與更佳的閘極控制組合可導致抑制奈米線元件中Dit引發之降級。亦減小奈米線元件之ISAT，此可由較低DOS、增加之聲子散射及與增加之侷限相關聯之有效質量預期。量子化亦導致子頻帶能量位準之增加，潛在地容許高k層中更深處通道電荷與陷阱之一更大相互作用。需要進一步研究來判定閘極堆疊中之陷阱分佈曲線之最佳化是否可增強效能。

Claims (15)

  1. 一種用於製造一環繞式閘極(GAA)半導體元件之方法，該方法包括：提供一第一結晶半導體材料之一半導體基板；在該半導體基板中形成淺溝渠隔離(STI)區域；在該半導體基板上形成複數個半導體鰭；該複數個半導體鰭包括一第二結晶半導體材料，該第二結晶半導體材料與該第一結晶半導體材料晶格失配，該複數個半導體鰭之各者經形成於STI區域對之間，其中該複數個半導體鰭係藉由該等STI區域彼此隔離；在該複數個半導體鰭之各者之該第二結晶半導體材料上，提供一第三結晶半導體材料之至少一奈米結構；在該至少一奈米結構上，提供一虛設閘極；在該至少一奈米結構上，提供一源極及一汲極區域於該虛設閘極之兩側處；移除該虛設閘極及其後移除該第二結晶半導體材料，藉此使由該源極及汲極區域錨固之該至少一奈米結構懸置；在移除該第二結晶半導體材料之後，圍繞該至少一奈米結構提供一最終閘極堆疊。
  2. 如請求項1之用於製造一環繞式閘極(GAA)半導體元件之方法，其中在該第二結晶半導體材料上提供該至少一奈米結構包含在該複數個半導體鰭之各者上提供僅一奈米結構。
  3. 如請求項2之用於製造一環繞式閘極(GAA)半導體元件之方法，其中提供僅一奈米結構包括在該複數個半導體鰭之各者上磊晶生長該第三結晶半導體材料。
  4. 如請求項2之用於製造一環繞式閘極(GAA)半導體元件之方法，其中該僅一奈米結構具有一錐形刻面。
  5. 如請求項1之用於製造一環繞式閘極(GAA)半導體元件之方法，其中在該第二結晶半導體材料上提供該至少一奈米結構包含在該複數個半導體鰭之各者上提供兩個奈米結構。
  6. 如請求項5之用於製造一環繞式閘極(GAA)半導體元件之方法，其中在該複數個半導體鰭之一鰭上提供兩個奈米結構包括：自各鰭之一頂面，在該半導體鰭與該半導體鰭之相對側上之STI區域之間之介面處之該第二結晶半導體材料中，提供兩個分離的間隙；在該第二結晶半導體材料上之該等間隙中，磊晶生長一第三結晶半導體材料；平坦化該第三結晶半導體材料。
  7. 如請求項5或6之任一項之用於製造一環繞式閘極(GAA)半導體元件之方法，其中提供該等間隙包括執行該第二結晶半導體材料之一熱處理。
  8. 如請求項5或6之任一項之用於製造一環繞式閘極(GAA)半導體元件之方法，其中各半導體鰭上之該兩個奈米結構彼此相距一距離D，其中D大於該最終閘極堆疊之一厚度且小於該半導體鰭之一寬度。
  9. 如請求項1至6之任一項之用於製造一環繞式閘極(GAA)半導體元件之方法，其中該第二結晶半導體材料包括一III-V族材料。
  10. 如請求項9之任一項之用於製造一環繞式閘極(GAA)半導體元件之方法，其中該第三結晶半導體材料包括不同於該第二結晶半導體材料之該III-V族材料之另一III-V族材料。
  11. 如請求項1至6之任一項之用於製造一環繞式閘極(GAA)半導體元 件之方法，進一步包括：在移除該第二結晶半導體材料之前，蝕刻該等STI區域之一頂部部分，使得該等STI區域之一各自頂面之一高度變得低於該等半導體鰭之一各自頂面之一高度。
  12. 一種環繞式閘極(GAA)半導體元件，其包括：一半導體基板，該半導體基板包括一第一結晶半導體材料；至少一經懸置奈米結構，其等至少部分係位於一對鄰近STI區域上方且係位於該對STI區域之間，且該至少一經懸置奈米結構係由該至少一懸置奈米結構之兩端處之一源極區域及一汲極區域固持於適當位置，該至少一經懸置奈米結構包括不同於該第一結晶半導體材料之一第三結晶半導體材料，其中一腔存在於該至少一經懸置奈米結構、該等STI區域之相對側壁與該半導體基板之間，其中該經懸置奈米結構係由一最終閘極堆疊包覆，且其中該等STI區域之頂面及該等側壁及來自該腔之該半導體基板之曝露表面亦由該最終閘極堆疊覆蓋。
  13. 如請求項12之環繞式閘極(GAA)半導體元件，其中該至少一奈米結構包含具有實質上等於該腔之寬度之一寬度之僅一經懸置奈米結構。
  14. 如請求項12之環繞式閘極(GAA)半導體元件，其中該至少一奈米結構包含彼此相距一距離D之兩個經懸置奈米結構，其中D大於該最終閘極堆疊之厚度且小於該腔之該寬度。
  15. 如請求項12至14之任一項之環繞式閘極(GAA)半導體元件，其中該第一結晶半導體材料係Si，且其中該第三結晶半導體材料包括一III-V族材料。
TW104109930A 2014-03-27 2015-03-27 Iii-v族環繞式閘極半導體元件及其製造方法 TWI642181B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP14162027 2014-03-27
??14162027.8 2014-03-27

Publications (2)

Publication Number Publication Date
TW201601308A TW201601308A (zh) 2016-01-01
TWI642181B true TWI642181B (zh) 2018-11-21

Family

ID=50382344

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104109930A TWI642181B (zh) 2014-03-27 2015-03-27 Iii-v族環繞式閘極半導體元件及其製造方法

Country Status (3)

Country Link
US (2) US9324818B2 (zh)
EP (2) EP3185302B1 (zh)
TW (1) TWI642181B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9530776B2 (en) * 2014-01-17 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET semiconductor device with germanium diffusion over silicon fins
US9590032B2 (en) * 2014-12-12 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-FET device and manufacturing method thereof
EP3238264A4 (en) * 2014-12-23 2018-08-22 Intel Corporation Apparatus and methods of forming fin structures with sidewall liner
US9754968B2 (en) 2015-04-30 2017-09-05 International Business Machines Corporation Structure and method to form III-V, Ge and SiGe fins on insulator
EP3314660A4 (en) * 2015-06-23 2019-01-23 Intel Corporation INDUSTRIAL NMOS TRANSISTOR CHANNELS
WO2017111958A1 (en) * 2015-12-22 2017-06-29 Intel Corporation Transistors having ultra thin fin profiles and their methods of fabrication
CN108369958A (zh) * 2015-12-24 2018-08-03 英特尔公司 包括拉伸应变的锗沟道的晶体管
WO2017111873A1 (en) * 2015-12-26 2017-06-29 Intel Corporation A method to achieve a uniform group iv material layer in an aspect ratio trapping trench
DE112016006574T5 (de) * 2016-03-11 2018-11-29 Intel Corporation Techniken zum ausbilden von transistoren, die gruppe-iii-v-material-nanodrähte aufweisen, welche gruppe-iv-materialopfreschichten verwenden
WO2017171875A1 (en) * 2016-04-01 2017-10-05 Intel Corporation An indium-containing fin of a transistor device with an indium-rich core
US9870948B2 (en) * 2016-06-09 2018-01-16 International Business Machines Corporation Forming insulator fin structure in isolation region to support gate structures
TWI622171B (zh) 2016-06-24 2018-04-21 財團法人國家實驗研究院 異質整合半導體裝置及其製造方法
EP3312885A1 (en) * 2016-10-18 2018-04-25 IMEC vzw Method for forming nanowires from strained layers on surfaces of a fin
US10290768B2 (en) 2017-09-14 2019-05-14 Globalfoundries Inc. Nanowire formation methods
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures
DE102020114813A1 (de) 2019-10-31 2021-05-06 Taiwan Semiconductor Manufacturing Co., Ltd. Struktur und bildungsverfahren für halbleitervorrichtung mit isolierungsstruktur
US11424242B2 (en) 2019-10-31 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with isolation structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130001591A1 (en) * 2011-06-30 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Finfet design and method of fabricating same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006125826A1 (en) * 2005-05-27 2006-11-30 The Provost Fellows And Scholars Of The College Of The Holy And Undivided Trinity Of Queen Elizabeth Near Dublin Electrically conducting nanowires
JP5413782B2 (ja) 2008-06-09 2014-02-12 独立行政法人産業技術総合研究所 ナノワイヤ電界効果トランジスタ及びこれを含む集積回路
US7884004B2 (en) * 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
US8422273B2 (en) 2009-05-21 2013-04-16 International Business Machines Corporation Nanowire mesh FET with multiple threshold voltages
KR101821672B1 (ko) * 2011-12-23 2018-01-24 인텔 코포레이션 비평면 게이트 올어라운드 장치 및 그의 제조 방법
US8486770B1 (en) * 2011-12-30 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming CMOS FinFET device
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8652891B1 (en) * 2012-07-25 2014-02-18 The Institute of Microelectronics Chinese Academy of Science Semiconductor device and method of manufacturing the same
US9728464B2 (en) * 2012-07-27 2017-08-08 Intel Corporation Self-aligned 3-D epitaxial structures for MOS device fabrication

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130001591A1 (en) * 2011-06-30 2013-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Finfet design and method of fabricating same

Also Published As

Publication number Publication date
US20160240532A1 (en) 2016-08-18
EP2924738A1 (en) 2015-09-30
US9601488B2 (en) 2017-03-21
EP3185302B1 (en) 2018-05-09
US9324818B2 (en) 2016-04-26
US20150279947A1 (en) 2015-10-01
EP2924738B1 (en) 2017-03-22
TW201601308A (zh) 2016-01-01
EP3185302A1 (en) 2017-06-28

Similar Documents

Publication Publication Date Title
TWI642181B (zh) Iii-v族環繞式閘極半導體元件及其製造方法
US11664456B2 (en) Semiconductor structures and methods of forming thereof
US9892912B2 (en) Method of manufacturing stacked nanowire MOS transistor
JP6301301B2 (ja) 非平面ゲルマニウム量子井戸デバイス
US9590085B2 (en) Method and structure for III-V FinFET
US9029222B2 (en) Three-dimensional quantum well transistor and fabrication method
US9917179B2 (en) Stacked nanowire devices formed using lateral aspect ratio trapping
US9472468B2 (en) Nanowire CMOS structure and formation methods
US8558219B2 (en) Nanowire field effect transistors
TWI656638B (zh) 用於ｉｉｉ－ｖ族奈米線穿隧ｆｅｔ之方法及結構
CN105405881B (zh) 半导体器件及其制造方法