WO2006125826A1

WO2006125826A1 - Electrically conducting nanowires

Info

Publication number: WO2006125826A1
Application number: PCT/EP2006/062643
Authority: WO
Inventors: Kevin Radican; Nickolai Berdunov; Igor Vasilievich Shvets; Shane Murphy
Original assignee: The Provost Fellows And Scholars Of The College Of The Holy And Undivided Trinity Of Queen Elizabeth Near Dublin
Priority date: 2005-05-27
Filing date: 2006-05-26
Publication date: 2006-11-30

Abstract

The present invention is directed to a nanowire assembly comprising a substrate (1 ) having an oxidised surface forming nanotrenches (2) with peaks (3) and troughs (4) and conducting nanowires on one of the peaks and troughs. The present invention is also directed to a process for forming this nanowire assembly and various electronic devices such as transistors comprising the nanowire assembly.

Description

"Electrically Conducting Nanowires"

Introduction

The present invention relates to a nanowire assembly and in particular to a method for preparing such a nanowire assembly. The invention further relates to electronic devices, such as transistors, comprising these nanowires.

During recent years there has been a massive increase in research effort on nanoscale conducting objects. Most commonly the attention in this area is paid to nanowires. In this specification, the term "conducting nanowire" or more simply "nanowire" is defined generally as an elongated object in which both of its orthogonal cross-sectional dimensions, thickness and width, are in the nanoscale range: e.g. 0.2-20 nm and that it is capable of transferring charge along its length. Both of the terms "nanowires" and "conducting nanowires" are used interchangeably in this specification. It is important to stress that both of the cross sectional dimensions, thickness and width must be in this range, not only one of them. Those skilled in the art wil! readily appreciate that if the definition were broader and it was suggested that only one of the two cross-sectional dimensions must be in the nanoscale range then any nanoscale-range thick film would fit the definition of a nanowire as its thickness is in this range. In practice, continuous thin films with a thickness in the nanometer and even sub-nanometer range are well known and are not the subject of the present specification. It is important to stress that the nanowires must be capable of transferring charge along their length. This means that such nanowires should be placed on substrates with relatively high resistance, i.e. the resistance of the substrate should at least be not much smaller than the resistance of the nanowire itself or alternatively the substrate must be separated from the nanowire by a layer of insulating material. If this condition is not fulfilled, then most of the current is drained from the nanowire and transferred through the substrate. In order to transfer current along the nanowire, it should be possible to connect input and output contacts to it. In practice this means that the nanowire or an array of nanowires should be positioned along a flat substrate, as making contacts to an unsupported nanowire is difficult.

The importance of conducting nanowires increases with the continuing miniaturization of electronic devices, which reduces the size of the drain and the source of the transistor to beiow 100 nm and also by the expectation that the electronic and optical properties of the material can be altered when its dimensions are reduced to the nanometer range. For example, silicon does not have visible luminescence as this is an indirect band gap material, but in contrast silicon nanowires are expected to have visible photoluminescence (J. D. Holmes, et al,

Science, 287 (2000) 1471), which could open up the prospect of using these for making lasers.

There are many approaches to fabrication of nanowires, some of which are described below.

H. Hamatsu et al (Jpn. J. Appi. Phys. VoI 35 (1996) L1 148-1150) described a method for forming silicon nanowires based on anisotropic etching of a Si layer deposited on top of a p-type (1 10) SIMOX substrate. Another lithographic process for fabricating nanowires of Si with a dimension down to 50 nm is described by M. Macucci et al (Microelectronic Engineering 61-62 (2002) 701-705). It is based on anisotropic etching and steam thermal oxidation. Another method utilizing pyrolysis of silane within hexagonal close packed nanochannel alumina templates is described by Xin-Yi Zhang et al (Advanced Materials, 13 (2001 ) 1238-1241 ). This method produces a brush-like array of nanowires growing perpendicular to the substrate surface. Yet, another method for forming silicon nanowires by chemical vapor deposition on alumina membrane is described by M. Lu et al (Chem. Phys. Lett. 374 (2003) 542). Wen-Sheng Shi et al (Adv. Mater 12 (2000) 1343-1345) described another method of forming silicon nanowires by evaporation of silicon monoxide on flat silicon substrates. The nanowires obtained in this way are relatively long, up to 2 mm in length. Another method of forming silicon nanowires is described by Junjie Niu et al (Chem. Phys. Lett 367 (2003) 528). In this latter method they used chemical vapor deposition of Si from silane in the presence of argon and hydrogen on anodically oxidized aluminium that forms a nanochannel tempiate.

FJ. Himpsei et ai describe another method of forming nanowires on silicon surfaces (Solid State Comm. 117 (2001) 149-157.). Their method utilizes a vicinal substrate of Si(1 11 ). They deposit CaF2 on the surface that decorates the step edges of the substrate. They demonstrated that a thin layer of Au can then be formed on such a substrate in which the stripes of CaF2 are used as a template leading to the formation of nanodots and nanowires of Au.

Another family of methods for fabrication of nanowires is based on deposition at a glancing angle. E. Olson et. al. (Appl. Phys. Lett. 65 (1994) 2740-2742) described a method in which a pattern of groves is formed on a substrate by lithography. Then a flux of evaporated material is deposited on the substrate not along the direction normal to it, but rather at an angle. In this case, some of the areas at the bottom of the groves are shadowed from the flux by the walls of the groves, thus forming wires of the evaporated material separated by the areas free from it.

It should be pointed out that deposition of films at a glancing angle with respect to the substrate surface is relatively well known and there are many publications on the topic. For information on this technique, reference is made to Aiouach and C.G.Mankey, J.Mater. Res. 19 (2004) 3620. it has been demonstrated that this technique can be used to form pillars of the deposit material which grow out of the plane of the substrate. Most of the publications on glancing angle deposition deal with relatively thick films and focus on the development of the out-of-plane film structure on the scale of tens and hundreds of nanometers or greater.

The method of forming nanowires described by T. Mueller et. al. (Nuci. Instr. And Methods in Physics Research B 175-177 (2001 ) 468-473) can be also considered as a member of the family of glancing-deposition-based methods. In this method, an array of V-grooves is formed on a Si(001 ) surface by anisotropic etching and subsequent oxidation of the surface. Then the surface is subjected to a flux of Ge atoms. The highest concentration of Ge atoms is formed at the bottom of the grooves because the bottom of the grooves acts as a small area located perpendicular to the flux whereas the walls of the grooves are positioned at an angle with respect to the flux, in this way, Ge wires with a diameter down to 30-40 nm can be formed. A similar effect was achieved in the case of GaAs/AIGaAs grown by organometallic chemical vapor deposition on v-grooved substrates as reported by E.Kapon et al (Appi. Phys. Lett 60 (1992) 477-479). In this approach, the πanowires are formed at the bottom of the grooves due to the difference in the speed of the chemical deposition reactions at the crests and troughs of the grooves.

R. M. Penner describes a method of forming nanowires by electrodeposition (J. Phys. Chem. B 106 (2002) 3339-3353). In this method, nanowires grow along the step edges as the eiectrodeposition reaction occurs faster at the step edges compared to the flat areas of the substrate.

It is an object of the present invention to provide a technique for creating nanowires that would be substantially universal, i.e. applicable to a variety of substrates and nanowire materials. There is further need to form arrays of regular nanowires with well-defined preferential orientation as opposed to bundles of nanowires having no well-defined preferential orientation. There is further need to form nanowires on relatively insulating substrates, so that the resistance of the substrate is preferably greater and definitely not much smaller than the resistance of the nanowires themselves. There is further need to form nanowires on substrates in such a fashion that electrical contacts can be connected to them.

An object of the present invention is to provide a method for forming electrically conducting nanowires that results in nanowires positioned on a substrate in contrast to unsupported nanowires.

Yet another object is to provide nanowires that are positioned on a substrate so that they have preferential orientation along the substrate surface.

Another objective is to provide the nanowires with relatively regular separation between the nanowires.

A further object is to provide the array in which the nanowires are of relatively similar cross-sectionai dimensions, in both the width and the thickness.

Yet another object of the invention is to provide nanowires of p-type and n-type doped semiconductor materials that are suitable for making a nanowire-based fieid effect transistor.

Another objective of the present invention is to provide a technique for making nanowires so that the separation between the nanowires could be altered so that the density of the nanowires on the surface is altered.

Yet another object is to provide the technique where the cross-sectional dimensions of the of the nanowires, namely the width and the thickness, could be altered.

Statements of Invention

According to a first aspect of the invention, there is provided a nanowire assembly comprising:

a substrate having an oxidised surface forming nanotrenches with peaks and troughs; and

conducting nanowires on one of the peaks or troughs.

Preferably, the substrate is a transition metal. More preferably, the substrate is selected from one of the following group Mo, W, Pt, Pd₁ Rh, Ti, V and Nb.

Ideally, substrate has a (111 ), (100) or (1 10) orientation or another surface that makes small angle with (11 1 ), (100) or (110) planes. It is also envisaged that orientations other than (110) may be used. Indeed, vicinal substrates with (111 ) or (100) would appear to be suitable. It is envisaged that any surface with a low miscut angle could also be used.

Preferably, the substrate is Mo(110), Mo(100) or Mo(111 ). According to one embodiment of the invention, the substrate is a multilayer substrate. In some embodiments of the invention the substrate is a thin film of metaϊ deposited on an insulator materia!.

Preferably, the multilayer substrate comprises the substrate deposited on SrTiO₃ or AI₂O₃. More preferably, the multilayer substrate comprises a Mo substrate on SrTiO₃.

Preferably, the conducting nanowire comprises a dopant material which forms a dopant nanowire on one of the peaks or troughs.

Ideally, the dopant material is selected from one or more of the following As, Sb, In, Ga, Al, B or P. It is also envisaged that atoms of other elements could be used if the surface material is suitable. Alternatively, the dopant material is selected from one or more of the following Au, Cu, Ag, Pb, Si, Ge, Pt, Rh₁ Mo, W, B, C, alloys thereof and combinations thereof. Preferably, the dopant material forms p-type or n-type impurities in a semiconductor material. It also is envisaged that in accordance with the invention that dopant nanowire couid be formed of Si, Ge or Si-ge alloy which are doped or undoped. Thus, it will be understood that the dopant material within the scope of the invention also covers a doped semiconductor itself and not just the dopant impurities. It is envisaged that if undoped nanowires are used, all that would is deposited is for example Si or Ge with impurities or alternatively Si or Ge could be deposited at the same time as depositing impurities from another source.

One particularly suitable dopant material is one which would include Fe but could include impurities to form -n type and -p type junctions.

According to one embodiment of the invention, the multilayer substrate is covered by a fractional monolayer of dopant material.

According to another embodiment of the invention, the nanowire assembly further comprises an over layer of material deposited on the dopant material to allow the _ j _

diffusion of the dopant material into one or both of the substrate and the over layer. The over layer materia! can be of a conducting, semi-conducting material and could also be of an insulating material. Similarly as mentioned above the dopant nanowires may be annealed before an over layer material is deposited. The purpose of the over layer material is to serve as an initial tool to suppress the diffusion of the elements forming the dopant nanowires around the surfaces of the substrate and therefore, normally it will be deposited prior to annealing. Typically, the substrate and over layer materials are of different materials and they may be chosen so that the material of the dopant nanowires will preferentially diffuse into the material with a higher diffusion coefficient.

Preferably, the over layer is selected from one or more of the following Si, Ge, Si- Ge alloy, GaAs, InP. More preferably, the overlayer and substrate are insulators and the dopant nanowire forms the conducting nanowires.

It will be understood that the nanowire may comprise additional layers over the overlayer.

Ideally, the periodicity of the nanotrenches varies in range from approximately 1 nm to approximately 20nm. For example, the periodicity of the nanotrenches for an oxidised Mo(HO)₁ W(H O), Ti(H O), V(HO) substrate is in the range from approximately 1 nm to 10nm.

The nanowire assembly according to any of the preceding claims which is electrically or optically transmitting.

According to a second aspect of this invention, there is provided a method of forming an array of nanowires comprising:

a. oxidising a surface of a substrate, preferably at an elevated temperature, to form nanotrenches having alternate peaks and troughs;

b. directing a dopant material onto the substrate to form spaced-apart dopant nanowires, each dopant nanowire being on one of the peaks or troughs;

c. depositing an over layer to form a multilayer structure, and

d. optionally annealing the multiiayer structure to allow the diffusion of the dopant material into either of one or both of the substrate and the over layer.

According to another embodiment of this aspect of the invention, there is provided a method of forming an array of nanowires comprising:

oxidising a surface of a substrate to form nanotrenches having alternate peaks and troughs;

directing a dopant material onto the substrate to form spaced-apart dopant nanowires, each dopant nanowire being on one of the peaks or troughs; and

annealing the dopant material.

In this embodiment, the dopant material is preferably a doped semiconductor material.

It will be understood that all the definitions, e.g. the substrate, overlayer and dopant material, from the first aspect of the invention are applicable to this aspect of the invention.

Thus, preferably the substrate is transition metal, more preferably selected from one of the following group Mo, W, Pt, Pd, Rh, Ti, V and Nb. The substrate may have a (111 ), (100) or (110) orientation or another surface that makes small angle with (1 11 ), (100) or (110) planes, preferably Mo(HO), Mo(IOO) or Mo(111 ).

Alternatively or additionally, the substrate may be a multilayer substrate. Preferably, the substrate is deposited on SrTiO₃ or AI₂O₃ to form a multilayer substrate, preferably a Mo substrate on SrTiO₃.

The multilayer substrate may covered by a fractional layer of dopant material.

The multilayer substrate may also be oxidised at an elevated temperature to form a templated oxide layer and a semiconductor layer, preferably chosen from one of the following Si, Ge, GaAs, InP or Si-Ge ailoy, may be subsequently deposited over templated oxide layer. Preferably, the oxidised substrate is a film of molybdenum oxide

Preferably, the over layer material is a conducting, semiconducting or an insulating material, preferably selected from one or more of Si, Ge, Si-Ge alloy, GaAs and/or InP. Ideally, the over layer material is a different material to that of the substrate.

Preferably, the material of the dopant nanowires preferentially diffuses into the substrate or over layer which has the higher diffusion coefficient.

According to another emdodiment of this invention, the method comprises a further step of exposing the conducting nanowires by removing the overlayer that is not doped or the semiconductor material that is not doped.

It will be understood that the periodicity of the nanotrenches is controlled by the treatment process. Specifically, the temperature of the substrate during oxidation and the partial pressure of the oxygen during oxidation may be altered to control the periodicity of the nanotrenches. Furthermore, the substrate may be oxidised in an oxygen plasma environment to achieve improved alignment and periodicity of the nanotrenches.

The periodicity of the nanotrenches generally varies in range from approximately 1nm to 20nm. For example, the periodicity of the nanotrenches for an Mo(H O) substrate is in the range from approximately 1 nm to 10nm.

According to one embodiment of this aspect of the invention, the multilayer structure of step (c) comprising the oxidised substrate, the dopant nanowires and the overlayer are annealed.

It is also envisaged that after formation of the nanowires, when an overlay material is used, the assembly can be subjected to treatment exposing the conducting nanowires. In this way, semiconductor material that is not doped can be removed and the nanowires exposed.

In another way of carrying out the invention prior to annealing the dopant material, an over layer material is deposited on the dopant nanowires. In another way of carrying out the invention the annealing is carried out first then to alfow diffusion of the dopant material through the film of molybdenum oxide and then the over layer is deposited once the nanotrenches have been formed.

It is envisaged that in some embodiments, it may not be necessary to anneal the multilayer construction and that the dopant nanowire embedded into a semiconductor material or placed in contact with a semiconductor material may form nanowires themselves. It will be appreciated that this depends entireiy on the type of conductor material and the dopant materia!, as well as an arrangement of the dopant elements within the semiconductor material.

According to a third aspect of this invention, there is provide an electronic switching device comprising a single nanowire or an array of nanowires as described previously.

It is envisaged that an electronic switching device may be made from one single nanowire or an array of nanowires. Thus for example a transistor may be made from a single nanowire or an array of nanowires. Obviously field effect transistors made in this way are particularly advantageous.

Preferably, this aspect of the invention relates to a transistor, preferably a field effect transistor, comprising a single nanowire or an array of nanowires as described previously wherein the transistor comprises a drain, a source, gate and a channel between the drain and the source wherein the nanowire or the array of nanowires forms the channel. Ideally, the drain and the source located at opposite ends of the conducting nanowire and a gate is located between the drain and source.

The transistor may further comprise a dieiectric layer, preferably an oxide or nitride, interposed between the conducting nanowire channel and the gate.

This aspect of the invention also provides, a method of making a field effect transistor as defined above comprising the steps of forming the dielectric layer, preferably a layer of oxide or nitride, directly on the conducting nanowire channel and forming the gate over the dielectric layer.

Detailed Description of the Invention

The invention can be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to accompanying drawings in which:

Fig 1. is a high resolution STM image of a molybdenum (1 10) surface;

Fig. 2 is a high-resolution STM image on a treated molybdenum (110) surface where nanotrenches are formed.

Fig. 3 is a schematic representation of a cross-section perpendicular to the surface of a treated molybdenum (1 10) surface with nanotrenches

Fig. 4 shows a high-resolution STM image of a molybdenum surface treated under different conditions.

Fig. 5 shows another high-resolution STM image of a molybdenum surface treated under different conditions.

Fig. 6 shows a STM image of a treated molybdenum surface covered by a layer of Fe, 2 monolayers thick. Fig. 7 shows a STM image of a treated molybdenum surface covered by a layer of Fe, 0.25 monolayers thick.

Fig. 8 shows a STM image of the surface of the same sample as shown in Fig. 7 following the anneal at 150 deg C for 10 min in ultra high vacuum.

Fig. 9 shows schematically the formation of conducting nanowires in accordance with the invention.

Fig. 10 shows schematically a later stage of formation of conducting nanowires in accordance with the invention.

Fig. 11 shows schematically the formation of conducting nanowires in accordance with the invention.

Fig. 12 shows schematically a later stage of the formation of conducting nanowires in accordance with the invention.

Fig. 13 shows another embodiment of the conducting nanowire array in which the conducting nanowires are exposed.

Fig. 14 shows a transistor device that is based on the conducting nanowires formed according to the invention.

Fig. 15 shows another embodiment of the transistor device that is based on the nanowires formed according to the invention.

Fig. 16 shows schematically another embodiment of the conducting nanowires.

Fig. 17 is a cross sectional view demonstrating the process of formation of dopant nanowires by glancing angle deposition.

Fig. 18 is a diagrammatic representation of one of the devices for forming nanowires according to the invention.

In this specification the term "film" and "layer" are used interchangeably, in this specification a film or layer, in which the aerial density of atoms is lower than the aerial density of atoms within the cross-section of the film material parallel to its surface, is called a fractional layer. Such a film does not cover totally the surface to which it adheres, leaving the areas of the bare substrate. One can also say that the fractional layer is a film with the nominal thickness below one monolayer. Therefore in this specification, a film with the nominal thickness of one monolayer is the film, in which the aerial density of the atoms is equal to the one of the substrate.

The following publications are included in their entirety by way of reference and together with the previously referenced documents are to be considered as forming part of the prior art.

The inventors of the present patent application have studied extensively the surfaces of refractory and noble metals such as Mo, W, Rh, Pt and in particular the surface of molybdenum (110). The indexes (1 10) referred here are the Miller indexes as used in conventional surface science and crystallography. Further information on this convention can be found in extensive literature known to those skilled in the art of epitaxial growth, condensed matter, surface science and crystallography. For further information on the surface of Mo(HO), reference is made to (S. Murphy, D. MacMathuna, G. Mariotto, i.V. Shvets, Morphology and strain-induced defect structure of ultrathin epitaxial Fe films on Mo(HO), Phys. Rev. B 66 195417 (2002) ). In brief, the cleaning procedure consists of several repetitions of heat treatment in an oxygen atmosphere of 10^~6 Torr followed by a number of high temperature flashes bringing the substrate temperature to 1500<T<1700 deg C in ultrahigh vacuum. Fig. 1 shows the (110) surface of a molybdenum single crystal. The size of the area presented can be seen from the scale bar on the image. The surface consists of atomic terraces separated by atomic steps. The methods for preparation of such a surface are described in detail in the above references which, as stated above, are incorporated into the application as background information. The sample referred to in Figs. 2, 3, 4, 5, 6, 7, 8 has a low miscut angle and therefore its surface looks rather featureless when imaged using conditions similar to the ones in Fig. 1. The step edges of the terraces are parallel to the <001 > direction and the average width of the terraces is some 100 nm. It should be stressed that the word "featureless" refers here to the surface only when it is prepared under conditions simiiar to the ones referred to in Fig. 1. One can readily see that the surfaces presented in Figs. 2, 3, 4, 5, 6, 7, 8 do have very rich topography. It is not a topography of vicinal atomic steps of a surface of miscut from a low index plane but rather a different one. Such a topography is developed only when the surface preparation conditions are altered as described in detail below.

The images shown in Figs. 1 , 2, 3, 4, 5, 6, 7, 8 were obtained by means of a Scanning Tunneling Microscope (STM) in ultra high vacuum with a bias voltage of 200-300 mV and a current of 0.1 nA.

Fig. 2 shows the surface of Mo(110) that was first treated in the same way as described with reference to Fig. 1 and then oxidized according to the following procedure. The sample was oxidised at 800 degrees C for 5 min at an oxygen pressure of 5^*10^"6 Torr. The sample was then cooled down at this oxygen pressure and then the oxygen was pumped out to establish the conditions of ultra high vacuum in the chamber to maintain the sample cleanliness. It was possible to see that the surface is covered by a regular pattern of trenches with the periodicity of 5.7 nm and the depth of 2.8 nm. These values were measured by means of a Scanning Tunneling Microscope. These features are hereinafter referred to as "nanotrenches". The direction of the nanotrenches is along <001>. The size of the image can be obtained from the scale bar. The diagrammatic sketch of the cross- section of the nanotrenches is shown in Fig. 3. In this figure the substrate is identified by the numeral 1 , the crests of the nanotrenches- by the numeral 3 and the troughs of the nanotrenches- by the numeral 4.

The periodicity and the depth of the nanotrenches depend on the conditions of the oxidation treatment in oxygen. For example, if the oxidation time is increased to 15 min and the oxygen pressure is kept unchanged at the level of 10^"6 Torr, then the periodicity of the nanotrenches becomes 8.3 nm and their depth 4.9 nm. This is shown in Fig. 4. On the other hand if the substrate is treated at 900 deg C for 2 minutes at an oxygen pressure of 10^'7 Torr, then the periodicity of the nanotrenches is 2 nm and their depth is only 0.035 nm as shown in Fig. 5. We have found that for the Mo(110) surface the favoured pressure range suitable for the formation of the nanotrenches is 1O^'a to 10^"s Torr. The scale bars in Figs. 4 and 5 indicate the size of the images.

Similar surface nanostructures can be formed by subjecting the surface to other electronegative elements, such as S, Se, Ti and electronegative complexes. Simiiar nanostructures can be formed by applying simitar process to surfaces of other metals.

Fig. 6 shows the surface of oxidized molybdenum with nanotrenches formed on it. The surface is covered by a 2 monolayer thick film of Fe. The film is deposited at room temperature after the formation of nanotrenches. The film forms clusters of Fe positioned at the troughs of the nanotrenches. The scale bar on the image indicates the size of the imaged area.

Fig. 7 shows a similar situation in which the film of Fe is only 0.25 monolayers thick, again deposited at room temperature on top of the surface containing nanotrenches. In this case the film nucleates at the crests of the nanotrench structure. If the film is annealed in ultra high vacuum for 10 min at 150 deg C, then the Fe clusters form nanowires positioned along the crests of the nanotrench structure as shown in Fig. 8. The scale bars on the images indicate the size of the imaged areas.

It should be stressed that the length of the nanowires is very long, compared to their width, they are at least several micrometers long. We confirm this by means of large-scale STM images. It can be further confirmed that the nanowires cover essentially the entire surface or most of it. Therefore the images presented by us of the nanotrenches and the nanowires are the representative images, not images of a carefully selected area of the surface.

In this specification, the chemical formula of the layer of molybdenum oxide is not defined. There does not appear to be any reliable experimental technique that would allow deriving such a formuia readily. Some indications of the stoichiometry but not a simple conclusive answer may be obtained using Raman optical spectrometry which can distinguish between metal complexes in different valence states. Moreover, it is likely that defining such a formula could be fundamentally flawed. The reason is that chemical formula in a crystallographic structure assumes translational symmetry in all the three directions. In this structure, there is no translational symmetry in the direction perpendicular to the surface. Defining which layer of subsurface belongs to the surface and which one belongs to the bulk of the substrate may be ambiguous. Furthermore, it is likely that the composition of the oxygen-molybdenum ratio throughout the cross-section of the nanotrenches changes. At the same time we do state that this particular structure of nanotrenches is a form of oxide as it consists of oxygen and molybdenum atoms only. We have established with our experiments that in the case of Mo(110) surface the stoichiometry of the molybdenum oxide layer is close to IvIoO₂.

Fig. 9 shows the formation of conducting nanowires in accordance with the invention. We shall focus on what appears to be the essential steps in the fabrication procedure. Those skilled in the art will readily appreciate that numerous other steps may be added to the process including substrate or multilayer washing, cleaning, drying, film characterization, plasma treatment, etc. These are not discussed in the present specification.

According to the invention, the substrate is prepared to form the nanotrenches as described in detail above with reference to Figs. 2, 3, 4, 5. In this particular embodiment we refer mainly to the substrate of oxidized Mo(110). However, it should be appreciated that substrates of other metals and metalloids can be prepared in the same way. For example we expect that the substrates of other transition metals with the (110) orientation or vicinal substrates with (11 1 ) and (100) orientation can be prepared in the same way. For background information on vicinal substrates and definitions we refer to PCT Patent Application PCT/ 1 E 04/00034, "A Magnetoresistive Medium", filed 2004 by the present applicants. Then the surface containing the nanotrenches is covered by a thin film of the material that is referred to as the dopant material. In this particular embodiment the dopant material is such that it can form donor or acceptor type (n-type or p-type) impurities in a semiconductor material. For example, this could be As, Sb, In, Ga, Al, B or P (or indeed atoms of other elements) if the semiconductor materia! in the over layer referred to later, is Ge or Si. The lists of conventional dopant materials are known to those skilled in the art of semiconductor technologies as well as the lists of semiconductor materials used in combination with such dopant materials. It is the essential point of the invention that the dopant material is positioned on the substrate in close correlation with the nanotrenches. This is iliustrated in the above example with reference to Figs. 6, 7, 8. The dopant material can be positioned along the crests or along the troughs of the nanotrenches, and both combinations could be acceptable embodiments of the present invention. Whether the dopant material positions itself at the crests or at the troughs depends on the specific combination of the dopant material and the substrate and also on the growth conditions such as substrate temperature and deposition rate. In this particular embodiment we consider the situation when the dopant material is positioned along the troughs of the nanotrenches. The layer of dopant material positioned in correlation with the surface containing nanotrenches is called the layer of dopant nanowires.

Referring now specifically to Fig. 9, there is illustrated a substrate 1 having nanotrenches, indicated generally by the reference numeral 2, having crests 3 and troughs 4. A fractional layer of dopant material is positioned along the crest 3 to form dopant nanowires 5. Then an over layer 6 is positioned on top of the substrate 1 to cover all the nanowires 5. Thus, the substrate 1 , dopant nanowires 5 and over layer 6 form the multilayer structure.

The over layer 6 in this embodiment is a semiconductor material but as explained later in other embodiments it could also be an insulating material. Then in one particular embodiment, the multilayer structure is subjected to an annealing treatment, leading to diffusion of elements of dopant nanowires in the areas neighbouring to these. In this way the areas of semiconductor with dopant impurities incorporated in them form nanowires. These areas are positioned in the vicinity of the dopant nanowires. As the dopant nanowires form a regular array of relatively equally spaced one-dimensional structures with the periodicity of the nanotrenches, the entire structure then forms an array of doped semiconductor areas with the cross section in the range of nanometers or some tens of nanometres, i.e. conducting nanowires. Therefore, it would be a reasonable simplified model to say that in this embodiment the dopant nanowires disappear upon annealing and the conducting nanowires appear in their place or in their proximity. Typically, such a treatment leading to the diffusion of the material from dopant nanowires into the surrounding area is a short anneal. The temperature and the duration of the annea! need to be established empirically. As a starting point in the search for the anneal temperature and anneal time one could use the data from the semiconductor device manufacturing industry. This will be known to those skilled in the art of semiconductor device manufacturing. Preferably, the anneal time should be rather short. The rationale for this is: the longer is the anneal time, the greater is area of diffusion. Therefore, if the device is subjected to a long anneai time, the dopant nanowires will diffuse around the subsurface region forming two-dimensional profiie of the dopant impurities in which the impurity concentration depends essentially on one coordinate, distance to the surface. In other words the material from the dopant nanowires smears out along the surface. Annealing the dopant nanowires before the over layer is deposited on it may lead to a result completely different to the one where anneal occurs after the deposition of the over layer. The over layer serves as an additional tool to suppress the diffusion of the elements forming dopant nanowires around the surface of the substrate. It should be stressed that the material from the dopant nanowires will diffuse into both, the substrate 1 and the over layer 6. In a typical embodiment the substrate and the over layer are different materials. Therefore, if the diffusion coefficients of the dopant impurities are substantially different in these two materials, then the material of the dopant nanowires will preferentially diffuse into the material with higher diffusion coefficient.

Referring to Fig. 10, the effect of annealing is illustrated and the dopant impurities or dopant atoms are identified by the reference numeral 7. The dopant atoms are ilϊustrated diffusing into both the substrate 1 and the over layer 6 to form dopant nanowires, identified by the reference numeral 10.

Fig. 10 shows schematically the situation whereby the diffusion coefficient of dopant impurities into the substrate 1 is lower than the one in the over layer 6. The doped areas in the semiconductor over layer 6 then form the conductance channels with the cross-sectional dimensions in range of 0.2- 10 nm, i.e. conducting nanowires 10. The areas of the substrate into which dopant impurities diffuse may still remain insulating, as it is rather difficult to convert an insulating material into a conductor by doping.

As explained above, the periodicity of the nanotrenches is controlled by the treatment process. It can varied in the range of 1 nm to some 30 nm for a Mo(H O) substrate and in a wider range when the selection of the substrates is broadened. Therefore, in this way one can vary the periodicity of the conducting nanowires.

The method proposed also allows changing the cross-sectional dimensions of the nanowires. These are controlled by the thickness of the fractional layer of dopant material, the conditions during the deposition of the fractional layer of the dopant material (mainly substrate temperature), the periodicity of the nanotrenches and the conditions of the heat treatment following the deposition of the over layer. Qualitatively, for many material combinations the dependencies are as follows. The greater the thickness of the fractional layer of the dopant material, the greater are the cross-sectional dimensions of the conducting nanowires. The greater the separation between the nanotrenches, the greater are the cross-sectional dimensions of the conducting nanowires. The longer is the anneal time and the higher is the anneal temperature for the anneal with the over layer deposited over the dopant nanowires, the greater is the area into which the dopant materials diffuses from the dopant nanowires.

It should be pointed out that in some embodiments it may not be necessary to anneal the multilayer structure. Indeed the dopant nanowire embedded into a semiconductor material or placed in contact with semiconductor material may still form nanowire. This entirely depends on the type of the semiconductor material and dopant material as well as on arrangement of the dopant elements within the semiconductor. Clearly, the electronic properties of such a proximity conducting nanowire are different to those in nanowires formed by diffusion of dopant impurities around a greater size area of semiconductor. Nonetheless a conducting nanowire array can still be formed by an array of dopant nanowires placed in proximity of the semiconductor surface.

It is also clear to those skilled in the art that additional layers can be added to these structures. For example, these could include the protection layers, layers of oxides, etc. A further layer could be added between the oxide substrate and the dopant nanowires. These are not discussed.

Those familiar with the subject of epitaxial growth will readily appreciate that the over layer grown in the embodiment described above may not be epitaxial. The reason is that the condition for the lattice match between the over layer and the substrate is not necessarily fulfilled. This condition is the key one for achieving epitaxial growth. It may also be possible after the annealing some areas of the over layer will restructure so that the pattern of the crystalline grains within the over layer changes.

Further, it should be appreciated that the substrate could itself be a multilayer substrate. For example, if could consists of a layer of Mo grown on SrTiO₃ substrate. For example, it is well known that Mo(HO) film can grow over the surface of SrTiO₃ (100). The film forms clusters of epitaxial Mo(HO) areas. Mo(HO) is also known to grow epitaxially on AI₂O₃ (1-120) , R-cut. It should be further stressed that in many cases it is indeed desirable to have substrate with high resistance. The reason is that once electronic devices are formed on the substrate it is desirable in many cases to avoid current leakage through the substrate. The layer of oxide formed on the substrate (in this case molybdenum oxide) is likely to be a high resistance layer. However, it may contain pinholes through which the current may leak into the substrate. Therefore the substrate formed as thin film of metal deposited on an insulator has advantage that it has greater resistance.

With reference to Fig. 9, this drawing may be used to illustrate another embodiment in which the substrate 1 and the over layer 6 are insulators and the dopant nanowires 5 are conducting pathways supported by such insulating substrates. In this case the dopant nanowires 5 themselves form the conducting nanowires 10. In this case the term dopant may be inappropriate as it does not reflect the function of the dopant nanowire 5 of this new embodiment. However, we wili use the same term for all the configurations keeping in mind that dopant nanowires in these embodiments may consist of Au, Cu, Ag, Pb, Si, Ge, Pt, Rh, Mo, W, B, C, and countless other elements and their alloys and combinations.

Finally with reference to Figs. 9 and 10, in another embodiment the material of the dopant nanowires 5 could diffuse into the substrate 1 and turn it into a plurality of conductor nanowires. This would be applicable to some substrate materials, generally the small band gap insulators. The dopant atoms that diffused into the substrate 1 are shown in Fig. 1 by circles with numerals 7 positioned in proximity of the crests of the nanotrenches.

Referring now to Figs. 11 and 12, there is illustrated an alternative embodiment of the invention, in which parts similar to those described with reference to the previous drawings are identified by the same reference numerals. In this embodiment, the dopant nanowires 5 are formed in the troughs 4, however, in all other aspects, the nanowires 10 are formed in exactly the same way.

Following the formation of the conducting nanowires in a semiconductor over layer, the film containing the array of the semiconductor nanowires can be subjected to treatment exposing the conducting nanowires. For this the semiconductor material that is not doped is removed from the structure. Those skilled in the art of semiconductor devices know that there is a large number of routine processes that allows for different rate of removal of doped and undoped semiconductor material from the surface or for different rate of removal of material having different type of doping.

Referring now to Fig. 13, there is illustrated the nanowires, in which parts similar to those described with reference to the previous drawings are identified by the same reference numerals. The nanowires 10 are illustrated as totally exposed. It should be appreciated that the thickness of exposed conducting nanowires could be much greater than the thickness of the dopant nanowires This is because as a result of the anneal the dopant nanowire could diffuse into a relatively large area of the size of some 1 nm or 10 nm or even greater even though the thickness of the dopant nanowires themselves could be 1 nm or 0.5 nm or even smaller. As a result the rate of materia! removal (etch rate) of relatively large area of Si could be affected, again having the size of 1 nm, 10 nm or even greater,

The arrays of nanowires may be employed for making a number of electronic, optoelectronic and information storage devices. Referring now to Fig. 14, there is illustrated, by way of example and without limitation, a field effect nanowire transistor, indicated generally by the reference numeral 20. There is provided a drain 21 and source 22 for the field effect nanowire transistor 20 which are located at both ends of the conducting nanowire 10. There is provided a gate 23 located in the middle of the nanowire 10. The gate may be separated from the nanowire by an optional layer, e.g. oxide layer or dielectric layer identified by numeral 23{a). Further, the gate 23 is enveloped on three sides of the conducting nanowire, as illustrated in Fig. 14, to enhance the transistor on/off current ratio. It will be appreciated that the gate 23 may be located on a single side of the transistor and, in the typical nanowire transistor, the conducting nanowires is a doped semiconductor nanowire. However, other materials could also be used. In some embodiments, the layer 23(a) can be a layer of semiconductor doped to produce the current carriers opposite in charge to those in the nanowire itself. For example, if the nanowire is doped p-type, then the layer 23(a) may be an n-type doped layer and vice versa. This will be clear to those familiar with the basics of field effect transistors which normally require that a depletion layer is formed along the conducting channel in the vicinity of the gate region. Again in some other embodiments, the layer 23(a) could be a complex layer consisting of two sub- layers, of which the lower layer is designed to form the depletion layer and is composed of doped semiconductor and the upper layer isolates the gate 23 from the depletion layer (dielectric). These are again very basic elements known to those skilled in the transistor design. In some other embodiments, the depletion layer is formed by doping the material underneath the nanowire. It should be stressed that the size of the areas 21 , 22, 23 relative to the size of the nanowire can vary. For example, it is possible to construct embodiments where the separation between the three regions is much smaller than the size of the regions themselves. It is even possible to have embodiments where the three regions partially overlap. In this case additional dielectric layers need to be added to avoid direct electric contact between the three regions. In some embodiments, the regions 21, 22, 23 could spread well beyond the size of the nanowire to cover other areas of the substrate.

Referring now to Fig. 15, there is provided a further nanowire transistor, indicated generaiiy by the reference numeral 25 comprising a plurality of nanowires 10.

The operation of the nanowire transistors shown in Figs. 14 and 15 will be clear to those familiar with fiied effect transistors and therefore does not require further description.

In the embodiments described above, the dopant nanowires were formed from dopant material deposited on the substrate. For certain materials it may be possible to create a thin layer of dopant material by its segregation from the substrate. Typically this is achieved by annealing the material in a vacuum or under controlled atmosphere. Reference is made to the description of the segregation of Ca and K impurities from the bulk of a single crystal of magnetite Fe₃O₄ by some of the present inventors [G. Mariotto, S. F. Ceballos, S. Murphy, N. Berdunov, C. Seoighe, LV. Shvets, Phys. Review B 70 Art No 035417 (2004)]. We have found that in the example of this particular system a significant fraction of a monolayer can segregate at the surface after 20-100 hours of anneal time in ultra high vacuum chamber. Clearly, the anneal temperature, anneal time and requirements for the atmosphere in the chamber during the anneal depend on the type of substrate material and the type of impurity that segregates from the bulk on the surface. In some cases a thin layer may be deposited on the surface underneath the metal layer to facilitate the segregation of the impurities from the bulk on the surface. For example, one could deposit a thin layer of dopant material in between the substrate (AI₂O₃, SrTiO₃, etc) and the layer of Mo. Then the layer of Mo is oxidized to form the nanotrenches and then it is annealed to cause segregation of dopant material though the layer of molybdenum oxide. Such embodiment is schematically shown in Fig. 16. In this embodiment there is a composite substrate comprising Mo layer deposited on top of the thin layer 31 of dopant material in turn deposited on top of a further layer 30 of the substrate material such as AI₂O₃, SrTiO₃, and so on. Then the layer of Mo is oxidised to form the nanotrenches 2. Then the over layer 6 is deposited on top of the nanotrenches 2 and the multilayer structure is subject to anneal to cause the diffusion of the dopant materia! 31 through the layer of Mo and molybdenum oxide nanotrenches to form the nanowires 10, as illustrated. The rate of such diffusion is different for the crests and the troughs of the nanotrenches and therefore this will modulate the concentration of dopant impurities along the surface of the over layer. Alternatively, the over layer 6 could be deposited after the anneal that has lead to the formation of the array dopant nanowires by diffusion through the layer of Mo and molybdenum oxide. This is rather similar to earlier embodiments.

A further method for forming arrays of dopant nanoiwres which correlate with the position of the nanotrenches is now described. The reason why such a method may be required is that for some substrate materials and some dopant materials it may be difficult or impossible to achieve the growth that is correlated with the position of the nanotrenches on the surface based on simple deposition of the dopant material on the substrate covered by array of nanotrenches. For example, the dopant material may simply form clusters on the surface positioned randomly or alternatively the temperature of the substrate required to sustain the growth correlated with the nanotrenches on the substrate is too high resuiting in unacceptably high diffusion of the dopant material into the bulk of the substrate leading to smearing of the dopant nanowires.

Referring to Fig. 17, in which parts similar to those described with reference to the previous embodiments, are described by the same reference numerals, there is illustrated the formation of dopant nanowires 5. The substrate 1 is prepared as heretofore to form the nanotrenches 2 and the dopant nanowires 5 are deposited by directing a flux on the substrate 1 at a glancing angle β and illustrated by the arrows F. While in the embodiment described, the flux has been shown directed in leftwards direction, it equally well could be in the rightwards direction,

During the deposition the substrate 1 is kept at a temperature low enough to suppress the diffusion of adatoms of the fractional iayer forming the dopant nanowires 5. In this case the adatoms of the layer forming the dopant nanowires will preferentially nucleate on the left side of each nanotrench as the right side is shadowed from the flux. The nanowires of dopant material may grow as non- epitaxial or as expitaxial. This depends of the specific choice of the dopant material and the substrate. In this way area in the vicinity of each nanotrench is subdivided into two regions: called T and T, that are respectively not covered and covered by the fractionai layer forming the dopant nanowires 5. The regions T and T' form, in effect nanostripes that are positioned along the length of the nanotrench. The ratio between the widths of the areas T and T are given by the angle β and by the profile of the nanotrenches (their depth and width). This is the matter of simple geometrical calculation.

We have explained above in detail how to utilize the array of dopant nanowires to form the array of conducting nanowires. Here we briefly outline some of these embodiments with reference specifically to Fig. 17. In one such embodiment, the substrate with the dopant nanowires is annealed. This leads to the diffusion of the dopant atoms thus forming the nanowires incorporated into the substrate. This would only be suitable for some types of materials, generally with low band gap that can be readily made conducting by doping. Then the optional layers can be deposited on top of the array of the nanowires if required. In another embodiment the dopant nanowires can actually be used as conducting nanowires.

According to another embodiment with reference to Fig. 17, the over layer as described above is deposited on top of the bare substrate and on top of the fractional layer forming the dopant nanowires 5, e.g. by deposition in the direction normal to the substrate or at a non-shallow angle. It may also be possible to deposit the over layer at a shallow angle β' that is equal to β or different from it. Following the deposition of the over layer (not shown) the structure is annealed forming the nanowires resulting from the diffusion of the atoms of dopant nanowires into the substrate 1 and into the over layer 6 as described above. The anneal temperature and the anneal time may be optimised experimentally.

Thus to grow the fractional layer according to the embodiments referred to in Fig. 17, the flux of the material to form the fractional layer should arrive at the substrate 1 at a shallow angle, nearly parallel to the surface. For example, the angle β couid be in the range of some 0.1 to 10 degrees but these values of the angle are given here merely as examples. In practice the value of the angle β should be optimised once the specific requirements for the dopant nanowires are given. To direct the flux at such a shallow angle on the substrate, it may be convenient to use a source located at a significant distance away from the substrate, e.g. at the distance of some 0.5 to 5 meters. These values are given here as examples and values outside this range are also possible.

Referring to Fig. 18, there is shown schematicaily a device, indicated generally by the reference numeral 40, for forming a nanowire array according to the invention. The device 40 is connected to a vacuum pump (not shown) through an outlet 41 and forms two growth chambers: namely a first chamber 42 and second chamber 43. The first growth chamber 42 mounts an effusion cell 44 containing evaporant material 45, the evaporant material 45 being used to provide the dopant nanowires. A substrate mounting device 50 is provided in the position that is common for the growth chamber 42 and growth chamber 43. The substrate mounting device 50 is oriented so that the substrate 1 is positioned in such a way that the nanotrenches 2 are parallel or almost parallel to the axis 46 of the growth chamber 42, identified by the reference numeral 46 and shown by one of the interrupted lines. The axis of the effusion cell 44 coincides with the axis of the chamber 42. The substrate 1 is displaced from the axis of the effusion cell 44 by a distance d and located at a linear separation D from the cell 44.

A deposition source 47 is located in the growth chamber 43 having an axis, identified by the reference numeral 48 and shown by interrupted line. The deposition source 47 could be any source suitable for the deposition of the film, e.g. magnetron, Knudsen cell, electron beam evaporator, etc. The flux of the material to form the film can arrive to the substrate 1 that is mounted on the mounting device 50 along a direction nearly norma! to the surface of the substrate 1.

In one embodiment, the surface of the substrate 1 is positioned parallel to the axis of the chamber 42. The distance d, as can be seen in Fig. 18, is much smaller than the separation D between the effusion cell 44 containing the evaporant 45 and the substrate 1 mounted in the mounting device 50. The effusion cell can be a Knudsen cell, thermal cell, electron gun heated cell, magnetron or other cell suitable for vacuum deposition of the material to form the dopant nanowires 5.

If the distance d is much smaller than the distance D, then the angle β in units of radian is equal to d/D. Thus by controlling the off-axis displacement d of the substrate, one can set the desired value of the angle β.

Further there are provided deposition monitors 51 and 52, measuring and controlling the flux from the effusion cell 44 and deposition source 47 respectively. The deposition monitor 51 is aligned to detect the flux of the evaporant material 45 along the axis of the growth chamber 46. The deposition monitor 52 is aligned to detect the flux of the material used to form the over layer film along the axis 48 of the growth chamber 43. It should be noticed that as the surface of the deposition monitor 51 is not parallel to the surface of the substrate 1 but nearly perpendicular to the substrate surface (so that it detects flux in the direction almost parallel to the surface of the substrate 1 ), the coverage of the materia! to form the dopant nanowires is not equal to the coverage detected by the deposition monitor 51. Thus, it needs to be multiplied by sin β. Again this does not require any further description to those skilled in the art. The chamber 43 is also equipped with pumps, controllers and various other monitors that are not shown in detail. The array of nanowires 5 is grown by first depositing the required amount of the material to provide the dopant nanowires by using the effusion cell 44 and the deposition monitor 51. Then the over layer is deposited by using the deposition source 47 and the deposition monitor 52.

Alternatively, to form an array of nanowires according to the invention one could utilize an instrument substantially similar to the one shown in Fig. 18 that is different in one significant aspect: instead of the effusion cell 44 it comprises a well- coilimated ion gun which is the source of energetic ions, e.g. source of Ar, Ga or O ions. The ions from the gun are directed to the surface of a substrate 1 at a shallow angle forming the ion beam. To control the angle of the ion beam, the sample position could be selected as described above in relation to Fig. 18. In addition to that one could use a further method of control utilizing the fact that ions are charged particles and their movement direction can be altered by means of an external electrostatic fieid. Thus to control the direction of the ion beam, an electrostatic field substantially perpendicular to the axis of the chamber 42 is formed. This can be done using techniques well known to those skilled in the art of ion sources. The ion gun can often be used for depositing ions on the surface or for etching the surface by a beam of ions. Whether the beam etches the surface or used for deposition is determined by energy of the ion beam and also by the substrate temperature. By using this instrument one could form the array of nanowires as follows. The ions could be used to form the dopant nanowires as described above in previous embodiment when the ion gun is set in the regime favouring the deposition of ions on the surface. This may not be possible to achieve for ail the ion sources, but only for some combinations of the substrates and ions. For example, this could be achieved for Ga ions but may be difficult to achieve for Ar ions. After that the over layer is deposited and the multilayer structure is subjected to anneal as explained in detail above. Alternatively, the method couid be as follows. Firstly the substrate is covered by a thin layer of dopant. For this the entire substrate could be covered at a non-glancing angle. Following this, the substrate could be subjected to ion etching at a shallow angle thus removing the fractions of the thin layer of dopant from some parts of the nanotrenches. For example, this could be done with etching by Ar ions removing the dopant material from those parts of the atomic terraces that are exposed to the ion beam. For this ion gun should be set in the regime of etching the surface by the ion beam. In this way the dopant nanowires are formed on the surface. Then the over layer is deposited and the multilayer structure is subjected to anneal as described earlier. It is also clear that the method could be a combination of the two above approaches. For example, the thin layer of dopant could also be deposited at a shallow angle thus forming dopant nanowires of a particular width determined by the angle β-, of deposition of dopant atoms. Then the substrate could be etched by directing the beam of ions at an angle β₂ that could be equal to P₁ or different from it.

Numerous other combinations will be now obvious to those skilled in the art.

It is envisaged that the device utilising the nanowire transistors will typically comprise massive arrays of such transistors accommodated on the area of up to some few centimetres square or even greater. The typical size of a modern processor or memory chip is in this range. Given that the separation between the nanowires is in the nanometre range, it is clear that the total number of nanowires on a chip could amount to many millions and possibiy many biiiions. These arrays could be used e.g. for making processors and memory chips. In this fight it will be useful to briefly outline how these arrays of nanowires could be utilised for such appiications.

The array of transistors can be established in numerous ways as will be clear to those skilled in the art of computer processor and memory chip design. Typically the architecture of a modern processor or memory chip implies a multilayer layout. The modern processors utilising 65 nm technology employ up to 8-10 layers. Essentially, just one layer of these 8-10 layers is a functional Si layer containing transistors whereas most other layers contain metallization interconnects and auxiliary elements. This complex three-dimensional layout is employed to reduce the heat loss and enhance the speed of the processor or memory chip. Typically the thickness of metallization and the size of the features in the upper layers are greater than these in the lower ones. For a typical architecture of a microprocessor one could look at the publication [S. Thompson, M. Alavi, M, Hussein, P. Jacob, C. Kenyon, P. Moon, M. Prince, S. Sivakumar, S. Tyagi, M. Bohr, "130 nm Logic technology featuring 60 nm transistors, low-K dielectrics and Cu interconnects", Intel Technology Journal vol 6 issue 2, pages 5-12] which is incorporated in the specification as background information. The invention envisages that the array of nanowires may be used in a similar fashion: one layer contains all the field effect transistors based on the nanowires and the all the interconnects are arranged in other layers deposited on top of the nanowire array. The functional layer containing the nanowires may need to be segmented into segments assigned to individual transistors leaving some gaps in between the segments in which the nanowires are removed. Alternatively, nanowires in between the segments could be doped in such a way that they are no longer conducting. For example, the substrate could be segmented into the areas with the lateral dimensions of some 10-50 nm by 10-50 nm so that the lateral size of a single transistor is e.g. 50 nm by 50 nm. It is envisaged that in order to enhance the yield of the technology it may be beneficial to include a number of nanowires into a single transistor. For example, a single transistor could contain 2 or 5 or 20 nanowires running substantially along the same direction. In this way if one of the nanowires is missing at the segment allocated to the transistor, this may not have catastrophic effect such as a dysfunctional transistor that would occur otherwise. It is further envisaged that in a typical transistor according to the invention, the length of the nanowire will not be too long. For example, even if the technology allows producing nanowires that are many micrometres long, the practical length of the nanowires in a single transistor could be less than 100 nm. Therefore, one long nanowire may need to be cut into segments along its length to make a number of independent transistors. In this way the surface covered by the nanowires should be considered as medium that needs to be segmented for further processing. Again it should be stressed that the term "cut nanowire" does not necessarily mean that the nanowire is cut physically into segments. If could mean that the nanowire is doped by subsequent lithography process in such a way that it contains conducting and nonconducting segments along its length. Clearly making such a processor would require numerous lithography steps on a substrate containing nanowires. It is also possible to alter the manufacturing process in such a way that the segmentation of the surface into areas for individual transistors is done before the formation of the nanowires. In this way the nanowires formed in various segments will be electrically insulated from each other right from the moment of their formation.

It should be further stressed that there is a massive variety of transistor types and even types of field effect transistors. These include n-MOS (NMOS) n-type Metal Oxide Semiconductor Field Effect Transistor, p-MOS (PMOS) p-type Metal Oxide Semiconductor Field Effect Transistor, CMOS - Complementary Metal Oxide Semiconductor Field Effect Transistor, and other types of field effect transistor. CMOS technology utittises pairs of transistors working in tandem to reduce the energy consumption of transistor-based logic and to enhance its speed. These technologies are well known to those skilled in the art of electronics and transistor design. For example, CMOS is known since 1960s. The credit for its invention is often ascribed to F. Wanlass and Fairchϋd Semiconductors. There are also numerous recent technological improvements routinely used for the transistor design. For example, low K dielectrics are used in the gate dielectric layer. The gate metal electrode that gave the name MOS is in fact routinely not made of metal any longer but e.g. of polycrystalline Si. Yet, the old abbreviation MOS originating from the time when gate electrode was typically made of metal Al, is still commonly used. We will not expand on this aspect as it can be found in numerous texts. An introductory text by JJ. Sparkes, "Semiconductor Devices", Chapman and Hall 1994 is incorporated in the specification as part of the background information.

We should also stress that although the examples of electronic devices are based on field effect transistor, other device types could be used. For example, one couid also use the nanowire as the body of the bipolar transistor so that the two ends of the nanowire become emitter and collector and its middle part contains the base. In this case the type of doping along the nanowire needs to be modified along its length with the help of lithography.

In the specification the terms "comprise, comprises, comprised and comprising" or any variation thereof and the terms "include, includes, included and including" or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

The invention is not limited to the embodiment hereinbefore described, but may be varied in both construction and detail.

Claims

Claims:

1. A nanowire assembly comprising:

a substrate (1) having an oxidised surface forming nanotrenches (2) with peaks (3) and troughs (4); and

conducting nanowires on one of the peaks or troughs.

2. The nanowire assembly according to claim 1 wherein the substrate (1 ) is a transition metai.

3. The nanowire assembly according to claim 2 wherein the substrate (1) is selected from one of the following group Mo, W, Pt, Pd, Rh, Ti, V and Nb.

4. The nanowire assembly according to any of claims 1 to 3 wherein the substrate (1 ) has a (111), (100) or (110) orientation or another surface that makes small angle with (11 1 ), (100) or (110) planes.

5. The nanowire assembly according to claim 4 wherein the substrate (1 ) is Mo(HO), Mo(100) or Mo(111).

6. The nanowire assembly according to any of the preceding claims wherein the substrate (1 ) is a multilayer substrate.

7. The nanowire assembly according to claim 6 wherein the multilayer substrate comprises the substrate deposited on SrTiO₃ or AI₂O₃.

8. The nanowire assembly according to claim 7 comprising a Mo substrate on

SrTiO₃.

9. The nanowire assembly according to any of the preceding claims wherein the conducting nanowire comprises a dopant material which forms a dopant nanowire (5) on one of the peaks or troughs.

10. The nanowire assembly according to claim 9 wherein the dopant material is selected from one or more of the following As, Sb, In, Ga, Al, B or P.

11. The nanowire assembly according to claim 9 wherein the dopant material is selected from one or more of the following Au, Cu, Ag, Pb, Si, Ge, Pt, Rh, Mo, W, B, C, alloys thereof and combinations thereof.

12. The nanowire assembly according to claim 10 or claim 11 wherein the dopant material forms p-type or n-type impurities in a semiconductor material.

13. The nanowire assembly according to any of claims 6 to 12 wherein the multilayer substrate is covered by a fractional monolayer of dopant material.

14. The nanowire assembly according to any of the preceding claims further comprising an over layer of material deposited on the dopant material to allow the diffusion of the dopant material into one or both of the substrate and the over layer.

15. The nanowire assembly according to claim 14 in which the over layer (6) is an insulating, semiconducting or conducting material.

16. The nanowire assembly according to claim 15 in which the over layer (6) is selected from one or more of the following Si, Ge, Si-Ge alloy, GaAs, InP.

17. The nanowire assembly according to any of the preceding claims wherein the overlayer (6) and substrate (1) are insulators and the dopant nanowire (5) forms the conducting naπowires.

18. The nanowire assembly according to any of the preceding claims further comprising additional layers over the overlayer (6).

19. The nanowire assembly according to any of the preceding wherein the periodicity of the nanotrenches (2) varies in range from approximately 1 nm to approximately 20nm.

20. The nanowire assembly according to any of the preceding claims wherein the periodicity of the nanotrenches (2) for an oxidised Mo(HO)₁ W(110), Ti(HO), V(HO) substrate is in the range from approximately 1nrn to 10nm.

21. The nanowire assembly according to any of the preceding claims which is electrically or optically transmitting.

22. A method of forming an array of nanowires comprising:

a. oxidising a surface of a substrate (1 ), preferably at an elevated temperature, to form nanotrenches (2) having alternate peaks (3) and troughs (4);

b. directing a dopant material onto the substrate to form spaced-apart dopant nanowires (5), each dopant nanowire being on one of the peaks (3) or troughs (4);

c. depositing an over layer (6) to form a multilayer structure, and

d. optionally annealing the multilayer structure to aliow the diffusion of the dopant material into either of one or both of the substrate (1 ) and the over layer (6).

23. The method according to claim 22 wherein the substrate (1) is transition metal, preferably selected from one of the foliowing group Mo, W₁ Pt, Pd, Rh, Ti, V and Nb.

24. The method according to claim 22 or 23 wherein the substrate (1 ) has a (111 ), (100) or (110) orientation or another surface that makes small angle with (111), (100) or (110) planes, preferably Mo(110) or Mo(111 ).

25, The nanowire assembly according to any of claims 22 to 24 wherein the substrate (1 ) is a multilayer substrate.

26. The nanowire assembly according to claim 25 wherein the substrate (1) is deposited on SrTiO₃ or AI₂O₃ to form a multilayer substrate, preferably a Mo substrate on SrTiO₃.

27. The method according to claim 26 wherein the multilayer substrate is covered by a fractional layer of dopant material.

28. The method according to any of claims 22 to 26 wherein the multilayer substrate is oxidised at an elevated temperature to form a templated oxide layer and a semiconductor layer, preferably chosen from one of the following Si, Ge, GaAs, InP or Si-Ge alloy, is subsequently deposited over templated oxide layer.

29. The method according to any of claims 22 to 26 wherein the oxidised substrate is a film of molybdenum oxide

30. The method according to any of claims 22 to 29 comprising steps (a), (b), (c) and (d).

31. The method according to any of claims 22 to 30 wherein the over layer (6) material is a conducting, semiconducting or an insulating material.

32. The method according to claim 31 wherein the over layer (6) material is selected from one or more of Si, Ge, Si-Ge alloy, GaAs and/or InP.

33. The method according to either claim 31 or claim 32 wherein the over layer

(6) material and the substrate are different materials.

34. The method according to any of claims 22 to 33 in which the material of the dopant nanowires (5) preferentially diffuses into the substrate (1 ) or over layer (6) which has the higher diffusion coefficient.

35. The method according to any of claims 22 to 33 further comprising the step of exposing the conducting nanowires by removing the over layer (6) that is not doped or the semiconductor material that is not doped.

36. The method according to any of claims 22 to 34, wherein the periodicity of the nanotrenches (2) is controlled by the treatment process.

37. The method of claim 36 wherein the temperature of the substrate during oxidation and/or the partial pressure of the oxygen during oxidation are altered to control the periodicity of the nanotrenches (2).

38. The method according to claim 36 or ciaim 37 wherein the substrate is oxidised in an oxygen plasma environment to achieve improved alignment and periodicity of the nanotrenches (2).

39. The method according to any of claims 36 to 38 wherein the periodicity of the nanotrenches (2) varies in range from approximately 1 nm to 20nm

40. The method according to claim 39 wherein the periodicity of the nanotrenches (2) for an Mo(HO) substrate is in the range from approximately 1nm to 10nm.

41. The method according to any of claims 22 to 40 wherein the multilayer structure of step (c) comprising the oxidised substrate (1), the dopant nanowires (5) and the overlayer (6) are annealed.

42. An electronic switching device comprising a single nanowire or an array of nanowires according to any of claims 1 to 21 or made in accordance with the method of any of claims 22 to 41.

43. A transistor, preferably a field effect transistor, comprising a single nanowire or an array of nanowires according to any of claims 1 to 21 or made in accordance with the method of any of claims 22 to 41 wherein the transistor comprises a drain, a source, gate and a channel between the drain and the source wherein the nanowire or the array of nanowires forms the channel.

44. The transistor according to claim 43 wherein the drain and the source are located at opposite ends of the conducting nanowire and a gate is located between the drain and source.

45. A transistor according to either claim 43 or claim 44, further comprising a dielectric layer, preferably an oxide or nitride, interposed between the conducting nanowire channel and the gate.

46. A method of making a field effect transistor according to claim 45 comprising the steps of forming the dielectric layer, preferably a layer of oxide or nitride, directly on the conducting nanowire channel and forming the gate over the dielectric layer.