CN101960570A - 制造半导体器件的方法和半导体器件 - Google Patents
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Abstract
公开了一种制造半导体器件的方法,包括:提供绝缘载体(10),例如氧化物晶片;在所述载体上形成在源极结构(12)与漏极结构(14)之间的沟道结构(20);选择性地去除沟道结构(20)的一部分,从而在沟道结构(20)与载体(10)之间形成凹入部(22);将器件外露于退火步骤,使得沟道结构(20’)获得实质上圆柱形形状;形成围绕实质上圆柱形沟道结构(20’)的限制层(40);生长围绕限制层(40)的氧化层(50);以及形成围绕氧化层(50)的栅极结构(60)。所述实质上圆柱形沟道结构20’可以包括半导体层30。还公开了相应的半导体器件。
Description
技术领域
本发明涉及制造半导体器件的方法,具体地涉及制造周围栅极(GAA)FinFET器件的方法。
本发明还涉及半导体器件,具体地涉及GAA FinFET器件。
背景技术
由于无法控制的短沟道效应,不断缩小传统体金属氧化物半导体场效应晶体管(MOSFET)的尺寸变得越来越困难。这种效应使晶体管性能在切换效率和换向速度方面下降很大。为此,研究若干备选的晶体管的设计,例如,在传统晶体管设计中使用诸如高k电介质之类的新型材料和金属栅极材料,和/或开发备选晶体管体系结构。
很具有吸引力的一种具体体系结构是所谓的FinFET器件,其中,在诸如氧化物晶片之类的绝缘载体上提供在源极极区和漏极区之间的细鳍形沟道,多个栅极控制沟道的电导率。由于FinFET器件卓越的固有性能以及其与传统CMOS工艺的高兼容性,FinFET器件被认为具有良好前景,FinFET器件与传统CMOS工艺的高兼容性意味着不需要在新制造器件方面的大量投入就可以制造这些器件。
与传统晶体管体系结构相比,FinFET器件的一个关键特点是很高的静电完整性。这是由于多栅极配置对沟道中的载体实施额外控制。因此,两个或三个栅极的存在提供了对短沟道效应的更好的控制,从而与传统晶体管设计相比得到高性能和改进的可缩放性。FinFET器件的自然扩展由周围栅极(GAA)器件来表示,其中栅极结构包封鳍形沟道。这进一步改进了对短沟道效应的控制。编号为US 2007/0145431的美国专利申请公开了这种器件的示例。
缩小晶体管尺寸在具有量化效应的器件(例如,基于量子线的晶体管)的设计中也具有重要作用。编号为2008/0014689的美国专利申请公开了一种周围栅极平面纳米线半导体器件,其中,在半导体衬底的绝缘层上方的源极和漏极之间形成平面纳米线,遍及平面纳米线而生长栅极堆叠。随后将该栅极堆叠蚀刻和图案化。在此过程中,在栅极和源极之间以及栅极和漏极之间切断平面纳米线,从而使周围栅极平面纳米线的一部分保持在源极和漏极之间并且起到沟道的有源区的作用。外延地再生长其余的周围栅极平面纳米线以与源极和漏极重新连接。
这种器件有若干缺点。制造工艺相对复杂,使得半导体纳米线具有平面形状,而不是便于最优化量化效应的圆柱形形状。
发明内容
本发明试图提供一种制造具有圆柱形形状沟道的半导体器件的方法,该圆柱形形状沟道具有围绕栅极。
本发明还试图提供一种具有圆柱形形状沟道的半导体器件,该圆柱形形状沟道具有围绕栅极。
根据本发明的第一个方面,提供了一种制造半导体器件的方法,包括:提供绝缘载体;在所述载体上提供在源极结构和漏极结构之间的沟道结构;选择地去除沟道结构的一部分,从而在沟道和载体之间形成凹入部;将器件外露于退火步骤,使得沟道结构获得实质上圆柱形形状;形成围绕实质上圆柱形沟道结构限制层;生长围绕限制层的氧化层;以及形成围绕氧化层的栅极结构。
本发明的方法允许使用传统CMOS工艺步骤来形成圆柱形沟道结构。例如,组合的沟道、源极和漏极结构可以是FinFET结构。限制层,即,比量子线的半导体层具有更大带隙的层,确保电荷载流子被限定在圆柱形沟道结构中,从而创建量子线。
在实施例中,所述方法还包括:在形成限制层之前,生长围绕实质上圆柱形沟道结构的半导体层,其中,限制层围绕实质上圆柱形沟道结构和半导体层,实质上圆柱形沟道用作半导体层的另一限制层。这在内部限制结构和外部限制结构之间创建了量子阱结构。这还提高了量子限制的效率,从而有助于减少线的表面电荷载流子的出现。半导体层可以是外延地生长的。
形成在绝缘载体上的沟道结构具有方形横截面。这具有优于例如传统FinFET工艺的优点,可以更容易地形成沟道结构,从而降低工艺复杂度。此外,已发现,与用传统FinFET工艺形成的器件相比,使用具有方形横截面的沟道结构会产生具有改进特性的器件。
可使用以上方法形成nMOS和pMOS型器件,从而便于通过传统CMOS工艺来制造包括本发明半导体器件的集成电路(IC)。
在实施例中,沟道结构是硅沟道结构,形成限制层的步骤包括:生长围绕实质上圆柱形沟道结构硅/锗SiGe层;以及在预定温度下生长围绕SiGe层的氧化层,所述预定温度便于Ge原子从SiGe层向实质上圆柱形沟道结构迁移,从而将SiGe层转化为限制层。该实施例产生用于在源极区和漏极区之间传输空穴的p型量子阱。
可以通过实施例来实现互补n-型器件,在该实施例中,沟道是应变硅沟道结构,形成限制层包括外延地生长SiGe层。可以将合适的III-V族材料而不是应变硅用于n型器件的半导体量子阱。
在当沟道结构是硅沟道结构时,可以实现p型器件,该p型器件具有夹在两个限制结构之间的量子阱,其中生长半导体层包括外延地生长SiGe层;形成限制层包括外延地生长围绕SiGe层的硅层。这种器件具有双层核心结构,包括由SiGe半导体量子阱包封的内部限制硅结构。
在当沟道结构是SiGe沟道结构时,可以实现相应的n型器件,其中生长半导体层包括生长应变硅层;形成限制层包括外延地生长围绕应变硅层的SiGe层。
根据本发明的另一方面,提供了一种在绝缘载体上的半导体器件,该器件包括源极区、漏极区以及在源极区和漏极区之间的沟道结构,沟道结构包括:实质上圆柱形核心结构,实质上圆柱形核心结构包括半导体材料;围绕核心结构的限制层;围绕限制层的氧化层;以及围绕氧化层的栅极结构。通过本发明的方法制造的这种器件具有卓越的导电特性和可控的短沟道效应,并且可以使用传统CMOS工艺技术来制造这种器件。
在实施例中,核心结构包括由半导体材料层围绕的另一限制结构,从而实现夹在两个限制结构之间的量子阱。这些半导体器件的半导体材料可以是硅/锗,在p型器件的情况下限制结构可以包括硅。半导体材料可以是应变硅,在n型器件的情况下限制结构可以包括硅/锗。备选地,n型器件可以包括合适的III-V族材料作为半导体材料。
附图说明
以下将参考附图,通过非限制性的示例对本发明的实施例进行更详细地描述。
图1图示了量子阱器件的原理;
图2A-F图示了根据本发明的实施例的制造半导体器件的方法实施例的关键步骤;以及
图3图示了根据本发明的备选实施例而制造的半导体器件。
应该理解,附图仅是示意性的而并不是按比例绘制的。还应理解,在所有附图中使用相同的参考标号以表示相同或相似的部分。
具体实施方式
图1图示了圆柱形量子阱的构思。这种阱有时也被称作量子线。在这种具体情况下,内部区域II(例如,Ge圆柱形沟道)夹在两个区域I(例如内部和外部硅层)之间。区域II用作电荷传递层,例如空穴传递层。由于分别针对区域I和区域II而分裂的价带(VB)和导带(CB)之间的能隙差异,量子阱形成在区域II内。因此,例如空穴的电荷载流子被限制在量子阱内部。换言之,区域I用作限制层以限制电荷载流子进入区域II。在量子阱内观测到的大子带分裂在很大程度上减少了子带内散射事件,在量子阱中,价带能级可以被提高至高于费米能级(EF)。因此,器件的载流子迁移率和电流驱动能力增大。在区域II包括Ge或SiGe且区域I包括Si的情况下,可获得pMOS器件。可以通过将应变Si层夹在两个SiGe层之间而获得nMOS器件。应变Si的备选包括合适的III-V族材料或其组合。
这种圆柱形量子阱结构的优点之一可以实现弹道传递行为。JieXiang等人在Nature,pp.489-493(2005)已经针对Ge/Si纳米线说明了这种行为。该器件的缺点是该器件的制造不能通过传统CMOS工艺来实现,而是需要基于生长纳米线的高度实验性工艺。
另一优点是,沟道中掺杂剂的缺乏和由于二维量子限制而获得的大子带分裂允许实质上增大器件中的平均自由行程。在Jie Xiang等人的前述出版物中已经实验性地说明了大于500nm的平均自由行程。即使通过区域II的电荷载流子传递是碰撞支配的,低和高场中的高电荷载流子迁移率也提高器件的性能。实际上,由于大子带分裂,子带内散射很大程度地减小。因此,极少的子带有效地参与传递,从而期望高迁移率。
这种器件还以对关于平面等同物的表面状态的更高抗扰性为特征,例如在号编为2008/0014689的美国专利申请中公开了平面等同物。晶体管的圆柱形特性和径向量子限制使得在圆柱体中心(即,远离圆柱体表面)产生导电沟道。这极大地减少了由于与在表面杂质的碰撞而导致的散射事件的出现,因此极大地提高了器件的迁移率。减小导电沟道(例如SiGe沟道)以及限制层(例如Si保护层)的直径使得可以增大区域II中的Ge浓度而不在器件中引起应变。
图2A-F图示了使用CMOS兼容工艺技术来制造这种器件的方法。在图2A中,提供了绝缘载体10(例如,氧化物晶片),在绝缘载体10上形成硅层并将该硅层图案化为源极结构12、漏极结构14以及楔在源极结构12和漏极结构14之间的沟道结构20。可以使用传统FinFET工艺形成源极结构12、漏极结构14和沟道结构20,沟道结构20是FinFET的“鳍”。
用于制造这种FinFET结构的许多合适的CMOS兼容工艺是本领域技术人员所熟知的,因此仅由于简洁原因而不做进一步解释。然而要强调的是,与传统的FinFET制造工艺不同,表征传统FinFET器件的高纵横比对本发明的半导体器件而言并不是必须的。事实上,鳍优选地具有方形横截面,因为这简化了产生鳍的蚀刻工艺,并且提高了图案化的鳍的质量。
在图2B中,在Si沟道结构20与绝缘载体10之间形成凹入部22。可以通过任何合适的蚀刻步骤来形成这种凹入部22。例如,可以钻蚀氧化物载体10。备选地,沟道结构20可以包括Si/SiGe堆叠,其中例如通过湿法蚀刻选择性地去除SiGe层。这样的蚀刻步骤是众所周知的,例如参见E.Saarniletho等人的“Local buried oxide technology for HVtransistors integrated in CMOS”,in the proceedings of 19th InternationalSymposium on Power Semiconductor Devices and IC’s,2007.ISPSD’07,27-31May 2007,page(s)81-84,因此将不再做进一步解释。
在图2C中,将凹陷的沟道结构转化为实质上圆柱形沟道结构20’。这可以通过任何合适的工艺步骤来实现,例如由Fu-Liang Yang等人在VLSI,pp.196-197(2004)中公开的氢退火步骤,其中这种退火步骤被成功地用于形成具有实质上圆柱形形状的线。
图2D图示了穿过源极区12所见的沟道结构20’的横截面,在图2D中,在实质上圆柱形沟道结构20’上生长半导体层30。例如,半导体层30可包括Si(1-x)Gex层,优选地0<<x<<1。在该层中优选相对高的Ge含量以增强该层的量子阱行为。优选地,x在0.3-0.4范围之内。已发现该范围使得可以增强半导体层30与围绕的限制层之间的带隙分裂,而不在半导体器件中引起应变。已发现,与使用Ge的最大含量为x=0.2的平面SiGe层的现有技术方案相比,该层的圆柱形形状使得该层中可以具有更高的Ge含量而不引起应变。
可以通过外延生长步骤来形成Si(1-x)Gex层。这种层的外延生长是本领域技术人员所熟知的,仅由于简洁原因而将不做进一步解释。
半导体层30优选地应不超过10nm的厚度,以在此层中获得明显的量子限制效果。
在图2E中,生长围绕半导体层30限制层40,例如硅保护层。可以以任何适合的方式来生长限制层,例如通过外延生长步骤来生长限制层。优选地,该保护层的厚度应仅为几纳米厚,例如2-3nm,以允许在该保护层上生长高质量的氧化层并且避免形成寄生导电沟道。
在图2F中,通过传统的周围栅极堆叠来实现量子阱,传统的周围栅极堆叠包括氧化层50和栅极层60。氧化层50可以包括任何适合的材料,例如基于SiO2的氧化物或介电常数大于5的材料,即,高-k电介质。栅极层60可以包括任何适合的材料,例如多晶Si或金属栅极电极。可以以任何适合方式来完成半导体器件。例如,可以采用与制造传统体MOSFETs相类似的方式来进行源极区和漏极区的形成。
在圆柱形沟道结构20’包含Si、半导体层30包括Si(1-x)Gex且限制层40包括Si的情况下,可以实现pMOS型量子阱器件,其中圆柱形沟道结构20’用作Si(1-x)Gex量子阱的另一限制结构。
可以通过如下改变上述工艺来形成相应的nMOS型器件。可以形成SiGe沟道结构20’,然后生长围绕SiGe沟道结构20’的应变Si半导体层30。应变Si半导体层30可被SiGe限制层40覆盖,SiGe限制层40可以外延地生长或以任何其他适合的方式生长。
图3示出了本发明的半导体器件的备选实施例,其中已省略内部限制层。因此,根据本发明的该实施例,半导体层30是量子阱半导体器件的最内部结构。
可以通过如下修改图2A-F中的工艺步骤来形成如图3所示的pMOS型器件。在圆柱形Si沟道结构20’上沉积Si(1-x)Gex半导体层30之后,省略沉积限制层40的步骤,方法进行至在Si(1-x)Gex半导体层30上生长氧化层50。将中间器件外露于热预算,热预算可以在氧化步骤的过程中或在氧化步骤之后,氧化步骤迫使Ge原子从半导体层30向实质上圆柱形Si沟道结构20’迁移,从而将层20’转化为半导体层30’,并将原始半导体层30转化为限制层40。半导体层30’典型地包括高于限制层40的Ge原子浓度。要强调的是,以这种方式,可以实现具有高Ge浓度的半导体层30’而不在半导体器件中引起应变和瑕疵。
可以通过将实质上圆柱形Si沟道结构20’用作半导体层并将Si(1-x)Gex层30用作限制结构,来形成相应的nMOS型器件,在这种情况下,可以从图2A-F中描述的工艺中省略限制层40的沉积。对于这种nMOS型器件,优选地限制Si(1-x)Gex层中的Ge浓度(例如,x≤0.2),以确保可以在该层上形成高质量的栅极堆叠。Si沟道和SiGe限制层之间的能隙差异给出了该器件中的带隙未对准。纯Ge的能隙大致是硅的能隙的一半,作为粗略的估算,可以获得Si(1-x)Gex层的能隙作为对于所考虑的x摩尔分数的纯Si(即,x=1)与纯Ge(即,x=0)的绝对带隙值之间的线性内插。应意识到,为确保Si半导体沟道30与SiGe限制层40之间保持充分的带隙未对准,x应实质上大于0,例如,对于该实施例0.1≤x≤0.2。
上述量子阱的制造工艺具有的优点是,可以通过CMOS兼容工艺步骤来实现上述量子阱的制造工艺,且这些工艺步骤都是可缩放的,使得也可利用这些工艺来实现未来的亚微米器件,例如特征尺寸远远低于22nm技术特征尺寸的器件。
应注意,上述实施例说明而非限制本发明,在不脱离所附权利要求所限定的本发明的范围的前提下,本领域技术人员将能够设计出许多备选实施例。在权利要求中,括号中的任何参考标记不应被解释为限制权利要求。词语“包括”并不排除存在除了在任何权利要求或说明书全文中所列元件或步骤以外的其他元件或步骤。可以利用具有若干不同元件的硬件来实现本发明。在列举了若干装置的设备权利要求中,这些装置中的一些可以由同一项软件或硬件来实现。在互不相同的从属权利要求中阐述特定措施并不表示不能有利地使用这些措施的组合。
Claims (14)
1.一种制造半导体器件的方法,包括以下步骤:
提供绝缘载体(10);
在所述载体(10)上提供在源极结构(12)和漏极结构(14)之间的沟道结构(20);
选择性地去除沟道结构(20)的一部分,从而在沟道结构(20)和载体(10)之间形成凹入部(22);
将器件外露于退火步骤,使得沟道结构(20’)获得实质上圆柱形形状;
形成围绕实质上圆柱形沟道结构(20’)的限制层(40);
生长围绕限制层(40)的氧化层(50);以及
形成围绕氧化层(50)的栅极结构(60)。
2.根据权利要求1所述的方法,还包括步骤:在形成限制层(40)之前,生长围绕实质上圆柱形沟道结构(20’)的半导体层(30),其中,限制层(40)围绕实质上圆柱形沟道结构(20’)和半导体层(30),实质上圆柱形沟道结构(20’)用作针对半导体层(30)的另一限制层。
3.根据权利要求2所述的方法,其中,半导体层(30)是外延地生长的。
4.根据权利要求1、2或3所述的方法,其中,沟道结构(20)具有方形横截面。
5.根据权利要求1至4中任一项权利要求所述的方法,其中,退火步骤包括氢退火步骤。
6.根据权利要求1所述的方法,其中,沟道结构(20)是硅沟道结构,形成限制层(40)的步骤包括:
生长围绕实质上圆柱形沟道结构(20’)的硅/锗SiGe层;以及
在预定温度下生长围绕SiGe层的氧化层(50),所述预定温度便于Ge原子从SiGe层向实质上圆柱形沟道结构(20’)迁移,从而将SiGe层转化为限制层(40)。
7.根据权利要求1所述的方法,其中,沟道结构(20)是应变硅沟道结构,形成限制层(40)包括外延地生长SiGe层。
8.根据权利要求2所述的方法,其中:
沟道结构(20)是硅沟道结构;
生长半导体层(30)包括外延地生长SiGe层;以及
形成限制层(40)包括外延地生长围绕SiGe层的硅层。
9.根据权利要求2所述的方法,其中:
沟道结构(20)是SiGe沟道结构;
生长半导体层(30)包括生长应变硅层;以及
形成限制层(40)包括外延地生长围绕应变硅层的SiGe层。
10.一种在绝缘载体上的半导体器件,所述器件包括源极区(12)、漏极区(14)以及在源极区和漏极区之间的沟道结构,所述沟道结构包括:
实质上圆柱形的核心结构(20,30),该核心结构包括半导体材料(30);
围绕核心结构(20,30)的限制层(40);
围绕限制层(40)的氧化层(50);和
围绕氧化层的栅极结构。
11.根据权利要求10所述的半导体器件,其中,核心结构(20,30)包括由半导体材料(30)层围绕的另一限制结构(20)。
12.根据权利要求10或11所述的半导体器件,其中,半导体材料(30)是硅/锗,限制结构(20,40)包括硅。
13.根据权利要求10或11所述的半导体器件,其中,半导体材料(30)是应变硅,限制结构(20,40)包括硅/锗。
14.一种集成电路,包括多个如权利要求10至13中任一项权利要求所述的半导体器件。
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- 2009-02-17 WO PCT/IB2009/050641 patent/WO2009107031A1/en active Application Filing
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CN102983165A (zh) * | 2011-09-06 | 2013-03-20 | 台湾积体电路制造股份有限公司 | 控制沟道厚度的FinFET设计 |
CN102983165B (zh) * | 2011-09-06 | 2015-06-10 | 台湾积体电路制造股份有限公司 | 控制沟道厚度的FinFET设计 |
US9318322B2 (en) | 2011-09-06 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET design controlling channel thickness |
CN103915316A (zh) * | 2013-01-09 | 2014-07-09 | 中国科学院微电子研究所 | 堆叠纳米线制造方法 |
CN104253048A (zh) * | 2013-06-28 | 2014-12-31 | 中国科学院微电子研究所 | 堆叠纳米线制造方法 |
CN104253048B (zh) * | 2013-06-28 | 2019-03-15 | 中国科学院微电子研究所 | 堆叠纳米线制造方法 |
CN105280689A (zh) * | 2014-07-02 | 2016-01-27 | 台湾积体电路制造股份有限公司 | 半导体器件及形成方法 |
CN105470303A (zh) * | 2014-09-30 | 2016-04-06 | 台湾积体电路制造股份有限公司 | 半导体器件及其沟道结构 |
Also Published As
Publication number | Publication date |
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US20110018065A1 (en) | 2011-01-27 |
WO2009107031A1 (en) | 2009-09-03 |
EP2257974A1 (en) | 2010-12-08 |
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