TW521373B - Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device Download PDF

Info

Publication number
TW521373B
TW521373B TW089114753A TW89114753A TW521373B TW 521373 B TW521373 B TW 521373B TW 089114753 A TW089114753 A TW 089114753A TW 89114753 A TW89114753 A TW 89114753A TW 521373 B TW521373 B TW 521373B
Authority
TW
Taiwan
Prior art keywords
manufacturing
integrated circuit
semiconductor integrated
film
scope
Prior art date
Application number
TW089114753A
Other languages
English (en)
Chinese (zh)
Inventor
Junji Noguchi
Naofumi Ohashi
Kenichi Takeda
Tatsuyuki Saito
Hiruzu Yamaguchi
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW521373B publication Critical patent/TW521373B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68792—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the construction of the shaft
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW089114753A 1999-08-10 2000-07-24 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device TW521373B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22687699A JP4554011B2 (ja) 1999-08-10 1999-08-10 半導体集積回路装置の製造方法

Publications (1)

Publication Number Publication Date
TW521373B true TW521373B (en) 2003-02-21

Family

ID=16851969

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089114753A TW521373B (en) 1999-08-10 2000-07-24 Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device

Country Status (4)

Country Link
US (11) US20020119651A1 (enExample)
JP (1) JP4554011B2 (enExample)
KR (1) KR100746543B1 (enExample)
TW (1) TW521373B (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424498B (zh) * 2006-03-31 2014-01-21 Applied Materials Inc 用以改良介電薄膜之階梯覆蓋與圖案負載的方法
TWI506697B (zh) * 2010-10-20 2015-11-01 Siltronic Ag 由單晶矽構成的未經塗覆的半導體晶圓
CN111593323A (zh) * 2019-02-21 2020-08-28 株式会社国际电气 半导体器件的制造方法、衬底处理装置及记录介质

Families Citing this family (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3645129B2 (ja) * 1999-06-25 2005-05-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP3805588B2 (ja) * 1999-12-27 2006-08-02 株式会社日立製作所 半導体装置の製造方法
JP2001223269A (ja) * 2000-02-10 2001-08-17 Nec Corp 半導体装置およびその製造方法
WO2001082367A1 (fr) * 2000-04-20 2001-11-01 Hitachi, Ltd. Circuit integre et procede de fabrication
JP2002110679A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
TW462085B (en) * 2000-10-26 2001-11-01 United Microelectronics Corp Planarization of organic silicon low dielectric constant material by chemical mechanical polishing
JP3901094B2 (ja) * 2001-03-16 2007-04-04 信越半導体株式会社 シリコンウエーハの保管用水及び保管方法
US6787462B2 (en) 2001-03-28 2004-09-07 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having buried metal wiring
KR100750922B1 (ko) * 2001-04-13 2007-08-22 삼성전자주식회사 배선 및 그 제조 방법과 그 배선을 포함하는 박막트랜지스터 기판 및 그 제조 방법
JP4803625B2 (ja) * 2001-09-04 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6949411B1 (en) * 2001-12-27 2005-09-27 Lam Research Corporation Method for post-etch and strip residue removal on coral films
US20030134499A1 (en) 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US6518184B1 (en) * 2002-01-18 2003-02-11 Intel Corporation Enhancement of an interconnect
JP3734447B2 (ja) * 2002-01-18 2006-01-11 富士通株式会社 半導体装置の製造方法および半導体装置の製造装置
US6764952B1 (en) * 2002-03-13 2004-07-20 Novellus Systems, Inc. Systems and methods to retard copper diffusion and improve film adhesion for a dielectric barrier on copper
JPWO2003079429A1 (ja) * 2002-03-15 2005-07-21 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3989763B2 (ja) * 2002-04-15 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
JP2003318151A (ja) 2002-04-19 2003-11-07 Nec Electronics Corp 半導体装置の製造方法
TWI288443B (en) 2002-05-17 2007-10-11 Semiconductor Energy Lab SiN film, semiconductor device, and the manufacturing method thereof
US6909196B2 (en) * 2002-06-21 2005-06-21 Micron Technology, Inc. Method and structures for reduced parasitic capacitance in integrated circuit metallizations
JP4087172B2 (ja) * 2002-07-11 2008-05-21 セイコーインスツル株式会社 半導体装置の製造方法
US7582260B2 (en) * 2002-07-18 2009-09-01 Montana State University Zwitterionic dyes for labeling in proteomic and other biological analyses
JP3974470B2 (ja) * 2002-07-22 2007-09-12 株式会社東芝 半導体装置
CN100352036C (zh) 2002-10-17 2007-11-28 株式会社瑞萨科技 半导体器件及其制造方法
JP2004172576A (ja) * 2002-10-30 2004-06-17 Sony Corp エッチング液、エッチング方法および半導体装置の製造方法
US6790777B2 (en) 2002-11-06 2004-09-14 Texas Instruments Incorporated Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device
DE10257682A1 (de) * 2002-12-10 2004-07-08 Infineon Technologies Ag Halbleiterschaltungsanordnung
JP2004304021A (ja) * 2003-03-31 2004-10-28 Ebara Corp 半導体装置の製造方法及び製造装置
JP2004273523A (ja) * 2003-03-05 2004-09-30 Renesas Technology Corp 配線接続構造
JP2004288696A (ja) * 2003-03-19 2004-10-14 Fujitsu Ltd 半導体装置の製造方法
JP4454242B2 (ja) 2003-03-25 2010-04-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2004356178A (ja) * 2003-05-27 2004-12-16 Oki Electric Ind Co Ltd エッチング方法、及び半導体装置の製造方法
US20040266185A1 (en) * 2003-06-30 2004-12-30 Texas Instruments Incorporated Method for reducing integrated circuit defects
US20050048768A1 (en) * 2003-08-26 2005-03-03 Hiroaki Inoue Apparatus and method for forming interconnects
CN100499030C (zh) * 2003-12-04 2009-06-10 东京毅力科创株式会社 半导体基板导电层表面的净化方法
JP2005183814A (ja) 2003-12-22 2005-07-07 Fujitsu Ltd 半導体装置の製造方法
JP4065855B2 (ja) * 2004-01-21 2008-03-26 株式会社日立製作所 生体および化学試料検査装置
US7700477B2 (en) * 2004-02-24 2010-04-20 Panasonic Corporation Method for fabricating semiconductor device
SG157226A1 (en) * 2004-02-24 2009-12-29 Taiwan Semiconductor Mfg A method for improving time dependent dielectric breakdown lifetimes
KR100519801B1 (ko) * 2004-04-26 2005-10-10 삼성전자주식회사 스트레스 완충 스페이서에 의해 둘러싸여진 노드 콘택플러그를 갖는 반도체소자들 및 그 제조방법들
US7829152B2 (en) * 2006-10-05 2010-11-09 Lam Research Corporation Electroless plating method and apparatus
JP4854938B2 (ja) * 2004-07-06 2012-01-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7138717B2 (en) 2004-12-01 2006-11-21 International Business Machines Corporation HDP-based ILD capping layer
JP2006179599A (ja) * 2004-12-21 2006-07-06 Toshiba Corp 半導体装置およびその製造方法
US7442114B2 (en) * 2004-12-23 2008-10-28 Lam Research Corporation Methods for silicon electrode assembly etch rate and etch uniformity recovery
KR100640525B1 (ko) * 2004-12-29 2006-10-31 동부일렉트로닉스 주식회사 반도체 소자의 금속 라인 형성 방법
KR100628225B1 (ko) * 2004-12-29 2006-09-26 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
JP4516447B2 (ja) 2005-02-24 2010-08-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7368383B2 (en) * 2005-05-24 2008-05-06 Taiwan Semiconductor Manufacturing Co., Ltd. Hillock reduction in copper films
US7414275B2 (en) * 2005-06-24 2008-08-19 International Business Machines Corporation Multi-level interconnections for an integrated circuit chip
DE102005035740A1 (de) * 2005-07-29 2007-02-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer isolierenden Barrierenschicht für eine Kupfermetallisierungsschicht
JP4548280B2 (ja) * 2005-08-31 2010-09-22 ソニー株式会社 半導体装置の製造方法
US8039049B2 (en) * 2005-09-30 2011-10-18 Tokyo Electron Limited Treatment of low dielectric constant films using a batch processing system
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
DE102005057057B4 (de) * 2005-11-30 2017-01-05 Advanced Micro Devices, Inc. Verfahren zur Herstellung einer isolierenden Deckschicht für eine Kupfermetallisierungsschicht unter Anwendung einer Silanreaktion
JP4637733B2 (ja) * 2005-11-30 2011-02-23 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7338826B2 (en) * 2005-12-09 2008-03-04 The United States Of America As Represented By The Secretary Of The Navy Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs
US7863183B2 (en) 2006-01-18 2011-01-04 International Business Machines Corporation Method for fabricating last level copper-to-C4 connection with interfacial cap structure
JP4535505B2 (ja) * 2006-02-10 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20070218214A1 (en) * 2006-03-14 2007-09-20 Kuo-Chih Lai Method of improving adhesion property of dielectric layer and interconnect process
US8193087B2 (en) * 2006-05-18 2012-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Process for improving copper line cap formation
JP2007005840A (ja) * 2006-10-16 2007-01-11 Renesas Technology Corp 半導体集積回路装置の製造方法
US7720562B2 (en) * 2006-11-08 2010-05-18 Ebara Corporation Polishing method and polishing apparatus
US7750470B2 (en) * 2007-02-08 2010-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement
JP2008218921A (ja) * 2007-03-07 2008-09-18 Nec Electronics Corp 位置ずれ量の測定用パターンおよび測定方法、ならびに半導体装置
JP4411331B2 (ja) * 2007-03-19 2010-02-10 信越化学工業株式会社 磁気記録媒体用シリコン基板およびその製造方法
JP2009204393A (ja) 2008-02-27 2009-09-10 Renesas Technology Corp プローブカード、プローブカードの製造方法、半導体検査装置および半導体装置の製造方法
US8334204B2 (en) 2008-07-24 2012-12-18 Tokyo Electron Limited Semiconductor device and manufacturing method therefor
US8105937B2 (en) * 2008-08-13 2012-01-31 International Business Machines Corporation Conformal adhesion promoter liner for metal interconnects
JP2010098195A (ja) * 2008-10-17 2010-04-30 Hitachi Cable Ltd 配線構造及び配線構造の製造方法
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
JP5548396B2 (ja) * 2009-06-12 2014-07-16 三菱マテリアル株式会社 薄膜トランジスタ用配線層構造及びその製造方法
KR101559958B1 (ko) * 2009-12-18 2015-10-13 삼성전자주식회사 3차원 반도체 장치의 제조 방법 및 이에 따라 제조된 3차원 반도체 장치
KR102014876B1 (ko) * 2011-07-08 2019-08-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US8525339B2 (en) 2011-07-27 2013-09-03 International Business Machines Corporation Hybrid copper interconnect structure and method of fabricating same
JP5387627B2 (ja) * 2011-07-28 2014-01-15 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2014534615A (ja) * 2011-09-26 2014-12-18 インテグリス・インコーポレーテッド Ｃｍｐ後クリーニング装置および方法
JP2013105753A (ja) * 2011-11-10 2013-05-30 Toshiba Corp 半導体装置の製造方法
US9147584B2 (en) * 2011-11-16 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Rotating curing
JP5870833B2 (ja) * 2012-04-24 2016-03-01 富士通セミコンダクター株式会社 半導体装置の製造方法
US8841208B2 (en) 2012-07-18 2014-09-23 International Business Machines Corporation Method of forming vertical electronic fuse interconnect structures including a conductive cap
JP2014027012A (ja) * 2012-07-24 2014-02-06 Toshiba Corp 半導体装置の製造方法および半導体装置の製造装置
WO2014026287A1 (en) * 2012-08-14 2014-02-20 Powerdisc Development Corporation Ltd. Fuel cell components, stacks and modular fuel cell systems
US9312203B2 (en) 2013-01-02 2016-04-12 Globalfoundries Inc. Dual damascene structure with liner
US8753975B1 (en) 2013-02-01 2014-06-17 Globalfoundries Inc. Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device
US8859419B2 (en) 2013-02-01 2014-10-14 Globalfoundries Inc. Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
JP2016149486A (ja) * 2015-02-13 2016-08-18 東京エレクトロン株式会社 絶縁膜の成膜方法及び半導体デバイスの製造方法
US10510688B2 (en) * 2015-10-26 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Via rail solution for high power electromigration
CN107026113B (zh) * 2016-02-02 2020-03-31 中芯国际集成电路制造(上海)有限公司 半导体装置的制造方法和系统
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US9824893B1 (en) 2016-06-28 2017-11-21 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
KR102722138B1 (ko) 2017-02-13 2024-10-24 램 리써치 코포레이션 에어 갭들을 생성하는 방법
US10546748B2 (en) 2017-02-17 2020-01-28 Lam Research Corporation Tin oxide films in semiconductor device manufacturing
CN111771264A (zh) 2018-01-30 2020-10-13 朗姆研究公司 在图案化中的氧化锡心轴
CN111886689A (zh) 2018-03-19 2020-11-03 朗姆研究公司 无倒角通孔集成方案
KR20250008974A (ko) 2019-06-27 2025-01-16 램 리써치 코포레이션 교번하는 에칭 및 패시베이션 프로세스
US11089673B2 (en) * 2019-07-19 2021-08-10 Raytheon Company Wall for isolation enhancement
KR102795747B1 (ko) * 2021-02-15 2025-04-16 삼성전자주식회사 반도체 소자 및 이의 제조 방법

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3837929A (en) * 1970-08-28 1974-09-24 Olin Corp Method of producing tarnish resistant copper and copper alloys and products thereof
DE3782904T2 (de) * 1986-09-17 1993-04-08 Fujitsu Ltd Verfahren zur ausbildung einer kupfer enthaltenden metallisierungsschicht auf der oberflaeche eines halbleiterbauelementes.
US5130274A (en) 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
JPH04354133A (ja) * 1991-05-31 1992-12-08 Sony Corp 銅配線の形成方法
JPH0547735A (ja) 1991-08-20 1993-02-26 Tadahiro Omi 洗浄装置
US6146135A (en) * 1991-08-19 2000-11-14 Tadahiro Ohmi Oxide film forming method
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
JP3072807B2 (ja) 1992-07-15 2000-08-07 日本電信電話株式会社 半導体装置の製造方法
JP3156886B2 (ja) 1993-01-26 2001-04-16 日本電信電話株式会社 半導体装置の製造方法
JP3103241B2 (ja) 1993-03-26 2000-10-30 川崎製鉄株式会社 半導体装置の製造方法
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5395801A (en) * 1993-09-29 1995-03-07 Micron Semiconductor, Inc. Chemical-mechanical polishing processes of planarizing insulating layers
JP3326642B2 (ja) 1993-11-09 2002-09-24 ソニー株式会社 基板の研磨後処理方法およびこれに用いる研磨装置
US5447887A (en) * 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
US5837929A (en) * 1994-07-05 1998-11-17 Mantron, Inc. Microelectronic thermoelectric device and systems incorporating such device
JP3397501B2 (ja) 1994-07-12 2003-04-14 株式会社東芝 研磨剤および研磨方法
JP2701751B2 (ja) * 1994-08-30 1998-01-21 日本電気株式会社 半導体装置の製造方法
JPH0982798A (ja) 1995-09-12 1997-03-28 Toshiba Corp 半導体装置およびその製造方法
US5744376A (en) * 1996-04-08 1998-04-28 Chartered Semiconductor Manufacturing Pte, Ltd Method of manufacturing copper interconnect with top barrier layer
JP3282496B2 (ja) 1996-05-17 2002-05-13 松下電器産業株式会社 半導体装置の製造方法
US5814557A (en) * 1996-05-20 1998-09-29 Motorola, Inc. Method of forming an interconnect structure
US5677244A (en) * 1996-05-20 1997-10-14 Motorola, Inc. Method of alloying an interconnect structure with copper
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
US5875507A (en) 1996-07-15 1999-03-02 Oliver Design, Inc. Wafer cleaning apparatus
WO1998004646A1 (en) 1996-07-25 1998-02-05 Ekc Technology, Inc. Chemical mechanical polishing composition and process
JPH1056014A (ja) 1996-08-12 1998-02-24 Sony Corp 基板処理方法
US5932486A (en) 1996-08-16 1999-08-03 Rodel, Inc. Apparatus and methods for recirculating chemical-mechanical polishing of semiconductor wafers
US5972792A (en) 1996-10-18 1999-10-26 Micron Technology, Inc. Method for chemical-mechanical planarization of a substrate on a fixed-abrasive polishing pad
US5818110A (en) * 1996-11-22 1998-10-06 International Business Machines Corporation Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same
JP3150095B2 (ja) 1996-12-12 2001-03-26 日本電気株式会社 多層配線構造の製造方法
JP3160545B2 (ja) 1997-01-28 2001-04-25 松下電器産業株式会社 埋め込み配線の形成方法
US6048789A (en) * 1997-02-27 2000-04-11 Vlsi Technology, Inc. IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JPH1116912A (ja) * 1997-06-25 1999-01-22 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置の製造装置
JP3463979B2 (ja) * 1997-07-08 2003-11-05 富士通株式会社 半導体装置の製造方法
US6171957B1 (en) * 1997-07-16 2001-01-09 Mitsubishi Denki Kabushiki Kaisha Manufacturing method of semiconductor device having high pressure reflow process
US6068879A (en) * 1997-08-26 2000-05-30 Lsi Logic Corporation Use of corrosion inhibiting compounds to inhibit corrosion of metal plugs in chemical-mechanical polishing
US6043153A (en) * 1997-09-25 2000-03-28 Advanced Micro Devices, Inc. Method for reducing electromigration in a copper interconnect
JP3371775B2 (ja) * 1997-10-31 2003-01-27 株式会社日立製作所 研磨方法
US6153043A (en) * 1998-02-06 2000-11-28 International Business Machines Corporation Elimination of photo-induced electrochemical dissolution in chemical mechanical polishing
JPH11251317A (ja) 1998-03-04 1999-09-17 Hitachi Ltd 半導体装置の製造方法および製造装置
US6174810B1 (en) * 1998-04-06 2001-01-16 Motorola, Inc. Copper interconnect structure and method of formation
US6016000A (en) * 1998-04-22 2000-01-18 Cvc, Inc. Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics
US6181012B1 (en) * 1998-04-27 2001-01-30 International Business Machines Corporation Copper interconnection structure incorporating a metal seed layer
JP2000012543A (ja) 1998-06-23 2000-01-14 Hitachi Ltd 半導体集積回路装置の製造方法
US6165894A (en) * 1998-07-09 2000-12-26 Advanced Micro Devices, Inc. Method of reliably capping copper interconnects
US6211084B1 (en) * 1998-07-09 2001-04-03 Advanced Micro Devices, Inc. Method of forming reliable copper interconnects
JP2000040679A (ja) * 1998-07-24 2000-02-08 Hitachi Ltd 半導体集積回路装置の製造方法
JP3248492B2 (ja) * 1998-08-14 2002-01-21 日本電気株式会社 半導体装置及びその製造方法
JP4095731B2 (ja) * 1998-11-09 2008-06-04 株式会社ルネサステクノロジ 半導体装置の製造方法及び半導体装置
US6355571B1 (en) * 1998-11-17 2002-03-12 Applied Materials, Inc. Method and apparatus for reducing copper oxidation and contamination in a semiconductor device
US6515343B1 (en) * 1998-11-19 2003-02-04 Quicklogic Corporation Metal-to-metal antifuse with non-conductive diffusion barrier
US6083840A (en) * 1998-11-25 2000-07-04 Arch Specialty Chemicals, Inc. Slurry compositions and method for the chemical-mechanical polishing of copper and copper alloys
US6596637B1 (en) * 1998-12-07 2003-07-22 Advanced Micro Devices, Inc. Chemically preventing Cu dendrite formation and growth by immersion
US6242349B1 (en) * 1998-12-09 2001-06-05 Advanced Micro Devices, Inc. Method of forming copper/copper alloy interconnection with reduced electromigration
US6153523A (en) * 1998-12-09 2000-11-28 Advanced Micro Devices, Inc. Method of forming high density capping layers for copper interconnects with improved adhesion
JP2000183000A (ja) 1998-12-14 2000-06-30 Fujitsu Ltd 半導体装置の製造方法、製造装置及び検査装置
US6271595B1 (en) * 1999-01-14 2001-08-07 International Business Machines Corporation Method for improving adhesion to copper
JP3974284B2 (ja) * 1999-03-18 2007-09-12 株式会社東芝 半導体装置の製造方法
JP2000277612A (ja) 1999-03-29 2000-10-06 Nec Corp 半導体装置の製造方法
US20020000665A1 (en) * 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
JP4083342B2 (ja) 1999-04-09 2008-04-30 株式会社トクヤマ 研磨方法
JP2000306873A (ja) 1999-04-20 2000-11-02 Tokuyama Corp 研磨方法
JP2000315666A (ja) * 1999-04-28 2000-11-14 Hitachi Ltd 半導体集積回路装置の製造方法
JP3099002B1 (ja) 1999-06-25 2000-10-16 茂徳科技股▲ふん▼有限公司 ２段階化学機械研磨方法
US6159857A (en) * 1999-07-08 2000-12-12 Taiwan Semiconductor Manufacturing Company Robust post Cu-CMP IMD process
JP4156137B2 (ja) 1999-07-19 2008-09-24 株式会社トクヤマ 金属膜用研磨剤
US6521532B1 (en) * 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects
US6207552B1 (en) * 2000-02-01 2001-03-27 Advanced Micro Devices, Inc. Forming and filling a recess in interconnect for encapsulation to minimize electromigration
JP2001291720A (ja) * 2000-04-05 2001-10-19 Hitachi Ltd 半導体集積回路装置および半導体集積回路装置の製造方法
JP2002110679A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP3668694B2 (ja) 2001-03-19 2005-07-06 株式会社日立製作所 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424498B (zh) * 2006-03-31 2014-01-21 Applied Materials Inc 用以改良介電薄膜之階梯覆蓋與圖案負載的方法
TWI506697B (zh) * 2010-10-20 2015-11-01 Siltronic Ag 由單晶矽構成的未經塗覆的半導體晶圓
CN111593323A (zh) * 2019-02-21 2020-08-28 株式会社国际电气 半导体器件的制造方法、衬底处理装置及记录介质
CN111593323B (zh) * 2019-02-21 2023-12-01 株式会社国际电气 半导体器件的制造方法、衬底处理装置及记录介质

Also Published As

Publication number Publication date
KR100746543B1 (ko) 2007-08-06
US20080138979A1 (en) 2008-06-12
US20030001277A1 (en) 2003-01-02
US20030045086A1 (en) 2003-03-06
KR20010030070A (ko) 2001-04-16
US20030017692A1 (en) 2003-01-23
US20020113271A1 (en) 2002-08-22
US6797606B2 (en) 2004-09-28
JP4554011B2 (ja) 2010-09-29
US6797609B2 (en) 2004-09-28
US6864169B2 (en) 2005-03-08
US6849535B2 (en) 2005-02-01
US6716749B2 (en) 2004-04-06
US6815330B2 (en) 2004-11-09
US20020127842A1 (en) 2002-09-12
US20020142576A1 (en) 2002-10-03
JP2001053076A (ja) 2001-02-23
US20020127843A1 (en) 2002-09-12
US20030001183A1 (en) 2003-01-02
US20030001280A1 (en) 2003-01-02
US20020119651A1 (en) 2002-08-29
US6756679B2 (en) 2004-06-29

Similar Documents

Publication Publication Date Title
TW521373B (en) Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
TW557575B (en) Fabrication method of semiconductor integrated circuit device
KR100698987B1 (ko) 반도체 집적 회로 장치의 제조 방법
TWI291760B (en) Method for producing semiconductor device and semiconductor device
TWI414041B (zh) Semiconductor device manufacturing method
JP2003051481A (ja) 半導体集積回路装置の製造方法
JP2001185515A (ja) 研磨方法、配線形成方法、半導体装置の製造方法及び半導体集積回路装置
JP5022900B2 (ja) 半導体集積回路装置の製造方法
JP2008141204A (ja) 半導体集積回路装置の製造方法
KR100746895B1 (ko) 반도체 집적 회로 장치의 제조 방법
KR101757037B1 (ko) 구리 배선을 가진 기판을 구비하는 반도체 장치의 제조 방법
JP2007005840A (ja) 半導体集積回路装置の製造方法
JP2005019802A (ja) 半導体装置の製造方法およびウェーハ構造体
TW550736B (en) Method of preventing copper diffusion through a wafer backside into the wafer
JP2012060148A (ja) 半導体集積回路装置の製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent