US20020142576A1 - Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device Download PDF

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US20020142576A1
US20020142576A1 US10/140,111 US14011102A US2002142576A1 US 20020142576 A1 US20020142576 A1 US 20020142576A1 US 14011102 A US14011102 A US 14011102A US 2002142576 A1 US2002142576 A1 US 2002142576A1
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Prior art keywords
film
interconnection
copper
gas
insulating film
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Abandoned
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US10/140,111
Inventor
Junji Noguchi
Naofumi Ohashi
Kenichi Takeda
Tatsuyuki Saito
Hizuru Yamaguchi
Nobuo Owada
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Renesas Technology Corp
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Hitachi Ltd
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Priority to JP11-226876 priority Critical
Priority to JP22687699A priority patent/JP4554011B2/en
Priority to US62153600A priority
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to US10/140,111 priority patent/US20020142576A1/en
Publication of US20020142576A1 publication Critical patent/US20020142576A1/en
Assigned to RENESAS TECHNOLOGY CORPORATION reassignment RENESAS TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
Application status is Abandoned legal-status Critical

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Abstract

After formation of Cu interconnections 46 a to 46 e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46 a to 46 e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Description

    BACKGROUND OF THE INVENTION
  • This invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, in particular, a technique effective when adapted for the so-called damascene method wherein an interconnection having copper as a main conductive layer is formed by cutting a groove in an insulating film, forming a copper film to be embedded in the groove and polishing by CMP (Chemical Mechanical Polishing). [0001]
  • Attendant on the recent tendency to miniaturizing an interconnection in a semiconductor integrated circuit device, a deterioration in the performance of the semiconductor integrated circuit device resulting from an increase in interconnection resistance or interconnection delay has come to be a problem. It has led to a serious problem particularly in a high-performance logic LSI as a factor for disturbing its performance. As described on pages 15 to 21 in the Preprint of 1993 VMIC (VLSI Multilevel Interconnection Conference), a method for forming an interconnection pattern in an interconnection groove by embedding a metal, which has copper (Cu) as a main conductive layer, in an interconnection groove formed in an insulating film and then removing the unnecessary portion of the metal outside the interconnection groove by chemical mechanical polishing (CMP) is now under investigation. [0002]
  • Described in Japanese Patent Application Laid-Open No. Hei 9-306915 is a technique which comprises forming an interconnection groove in a silicon oxide film on a semiconductor substrate, depositing a titanium nitride film and copper film by sputtering, filling the groove with copper by reflow, removing the copper film outside the groove by CMP and then heat treating in a hydrogen atmosphere. According to it, defects in the copper interconnection can be reduced by this technique. [0003]
  • Described in Japanese Patent Application Laid-Open No. Hei 10-56014 is a technique comprising polishing a material, which has a titanium nitride film and tungsten film and is formed over a semiconductor substrate, by CMP and subjecting the polished surface to plasma treatment with a halogen-based mixed gas. According to it, no interconnection short-circuit occurs even if micro scratches are formed by CMP. [0004]
  • Described in Japanese Patent Application Laid-Open No. Hei 10-56014 is a technique comprising forming a photosensitive SOG film over a base on which an interconnection is to be formed, forming an interconnection groove in the SOG film, forming a titanium nitride film, a copper film and a copper titanium alloy film, leaving the films only inside of the interconnection groove by CMP, and heat treating in an ammonia atmosphere to form a titanium nitride film over the surface layer of the copper titanium alloy film. [0005]
  • Described in Japanese Patent Application Laid-Open No. Hei 11-16912 is a technique of subjecting the surface of a through-hole or the like of a copper interconnection formed by the damascene method to plasma treatment in an atmosphere such as ammonia. [0006]
  • SUMMARY OF THE INVENTION
  • The present inventors have found the below-described problems in the interconnection forming technique, so called damascene method, which comprises forming the above-described interconnection groove, forming a metal film (ex. copper film) to be embedded in the groove and removing the copper film outside the interconnection groove by CMP. [0007]
  • When application of the above-described technique to high-performance logic LSI is considered, a reduction in interconnection resistance is one of the most important problems to be technically investigated. The present inventors therefore are now investigating copper as a metal constituting the interconnection. Copper tends to be diffused in a silicon oxide film, which is an insulating film, compared with another metal (ex. aluminum or tungsten) so that a barrier film covering the interconnection must be studied. As the barrier film in the interconnection groove, a titanium nitride film is studied. As a film (cap film) covering the upper portion of the interconnection, a silicon nitride film is studied. Reliability improvement of the interconnection by covering copper with the titanium nitride film lying on the interconnection groove and the silicon nitride film for capping the upper portion of the interconnection, thereby blocking diffusion of copper into the intrastratum insulating film (silicon oxide film) is under investigation. [0008]
  • When copper is employed as an interconnection material, TDDB (Time Dependence on Dielectric Breakdown) is markedly short compared with another metal material (ex. aluminum or tungsten). The TDDB test is one of acceleration test methods for evaluating the dielectric breakdown resistance between interconnections. According to it, time dependence on dielectric breakdown (lifetime) under the ordinary using condition can be estimated from the time dependence on dielectric breakdown under a higher electric field at a higher predetermined temperature than the ordinary using condition. The TDDB is a lifetime estimated from this TDDB test. The TDDB will be described later in detail. [0009]
  • FIG. 55 is a graph illustrating the measured data of TDDB characteristics of a copper interconnection, an aluminum interconnection and a tungsten interconnection. The TDDB and electric field strength are plotted along the ordinate and abscissa, respectively. When the characteristics (data A) of the aluminum interconnection and those (data B) of the tungsten interconnection are extrapolated, the TDDB at an electric field strength of 0.2 MV/cm (ordinary using condition) easily exceeds 3×10[0010] 8 sec (10 years), which is a development target of the present inventors. When the characteristics (data C) of the copper interconnection is extrapolated, on the other hand, there is almost no margin for the development target of 10 years. The aluminum interconnection is formed by film deposition and patterning by photolithography, while the tungsten interconnection is formed by the damascene method similar to the copper interconnection. The copper interconnection and tungsten interconnection differ only in the material. There is no difference in their structures. A marked difference in TDDB characteristics between these two materials suggests that it results from the difference in the interconnection material. Here, the TDDB characteristics are measured at 140° C.
  • A deterioration in the TDDB characteristics is generally presumed to result from a reduction in the withstand voltage between interconnections due to diffusion of copper, used as an interconnection material, into its surroundings. According to the investigation by the present inventors, however, it is mainly caused by drifting and diffusion of not copper atoms but ionized copper fed from copper oxide or copper silicide at an electric potential between interconnections. Copper is presumed to be mainly diffused from the interface between an insulating film having a copper interconnection formed thereon and a cap film. Described specifically, copper ions are formed from a copper compound such as copper oxide or copper silicide formed over the surface of the copper interconnection and then, such ionized copper drifts and is diffused along the interface between the insulating film wherein an interconnection is to be formed and a cap film by an electric field between interconnections. The copper atoms thus diffused are presumed to increase a leak current. The increase in the leak current heightens thermal stress and finally causes dielectric breakdown at a leak path, leading to the expiration of the lifetime. This mechanism will be described later in detail. [0011]
  • According to the investigation by the present inventors, formation of a multilayered interconnection layer causes a problem that there appears peeling between the lower interconnection and insulating film (cap film) formed thereover in the CMP step for forming an upper interconnection. [0012]
  • In addition, use of a silicon nitride film as a cap film on the copper interconnection is accompanied with the problem that a silicide is formed on the interface between copper and a silicon nitride film, causing an increase in the resistance of the copper interconnection. [0013]
  • An object of the present invention is to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method. [0014]
  • Another object of the present invention is to suppress the generation of peeling of a cap film from an interconnection layer. [0015]
  • A further object of the present invention is to prevent an increase in the resistance of a copper interconnection when a silicon nitride film is employed as a cap film. [0016]
  • The above-described and the other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings. [0017]
  • Among the inventions disclosed herein, representative ones will next be summarized simply. [0018]
  • In the present invention, the surface of each of an interconnection and an intrastratum insulating film (ex. silicon oxide film) in which the interconnection has been embedded is subjected to a reducing plasma after the CMP step but prior to the formation of a cap film (ex. silicon nitride film). [0019]
  • This treatment makes it possible to continuously form the interface between the interconnection and intrastratum insulating film, and the cap insulating film, leading to an improvement in the adhesion on the interface and, in turn, a marked improvement in the TDDB characteristics. [0020]
  • The summaries of the present invention will next be described. [0021]
  • In one aspect, the present invention provides a manufacturing method which comprises forming a first insulating film (ex. silicon oxide film) over a semiconductor substrate; forming a groove (interconnection groove) in the first insulating film; successively forming a first conductive film (a blocking film, for example, a titanium nitride film, for preventing diffusion of copper) and a second conductive film (copper film) to be embedded in the groove; polishing the second conductive film and first conductive film to form an interconnection in the groove; treating the surface of each of the first insulating film and interconnection to a plasma of reducing atmosphere; and then depositing a first insulating film and, over the interconnection, a second insulating film (a cap insulating film, for example, a silicon nitride film). [0022]
  • In the above-described method, as the plasma of reducing atmosphere, an ammonia (NH[0023] 3) plasma or a hydrogen (H2) plasma can be employed. In addition, a mixed gas plasma of ammonia (NH3) and a diluting gas (one or more gases selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He)) or a mixed gas plasma of hydrogen (H2) and a diluting gas (one or more gases selected from ammonia (NH3), nitrogen (N2), argon (Ar) and helium (He)) can also be used. The mixed gas contains ammonia or hydrogen in an amount of at least 5%.
  • It is possible to form a silicon oxide film as the first insulating film, a copper film as the second conductive film and a silicon nitride film as the second insulating film. It is needless to say that copper may contain alloy elements, additives and/or impurities within an extent not impairing the properties of copper as an interconnection. In the embodiment, copper having a purity as high as 4N, that is, 99.99% or higher is usually employed. [0024]
  • After the polishing step but prior to plasma treatment, the surface of each of the first insulating film and interconnection can be washed with an acid. For washing, an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH[0025] 2COOH)2(OH) (COOH)) can be employed.
  • In the polishing step, abrasive-grain-free chemical mechanical polishing can be adopted. Polishing can be conducted in three stages, that is, first polishing by abrasive-grain-free chemical mechanical polishing, second polishing by abrasive-grain-using chemical mechanical polishing, and third polishing by selective chemical mechanical polishing conducted at a 5:1 selection ratio of the first conductive film to the second conductive film. [0026]
  • In another aspect, the present invention provides a manufacturing method which comprises forming a first insulating film over a semiconductor substrate, forming a groove in the first insulating film, forming a first conductive film and a second conductive film to embed the groove therewith, polishing the second and first conductive films to form an interconnection in the groove, subjecting the surface of each of the first insulating film and interconnection to reducing treatment and nitriding treatment with a plasma, and then depositing a second insulating film over the first insulating film and interconnection. [0027]
  • In this case, an ammonia (NH[0028] 3) plasma, or a mixed gas plasma of ammonia with one or more gases selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He) can be used as the plasma.
  • In a further aspect, the present invention provides a manufacturing method which comprises forming a first insulating film having a dielectric constant lower than that of a silicon oxide film contained in a protecting film (passivation film), forming a groove or opening in the first insulating film, treating the exposed surface of the first insulating film with a plasma of reducing atmosphere, depositing a first conductive film which covers the surface including the inside wall of the groove or opening, forming a second conductive film to be embedded in the groove or opening, and removing the second conductive film and first conductive film outside the groove or opening by polishing, thereby forming a conductive member in the groove or opening. For this method, the above-described plasma of reducing atmosphere can be used. The second insulating film may be formed over the first insulating film. [0029]
  • In a still further aspect, the present invention provides a semiconductor integrated circuit device which comprises a first insulating film, an interconnection embedded in the groove of the first insulating film, and a second insulating film formed over the first insulating film and interconnection, wherein a nitride film is formed on the interface between the first insulating film and interconnection, and second insulating film. In this device, the first insulating film, interconnection and second insulating film are a silicon oxide film, copper and a silicon nitride film, respectively. The nitrogen concentration in the nitride film becomes higher from the side of the first insulating film and interconnection toward the second insulating film. [0030]
  • In a still further aspect, the present invention provides a manufacturing method which comprises forming a first insulating film over a semiconductor substrate, forming a groove in the first insulating film, depositing a first conductive film over the first insulating film, forming a second conductive film to embed the groove therewith, polishing the second conductive film and first conductive film to form an interconnection in the groove, treating the surface of each of the first insulating film and interconnection with a plasma of reducing atmosphere, and continuously depositing a second insulating film over the first insulating film and interconnection while maintaining a pressure-reduced or inactive condition without exposing the semiconductor substrate to the atmosphere. [0031]
  • The summary of the other inventions of the present application will next be described briefly in items. [0032]
  • 1. A manufacturing method of a semiconductor integrated circuit device, which comprises: [0033]
  • (a) forming a first insulating film over a semiconductor substrate and forming a groove in the first insulating film, [0034]
  • (b) depositing a first conductive film over the first insulating film and forming a second conductive film to embed the groove therewith, [0035]
  • (c) removing the second conductive film and first conductive film over the first insulating film outside the groove and forming an interconnection in the groove, [0036]
  • (d) treating the surface of each of the first insulating film and interconnection with a plasma of reducing atmosphere, and [0037]
  • (e) after completion of the plasma treating step, depositing a second insulating film over the first insulating film and interconnection. [0038]
  • 2. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is an ammonia (NH[0039] 3) plasma or hydrogen (H2) plasma.
  • 3. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is mixed gas plasma of ammonia (NH[0040] 3) and a diluting gas, and the diluting gas contains one or more gases selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He)
  • 4. A manufacturing method according to the item 3, wherein the concentration of ammonia (NH[0041] 3) is at least 5 wt. % based on the mixed gas.
  • 5. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is a mixed gas plasma of hydrogen (H[0042] 2) and a diluting gas and the diluting gas contains one or more gases selected from ammonia (NH3), nitrogen (N2), argon (Ar) and helium (He).
  • 6. A manufacturing method according to the item 5, wherein the concentration of hydrogen (H[0043] 2) is at least 5 wt. % based on the mixed gas.
  • 7. A manufacturing method according to the item 1, wherein the first insulating film is a silicon oxide film and the second conductive film is made of copper. [0044]
  • 8. A manufacturing method according to the item 7, wherein the second insulating film is a silicon nitride film. [0045]
  • 9. A manufacturing method according to the item 8, wherein the plasma of reduced atmosphere is an ammonia (NH[0046] 3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
  • 10. A manufacturing method according to the item 9, wherein the copper has a purity as high as 99.99% or greater. [0047]
  • 11. A manufacturing method according to the item 1, which further comprises washing the surface of each of the first insulating film and interconnection with an acid between the steps (c) and (d). [0048]
  • 12. A manufacturing method according to the item 11, wherein an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH[0049] 2COOH)2(OH) (COOH) is used as the acid for washing.
  • 13. A manufacturing method according to the item 12, wherein the first insulating film, the second conductive film and the second insulating film are a silicon oxide film, copper and a silicon nitride film, respectively. [0050]
  • 14. A manufacturing method according to the item 12, wherein the plasma of reduced atmosphere is an ammonia (NH[0051] 3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
  • 15. A manufacturing method according to the item 14, wherein the copper has a purity as high as 99.99% or greater. [0052]
  • 16. A manufacturing method according to the item 1, wherein abrasive-grain-free chemical mechanical polishing is employed for the polishing in the step (c). [0053]
  • 17. A manufacturing method according to the item 16, wherein the polishing in the step (c) is conducted in three stages, that is, first polishing by abrasive-grain-free chemical mechanical polishing, second polishing by abrasive-grain-using chemical mechanical polishing and third polishing by selective chemical mechanical polishing at a first conductive film:second conductive film selection ratio of at least 5. [0054]
  • 18. A manufacturing method according to the item 17, wherein the first insulating film, the second conductive film and the second insulating film are a silicon oxide film, copper and a silicon nitride film, respectively. [0055]
  • 19. A manufacturing method according to the item 18, wherein the plasma of reduced atmosphere is an ammonia (NH[0056] 3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He)
  • 20. A manufacturing method according to the item 19, which further comprises, between the steps (c) and (d), washing the surface of each of the first insulating film and interconnection with an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH[0057] 2COOH)2(OH) (COOH)
  • 21. A manufacturing method according to the item 20, wherein the copper has a purity as high as 99.99% or greater. [0058]
  • 22. A manufacturing method of a semiconductor integrated circuit device, which comprises: [0059]
  • (a) forming a first insulating film over a semiconductor substrate and forming a groove in the first insulating film, [0060]
  • (b) depositing a first conductive film over the first insulating film and forming a second conductive film to embed the groove therewith, [0061]
  • (c) removing the second conductive film and first conductive film over the first insulating film outside the groove by polishing and forming an interconnection in the groove, [0062]
  • (d) subjecting the surface of each of the first insulating film and interconnection to reducing treatment and nitriding treatment with a plasma, and [0063]
  • (e) depositing the second insulating film over the first insulating film and interconnection. [0064]
  • 23. A manufacturing method according to the item 22 wherein the plasma is an ammonia (NH[0065] 3) plasma or a mixed gas plasma thereof with a diluting gas, and the diluting gas is at least one gas selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He)
  • 24. A manufacturing method of a semiconductor integrated circuit having a first insulating film formed over a semiconductor substrate and a protecting film formed thereover for preventing the invasion of impurities, which comprises: [0066]
  • (a) forming a first insulating film having a dielectric constant lower than that of a silicon oxide film contained in the protecting film, [0067]
  • (b) forming a groove or opening in the first insulating film, [0068]
  • (c) treating the exposed surface of the first insulating film with a plasma of reducing atmosphere, [0069]
  • (d) depositing a first conductive film to cover the surface including the inside wall of the groove or opening and forming a second-conductive film to embed therewith the groove or opening, and [0070]
  • (e) removing the second conductive film and first conductive film outside the groove or opening by polishing and forming a conductive member in the groove or opening. [0071]
  • 25. A manufacturing method according to the item 24, wherein the plasma of reduced atmosphere is an ammonia (NH[0072] 3) plasma or a hydrogen (H2) plasma, or a mixed gas plasma thereof with one or more gases selected from nitrogen (N2), argon (Ar) and helium (He).
  • 26. A manufacturing method according to the item 25, wherein a second insulating film is formed over the first insulating film, a groove or opening is formed in the first and second insulating films in the step (b) and the surface of the first insulating film exposed to the inside wall of the groove or opening is treated with a plasma of reducing atmosphere. [0073]
  • 27. A semiconductor integrated circuit device having a first insulating film formed over a semiconductor substrate, an interconnection embedded in a groove of the first insulating film and a second insulating film formed over the first insulating film and interconnection, wherein a nitride film is formed on the interface between the first insulating film and interconnection, and the second insulating film. [0074]
  • 28. A semiconductor integrated circuit device according to the item 27, wherein the first insulating film, interconnection and second insulating film are a silicon oxide film, copper and silicon nitride film, respectively. [0075]
  • 29. A semiconductor integrated circuit device according to the item 28, wherein the nitrogen concentration of the nitride film becomes higher from the first insulating film and interconnection toward the second insulating film. [0076]
  • 30. A manufacturing method according to the item 1, which further comprises, after the completion of the step (d), depositing the second insulating film over the first insulating film and interconnection continuously while maintaining a reduced-pressure or inactive condition without exposing the semiconductor substrate to the atmosphere.[0077]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a manufacturing method of a semiconductor integrated circuit device according to one embodiment (Embodiment 1) of the present invention; [0078]
  • FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0079]
  • FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0080]
  • FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0081]
  • FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0082]
  • FIG. 6([0083] a) is a plan view illustrating the manufacturing method of Embodiment 1 and FIG. 6(b) is a fragmentary cross-sectional view illustrating the manufacturing method of Embodiment 1;
  • FIG. 7([0084] a) is a plan view illustrating the manufacturing method of Embodiment 1 and FIG. 7(b) is a fragmentary cross-sectional view illustrating the manufacturing method of Embodiment 1;
  • FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0085]
  • FIG. 9 is a schematic view illustrating one example of the whole constitution of a CMP apparatus used for the formation of a Cu-embedded interconnection; [0086]
  • FIG. 10 is a schematic view illustrating a part of the CMP apparatus used for the formation of a Cu-embedded interconnection; [0087]
  • FIG. 11 is a perspective view illustrating a scrub washing method of a wafer; [0088]
  • FIG. 12 is a schematic view illustrating another example of the whole constitution of a CMP apparatus used for the formation of a Cu-embedded interconnection; [0089]
  • FIG. 13 is a schematic view illustrating a further example of the whole constitution of a CMP apparatus used for the formation of a Cu-embedded interconnection; [0090]
  • FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0091]
  • FIG. 15([0092] a) is a schematic cross-sectional view of a plasma treating apparatus used for ammonia plasma treatment an deposition of a silicon nitride film and FIG. 15(b) is a plan view of the apparatus;
  • FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0093]
  • FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of Embodiment 1; [0094]
  • FIG. 18 is a flow chart illustrating the manufacturing method of the semiconductor integrated circuit device of Embodiment 1; [0095]
  • FIG. 19 is a schematic cross-sectional view illustrating the semiconductor integrated circuit device of Embodiment 1; [0096]
  • FIG. 20 is a graph illustrating TDDB; [0097]
  • FIG. 21 is a graph illustrating TDDB; [0098]
  • FIGS. [0099] 22(a) to 22(d) are graphs each illustrating XPS data;
  • FIGS. [0100] 23(a) to 23(d) are graphs each illustrating XPS data;
  • FIGS. [0101] 24(a) to 24(d) are graphs each illustrating XPS data;
  • FIGS. [0102] 25(a) to 25(d) are graphs each illustrating XPS data and (f) is a table showing a component ratio;
  • FIGS. [0103] 26(a) to 26(d) are graphs each illustrating the results of mass spectroscopy;
  • FIGS. [0104] 27(a) to 27(d) are graphs each illustrating the results of mass spectroscopy;
  • FIG. 28 is a TEM photograph of the interconnection portion of Embodiment 1; [0105]
  • FIG. 29 is TEM photograph for comparison; [0106]
  • FIG. 30 is a graph illustrating interconnection resistance; [0107]
  • FIG. 31([0108] a) is a TEM photograph of the interconnection portion without treatment, FIG. 31(b) is a TEM photograph of the interconnection portion of Embodiment 1, and FIGS. 31(c) and 31(d) are traced drawings of FIGS. 31(a) and 31(b), respectively;
  • FIGS. [0109] 32(a) to 32(c) are TEM photographs for comparison, and FIGS. 32(d), 32(e) and 32(f) are traced drawings of FIGS. 32(a), 32(b) and 32(c), respectively;
  • FIG. 33 is a graph illustrating the TDDB life; [0110]
  • FIG. 34 is a schematic view illustrating one example of the whole constitution of a CMP apparatus used for a manufacturing method of a semiconductor integrated circuit device according to Embodiment 2 of the present invention; [0111]
  • FIG. 35 is a schematic view illustrating a part of a CMP apparatus used for the formation of a Cu-embedded interconnection; [0112]
  • FIG. 36 is a schematic view of a CMP apparatus illustrating the polished condition of a Cu film; [0113]
  • FIG. 37 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of a semiconductor integrated circuit device according to Embodiment 2; [0114]
  • FIG. 38([0115] a) is a fragmentary plan view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2 and FIG. 38(b) is a fragmentary cross-sectional view of the substrate;
  • FIG. 39 is a fragmentary cross-sectional view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2; [0116]
  • FIG. 40([0117] a) is a fragmentary plan view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2 and FIG. 40(b) is a fragmentary cross-sectional view of this substrate;
  • FIG. 41 is a fragmentary cross-sectional view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2; [0118]
  • FIG. 42([0119] a) is a fragmentary plan view of the semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2 and FIG. 42(b) is a fragmentary cross-sectional view of this substrate;
  • FIG. 43 is a flow chart showing the manufacturing method of the semiconductor integrated circuit device according to Embodiment 2; [0120]
  • FIG. 44 is a graph illustrating TDDB; [0121]
  • FIG. 45 is a flow chart showing a manufacturing method of a semiconductor integrated circuit device according to Embodiment 3; [0122]
  • FIG. 46 is a graph illustrating TDDB; [0123]
  • FIG. 47 is a fragmentary cross-sectional view of a semiconductor substrate illustrating a manufacturing method of a semiconductor integrated circuit device according to Embodiment 4; [0124]
  • FIG. 48([0125] a) is a fragmentary plan view of a semiconductor substrate illustrating the manufacturing method of the semiconductor integrated circuit device according to Embodiment 4 and FIG. 48(b) is a fragmentary cross-sectional view of this substrate;
  • FIG. 49 is a fragmentar