TW495953B - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
TW495953B
TW495953B TW089122252A TW89122252A TW495953B TW 495953 B TW495953 B TW 495953B TW 089122252 A TW089122252 A TW 089122252A TW 89122252 A TW89122252 A TW 89122252A TW 495953 B TW495953 B TW 495953B
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Taiwan
Prior art keywords
semiconductor wafer
semiconductor
main surface
substrate
semiconductor device
Prior art date
Application number
TW089122252A
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English (en)
Inventor
Masachika Masuda
Toshihiko Usami
Original Assignee
Hitachi Ltd
Akita Electron Co Ltd
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Publication date
Application filed by Hitachi Ltd, Akita Electron Co Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW495953B publication Critical patent/TW495953B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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Description

495953 A7 ___ B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（1 ) 本發明係關於，半導體裝置及其製造技術，特別是關 於，應用於堆疊多片半導體晶片，以樹脂封裝成單一組件 之半導體裝置時，十分有效之技術。 作爲將快閃記憶器或D R A M ( Dynamic Random Access Memory )等之記憶L S I大容量化之對策，有各 種提案，建議將形成有此等記憶L S I之半導體晶片堆疊 ，封裝成單一組件之記憶模組構造。 舉例言之，日本國特開平4-3 0 2 1 6 4號公報揭示 一種組件構造，係在一個組件內，介由絕緣層成台階狀堆 疊同一機能，同一尺寸之多片半導體晶片，再用導線，以 電氣方式連接露出在各半導體晶片之台階狀部分之焊接區 ，與組件之內部引線，使成組件。 又在特開平1 1-2 0 4 7 2 0號公報揭示一種組件構 造，係介由熱壓接片在絕緣性基板上搭載第1半導體晶片 ，再介由熱壓接片在此第1半導體晶片上搭載外形尺寸較 第1半導體晶片小之第2半導體晶片，經由導線，以電氣 方式連接第1及第2半導體晶片之焊接區，與絕緣性基板 上之配線層，再以樹脂封裝第1及第2半導體晶片及導線 ，使成組件。 堆疊兩片以上之尺寸及焊接區配置均相同之半導體晶 片，安裝在基板上，再以導線連接各半導體晶片之焊接區 與基板之電極時，從上面看，以電氣方式連接此等半導體 晶片之電氣性質相同之共同焊接區與電極之多數導線相互 間，幾乎是重疊在一起，因此在結束導線搭接製程後實施 ------— — — — — — — : (請先閲讀背面之注t事項再填 裝i — 寫本頁) 訂· 線」 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- 495953 A7 ___ B7 五、發明說明（2 ) 之外觀檢査過程，要判定上下導線相互間有無短路十分困 難。 同時，連接電氣性質相同之共同焊接區與電極之上述 多數導線中，連接在下層之半導體晶片之焊接區之導線， 係大致上位於連接在上層之半導體晶片之焊接區之導線之 直下方，因此，如果降低連接在上層之半導體晶片之焊接 區之導線之環形高度，跟其直下方之導線之距離會縮短， 雙方便很容易短路。爲了防止發生這種事故，而提高連接 在上層之半導體晶片之焊接區之導線之環形高度時，封裝 半導體晶片與導線之樹脂會變厚，致很難將組件薄形化。 本發明之目的在提供，對堆疊多片半導體晶片以樹脂 封裝之半導體裝置，提高在其導線搭接製程後實施之外觀 檢查之可靠性之技術。 本發明之其他目的在提供，推動堆疊多片半導體晶片 以樹脂封裝之半導體裝置之小型化、薄形化之技術。 本發明之其他目的在提供，降低堆疊多片半導體晶片 以樹脂封裝之半導體裝置之製造成本之技術。 本發明之上述及其ffe目的以及新穎之特徵，可以從本 說明書之記述及附圖獲得進一步之瞭解。茲簡單說明本案 所揭示之發明中，具代表性者之槪要如下。 本發明之半導體裝置，係在基板上安裝，沿著主面之 一邊形成有多數焊接區之第1半導體晶片’在上述第1半 導體晶片之主面上堆疊，沿著主面之一邊形成有多數焊接 區之第2半導體晶片，經由導線，以電氣方式連接上述第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱1 " I n I ϋ ϋ I 1 I I I- I I n I · I I <請先閱讀背面之注意事項寫本頁) 訂· 線· 經濟部智慧財產局員工消费合作社印製 495953 A7 ___ B7 五、發明說明（3 ) 1及第2半導體晶片之上述焊接區，與上述基板上之電極 ，再以樹脂封裝上述第1及第2半導體晶片及上述導線， 上述第2半導體晶片係以，向與上述第1半導體晶片之一 邊平行之方向，及與之垂直之方向偏移之狀態，堆疊在上 述第1半導體晶片之主面上。 本發明之半導體裝置，係在基板上安裝，沿著主面之 一邊形成有多數焊接區之第1半導體晶片；沿著主面之一 邊形成有多數焊接區之第2半導體晶片，係向與上述第1 半導體晶片之一邊平行之方向，及與之垂直之方向偏移之 狀態，堆疊在上述第1半導體晶片之主面上，使上述第2 半導體晶片之一邊面對上述第1半導體晶片之一邊，且使 上述第1半導體晶片之上述焊接區露出；沿著主面之一邊 形成有多數焊接區之第3半導體晶片，係使上述第3半導 體晶片之一邊與上述第1半導體晶片之一邊沿著同一方向 ，且與上述第1半導體晶片相互朝向同一方向之狀態，堆 疊在上述第2半導體晶片之主面上；上述第1、第2及第 3半導體晶片之上述焊接區與上述基板上之電極，係分別 經由導線以電氣方式連接在一起，並用樹脂封裝上述第1 、第2及第3半導體晶片及導線。 本發明之半導體裝置之製造方法，包含有下列製程。 (a )在基板上安裝，沿著主面之一邊形成有多數焊 接區之第1半導體晶片之製程： (b )將沿著主面之一邊形成有多數焊接區之第2半 導體晶片，向與上述第1半導體晶片之一邊平行之方向， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閲 讀 背 面 之 注 項 再 填 寫 本 頁 經濟部智慧財產局員工消f合作社印製 -6 - 495953 A7 _____________ B7 五、發明說明（4 ) 及與之垂直之方向偏移之狀態，堆疊在其主面上。 (C )經由導線，以電氣方式連接形成在上述第1及 第2半導體晶片之上述多數焊接區，與形成在上述基板上 之電極之製程； (d )以樹脂封裝上述第1及第2半導體晶片及上述 導線之製程。 茲參照附圖，詳細說明本發明之實施形態如下。再者 ，在說明實施形態之所有圖式，相同之構件標示同一記號 ，省略重複之說明。 第1圖係表示本實施形態之半導體裝置之外觀之平面 圖，第2圖係此半導體裝置之長度方向（A-A線）之截面 圖，第3圖係表示此半導體裝置之基座基板之平面圖。 本實施形態之半導體裝置，係在基座基板2上安裝， 在主面形成有半導體元件之例如快閃記憶器之兩片半導體 晶片（以下簡稱爲晶片或記憶晶片）1 A、1 A，及形成 有用以控制此快閃記憶器之電路之1片半導體晶片（以下 簡稱晶片或控制用晶片）1 B，而以樹脂3封裝此等3片 晶片ΙΑ、ΙΑ、1B，同時以樹脂製之蓋体4被覆基座. 基板2上面之記憶卡M C。此記憶卡M C係例如設在數位 攝影機等之攜帶式電子機器內，供保存畫像等資料之記憶 体使用。記憶卡MC之外形尺寸之一例是，長邊3 2mm 、短邊24mm、厚度1·2mm。 安裝在上述記憶卡MC之基座基板2上之兩片記憶晶 片1 A、1 A具有相同之外形尺寸，形成同一容量之快閃 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) 先 閱 讀 背 面 之 注 項 寫 本 頁 經濟部智慧財產局員工消费合作社印製 495953 A7 ___ B7 五、發明說明（5) 記憶器。此等記億晶片1 A、1 A係以在一方之上部重疊 另一方之狀態安裝在基座基板2上。下層之記憶晶片1 A 用接合劑等接合在基座基板2之上面，上層之記憶晶片 1 A用接合劑等接合在下層之記億晶片1 A之上面。另一 方面，控制晶片1 B係安裝在記憶晶片1 A、1 A附近之 基座基板2，同樣用接合劑等接合在基座基板2之上面。 此等3片之晶片1A、1A、1B均以主面（形成元件之 面）朝上之狀態安裝在基座基板2上。 形成有快閃記憶器之兩片記憶晶片1 A、1 A之各主 面，沿其一邊成一列形成有多數焊接區B P。亦即，記憶 晶片1 A係採用，在元件形成面之周邊部形成焊接區B P ，且沿其一邊將此等焊接區B P配置成一列之單邊焊接區 方式。另一方面，在控制晶片1 B之主面係例如沿著相對 之兩長邊各形成一列焊接區.B P。 兩片記憶晶片1 A、1 A係以朝向同一方向之狀態重 疊，一方之記億晶片1 A之焊接區B P與另一方之記憶晶 片1 A之焊接區B P係靠近配置在一起。而，上層之記憶 晶片1 A係以向與下層之記憶晶片1 A之一邊平行之方向 (X方向），及與其垂直相交之方向（Y方向）偏移之狀 態堆疊，以避免其一部分與下層之記憶晶片1 A之焊接區 B P重疊。 上述記憶晶片ΙΑ、1A、1 B近旁之基座基板2上 形成有多數電極5，而經由Au (金）之導線6 ’以電氣 方式連接到各晶片ΙΑ、1A、1 B之相對應之焊接區 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公爱） · 8 · (請先閱讀背面之注意事項3寫本頁) 訂： --線- 經濟部智慧財產局員工消費合作社印製 495953 A7 __ B7 五 '發明說明（6 ) BP。晶片ΙΑ、ΙΑ、1B之焊接區BP，係經由電極 5及以電氣方式連接在電極5之基座基板2之配線（未圖 示），以電氣方式連接在形成於基座基板2之一主面一端 之接續端子7 B及另一端之測試區8。接續端子7 B被用 作將此記憶卡MC安裝在攜帶式電子機器時之接續端子， 係通過通孔1 1以電氣方式連接在基座基板2下面之外部 接續端子7 A。而測試區8係在安裝此記憶卡MC之裝配 製程等時，用以測量電氣特性。 第4圖（a )係以簡化方式表示，以導線6連接上述 兩片記億晶片ΙΑ、1A之焊接區BP，與基座基板2之 對應之電極5之狀態之平面圖，該圖（b )係同上之截面 圖。 如上述，堆疊成兩層之記憶晶片ΙΑ、1A中，上層 之記憶晶片1 A係以向跟下層之記憶晶片1 A之一邊平行 . · 之X方向，及與之垂直相交之Y方向偏移之狀態堆叠。因 此，以兩條導線6 (例如導線6a及導線6b)，連接兩 片記憶晶片1 A、1 A所共同之焊接區B P (例如，上層 之記億晶片1 A之焊接區B P a及下層之記憶晶片1 A之 焊接區BPb )時，連接在一方之焊接區BP a之導線 6 a與連接在另一方之焊接區BPb之導線6 b，在從上 方看時不會重疊。因此，在結束導線搭接製程後之外觀檢 查過程中，可以從基座基板2之上方用攝影機等很容易判 定上下導線6相互間有無短路等之導線6之連接狀態。 對此，如第5圖所示，僅將上層之記憶晶片1 Α偏移 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝--- <請先闐讀背面之注意事項寫本頁) 訂： 經濟部智慧財產局員工消费合作社印製 495953 A7 B7 五、發明說明（7 ) <請先閲讀背面之注意事項 向一方（例如X方向）而重疊時，從上方看連接在一方之 焊接區B P a之導線6 a與連接在另一方之焊接區B p b 之導線6 b時，雙方幾乎是重疊在一起，要判定上下之導 線6相互間有無短路很困難。 若採上述第5圖所示之堆疊方式，因爲連接在下層之 記憶晶片1A之焊接區BPb之導線6b，係位於連接上 層之記憶晶片1 A之焊接區B P a之導線6 a之大体直下 方，因此，若降低導線6 a之環形高度，與其直下方之導 線6 b之距離會靠近，雙方便很容易短路。 ·線· 對此，若採第4圖所示之本實施形態之晶片堆叠方式 ，則因連接在同一電極5之導線6 a與導線6 b是向水平 方向錯開，因此，縱使降低導線6 a之環形高度，與其下 方之導線6 b短路之可能性不大。亦即，由於採用本實施 形態之晶片堆疊方式，便可以降低連接上層之記憶晶片 1 A之焊接區B P a之導線6 a之環形高度，因此可以使 封裝記億晶片1 A、1 A、1 B及導線6之樹脂3之厚度 相對變薄，可以達成記憶卡M C之薄型化、輕量化。 經濟部智慧財產局貝工消t合作社印製 裝配如上述構成之本實施形態之記憶卡M C時，係首 先在基座基板2上使用接合劑等安裝第1記憶晶片1 A， 接著，在其上面使用接合劑等安裝第2記億晶片1 A。這 時，第2記憶晶片1 A係對第1記憶晶片1 A向X方向及 Y方向偏移其位置堆疊。並在此作業之前後，於基座基板 2上之其他領域使用接合劑等安裝控制晶片1 B ° 接著，將安裝有晶片ΙΑ、ΙΑ、1B之上述基座基 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -10- 經濟部智慧財產局貝工消f合作社印製 495953 A7 B7 五、發明說明（8 ) 板2搭載於導線搭接裝置之加熱台，利用真空吸著等將基 座基板2之背面固定在加熱台後，依序用導線6以電氣方 式連接晶片ΙΑ、ΙΑ、1B之焊接區BP與相對應之電 極5。使用導線6連接的方法是，例如倂用熱壓接與超音 波振動之導線搭接方法。而以導線6連接上層之記憶晶片 1 A之焊接區B P與電極5時，若採用先將導線6之一端 連接在電極之一端（第1次搭接），然後在焊接區BP之 表面連接導線6之另一端（第2次搭接）之反向搭接方式 ，便可以將連接在上層之記億晶片1 A之焊接區B P之導 線6之環形高度降低。 其次，在藉外觀檢查判定導線6之連接狀態良否後， 以樹脂3封裝記憶晶片1 A、1 A、1 B及導線6。封裝 方法可以採使用灌注樹脂封裝或塑模封裝之任一方法。然 後，將探針接到觸形成在基座基板2 —端之測試區8 ’檢 查電氣特性後，再以樹脂製之蓋体4被覆基座基板2上面 ，而完成上述第1圖〜第3圖所示之本實施形態之記億卡 M C。 再者，也可以例如第6圖所示，以樹脂3封裝整個基 座基板2之上面，取代以蓋体4被覆基座基板2之整個上 面，做爲減少記憶卡之零件數降低製造成本之對策。樹脂 封裝可以用個別封裝或藉多連基板之以整批封裝（塑模） 個片化切割之樹脂封裝製作。 上述記憶卡M C係在基座基板2上安裝控制晶片1 Β ，但外形尺寸較記憶晶片1 Α小之控制晶片1 Β，可以如 ---!!1-裝--- <請先閱讀背面之注意Ϋ項H寫本頁) 訂·· --線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) - 11 - 495953 A7 — B7 五、發明說明（9 ) 第7圖及第8圖所示，堆疊在上層之記億晶片1 A上面。 採用這種晶片堆疊方式時，基座基板2不需保留控制 晶片1 B之安裝用面積，基座基板2便可以縮小相當於這 一部分之面積，藉此縮小其外形尺寸，因此可以達成記億 卡M C之小型化、輕量化。 同時，採用這種晶片堆疊方式時，因爲晶片1 A、 ΙΑ、1B會堆疊成3層，因此，封裝晶片ΙΑ、1A、 1 B及導線6之樹脂3會變厚，妨礙到記億卡MC之薄型 化。其對策是，硏磨晶片ΙΑ、ΙΑ、1B之背面使其變 薄，如此便可以抑制樹脂3之膜厚度增加。 本實施形態之晶片堆疊方式也可以適用到B G A ( Ball GridArray )型之組件。例如第9圖及第1 0圖所示之 B G A，係用樹脂3封裝安裝有堆疊成兩層之記憶晶片 1 A、1 A及控制晶片1 B之基座基板2之整個上面，而 在基座基板2之下面連接由焊錫等構成之突塊電極1 〇。 而第1 1圖及第1 2圖所示之BGA，係在堆叠兩層之記 億晶片1 A、1 A上再堆疊控制晶片1 B。 再者，要將本實施形態之晶片堆疊方式應用在B GA 時，若在下層之記憶晶片1 A與基座基板2之間，夾裝彈 性率較構成基座基板2之樹脂材料低之彈性体或由多孔質 樹脂所成之片狀材料，便可以減低將B G A安裝於基板時 加在突塊電極10之熱應力。 (實施形態2 ) — — — — — — — — — — 1! _ I I 請先闓讀背面之注意事項HS本頁) il· -線- 經濟部智慧財產局貝工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -12- 495953 A7 __ B7 五、發明說明（1〇 ) 第1 3圖係本實施形態之半導體裝置之截面圖，第 1 4圖係表示此半導體裝置之基座基板之平面圖。 本實施形態之半導體裝置係將形成有快閃記億器之4 片記憶晶片1 A i〜1 A 4及1片控制晶片1 B安裝於基座 基板2上，以樹脂3封裝此等記億晶片1 A i〜1 A 4、· 1 B，同時以樹脂製之蓋体4被覆基座基板2上面之記憶 卡M C。 4片記憶晶片1 Ai〜1 Α4形成有同一外形尺寸，同 一記憶容量之快閃記憶器。同時，此等記億晶片1 A i〜 1 A4係採用，在元件形成面之周邊部形成焊接區B P，且 沿其一邊將此等焊接區BP配置成一列之單邊焊接區方式 〇 本實施形態係將上述4片記憶晶片1 A i〜1 A 4成4 層重疊之狀態安裝在基座基板2上。這時，對最下層之記 憶晶片1 A i及從下面算起第3層之記憶晶片1 A 3，從下 面算起第2層及第4層之記憶晶片1 A 2、1 A 4，係向平 行於配置焊接區B P之一邊之X方向及與之垂直相交之方 向偏移之狀態堆疊。記憶晶片1 A i〜1 A 4係以朝向同一 方向之狀態重疊，記憶晶片1 A i、1 A 3，記憶晶片 1 A 2、1 A 4係分別重疊成從上看相互錯開狀。同時，從 下面算起第2層之記億晶片1 A 2及最上層之記憶晶片 1 A4，最下層之記憶晶片1 從下面算起第3層之記 億晶片1 A3，係堆疊成焊接區B P之位置成左右反方向。 在上述本實施形態之晶片堆疊方向，最下層之記憶晶 ------------»!裝 <請先閱讀背面之注意事項 寫本頁) •線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -13 - 495953 A7 ___ B7_____ 五、發明說明（11 ) 片1六：及從下面算起第3層之記憶晶片1 A3，從下面算 起第2層之記憶晶片1 A 2及最上層之記憶晶片1 A 4，因 分別連接到成電氣特性上共同之焊接區B P之兩條導線6 、6雖未向水平方向錯開，但因中間有記憶晶片，因此在 搭接時不必顧慮導線之環形高度。 因此，搭接在同一側之上下之導線6相互間之短路問 題會很少發生，在導線搭接製程結束後實施之外觀檢查過 程，可以使用攝影機等很容易判定導線6之連接狀態。 如第1 5圖及第1 6圖所示，本實施形態之晶片堆疊 方式係與上述實施形態1之晶片堆疊方式同樣，可以適用 B G A等之樹脂封裝型組件。當然也跟上述實施形態1同 樣，可以在最上層之記億晶片1 A 4之上面，堆疊外形尺寸 較其小之控制晶片1 B等。 也可以如第1 7圖所示，將兩片記憶晶片1 A、1 A 及控制晶片1 B之共同之焊接區B P (信號插腳）連接在 基座基板2上之同一電極5。該圖係應用在記憶卡MC之 例子，當然也可以應用在B G A型之組件。 以上，依據上述實施形態具体說明本發明人等所完成 之發明，但本發明並不限定在上述實施形態，當然可以在 未脫離其主旨之範圍內作各種變更。 上述實施形態係說明堆疊形成有快閃記憶器之晶片2 情形，但是並不限定如此，例如也可以適用在堆疊形成有 外形尺寸不相同之多片晶片或形成有不同種之記億器之多 片記憶器等時。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 先 閲 讀 背 面 之 注 3· I 頁 經濟部智慧財產局員工消费合作社印製 -14 - 495953 A7 B7 五、發明說明（12 ) (請先閱讀背面之注意事項|?!|寫本頁) 同時，上述實施形態係說明堆疊兩片或4片記憶晶片 之情形，但不限定如此，也可以適合於堆疊3片或5片以 上之晶片。 簡單說明從本案所揭示之發明中較具代表性者所能獲 得之效果如下。 依據本發明時，在堆疊多片半導體晶片而用樹脂封裝 之半導體裝置，可以降低，連接在下層之半導體晶片之焊 接區之導線與連接在上層之半導體晶片之焊接區之導線發 生短路事故。 依據本發明時，在堆疊多片半導體晶片而用樹脂封裝 之半導體裝置，可以提高在導線搭接製程後實施之外觀檢 查之可靠性。 依據本發明時，可以推動，堆疊多片半導體晶片而用 樹脂封裝之半導體裝置之小型化、薄型化。 依據本發明時，因爲堆疊多片半導體晶片會更容易， 因此可以藉小型、薄型以達成大容量之記億器組件。 經濟部智慧財產局員工消f合作社印製 依據本發明時，在堆疊多片半導體晶片而用樹脂封裝 之半導體裝置，因爲是藉導線搭接方式達成半導體晶片與 基板之電氣接續，因此可以降低半導體裝置之製造成本。 圖式之簡單說曰月 第1圖係表示本發明一實施形態之半導體裝置之外觀 之平面圖。 第2圖係第1圖之沿A -A線之截面圖。 -15· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 495953 A7 __B7 經濟部智慧財產局員工消费合作社印製 五 '發明說明（13 ) 第3圖係表示第1圖所示半導體裝置之基座基板之平 面圖。 第4圖（a )係簡化表示，以本發明之晶片堆疊方式 用導線連接兩片記憶晶片之焊接區與基座基板之相對應之 電極之狀態之平面圖。 第4圖（b )係簡化表示，以本發明之晶片堆疊方式 用導線連接兩片記憶晶片之焊接區與基座基板之相對應之 電極之狀態之截面圖。 第5圖（a )係簡化表示，以其他方式用導線連接兩 片記億晶片之焊接區與基座基板之相對應之電極之狀態之 平面圖。 第5圖（b )係簡化表示，以其他方式用導線連接兩 片記億晶片之焊接區與基座基板之相對應之電極之狀態之 截面圖。 第6圖係表示本發明之其他實施形態之半導體裝置之 截面圖。 第7圖係表示本發明之其他實施形態之半導體裝置之 截面圖。 第8圖係表示第7圖所示半導體裝置之基座基板之平 面圖。 第9圖係表示本發明之其他實施形態之半導體裝置之 截面圖。 第1 0圖係表示第9圖所示半導體裝置之基座基板之 平面圖。 ------------ 裝 (請先閱讀背面之注意事項 :窝本頁) 訂·· --線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） •16- 495953 A7 B7 五、發明說明（14) 第1 1圖係表示本發明之其他實施形態之半導體裝置 之截面圖。 第1 2圖係表示第1 1圖所示半導體裝置之基座基板 之平面圖。 第13圖係表示本發明之其他實施形態之半導體裝置 之截面圖。 第1 4圖係表不第1 3圖所不半導體裝置之基座基板 之平面圖。 第15圖係表示本發明之其他實施形態之半導體裝置 之截面圖。 第1 6圖係表示第1 5圖所示半導體裝置之基座基板 之平面圖。 第1 7圖係表示本發明之其他實施形態之半導體裝置 之基座基板之平面圖。 元件對照表 1 A............記憶晶片 1B............控制晶片、 2-...........基座基板 3 ............樹脂 4 ............蓋体 5 ............電極 6 ............導線 7A............外部接續端子 裝—— <請先閱讀背面之注意事項^寫本頁) 訂： -·線· 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 17 495953 A7 五、發明說明（15 ) 7B............接續端子 8............測試區 10 ............突塊電極 11 ............通孔 BP............焊接區 MC............記憶卡。 i — — — — — — — — — — — — - I I (請先閲讀背面之注意事項寫本頁) 訂： i線· 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) -18-

Claims (1)

  1. 495953 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 第89 1 22252號專利申請案 中文申請專利範圍修正本 91· 1· 3〇 民國9 1年.1月修正 1 · 一種半導體裝置，係將沿著主面之一邊形成有多 數焊接區之第1半導體晶片安裝在基板上，在該第1半導 體晶片之主面上堆疊沿著主面之一邊形成有多數焊接區之 第2半導體晶片，介由導線以電氣方式連接該第1及第2 半導體晶片之該焊接區，與該基板上之電極，而以樹脂封 裝該第1及第2半導體晶片及該導線之半導體裝置，·其特 徵在於，該第2半導體晶片係以平行於該第1半導體晶片 之一邊之方向，及與之垂直之方向偏移之狀態，堆疊在該 第1半導體晶片之主面上。 2 ·如申請專利範圍第1項之半導體裝置，其中該第 1及第2半導體晶片係相互形成有同一機能之電路之同一 · 尺寸之半導體晶片。 3 ·如申請專利範圍第2項之半導體裝置，其中在該 第1及第2半導體晶片之主面形成有快閃記憶器。 4 ·如申請專利範圍第1項之半導體裝置，其中該第 1及第2半導體晶片以相互朝向同一方向之狀態重疊，形 成在一方之半導體晶片之主面之該多數焊接區，與形成在 另一方之半導體晶片之主面之該多數焊接區，配置成相互 接近之狀態。 5 .如申請專利範圍第1項之半導體裝置，其中在該 第2半導體晶片之主面上，堆疊有外形尺寸較該第2半導 -- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） 495953 A8 B8 C8 _ D8 六、申請專利範圍 體晶片小之第3半導體晶片。 (請先閱讀背面之注意事項再填寫本頁) 6 .如申請專利範圍第5項之半導體裝置，其中該第 3半導體晶片係配置在，面對該第1半導體晶片之形成該 焊接區之一邊之另一邊，與該第2半導體晶片之形成該焊 接區之一邊所夾之領域。 7 ·如申請專利範圍第1項之半導體裝置，其中在該 基板上安裝有第3半導體晶片。 8 .如申請專利範圍第1項之半導體裝置，其中該第 2半導體晶片係該第1半導體晶片的主面上，在平行於該 第1半導體晶片的一邊方向以及在與此方向直交的方向偏 移的狀態下來堆疊，俾該第2半導體晶片的該主面的一邊 面對該第1半導體晶片的該主面的一'邊，且露出該第1半 導體晶片的該焊接區， 沿著主面的一邊，形成複數個焊接區的第三半導體晶· 片係該第2半導體晶片的主面上，俾該第3半導體晶片的 一^邊沿者5亥弟1半導體晶片的一*邊之同一'方向’且在與g亥 第1半導體晶片朝同一方向的狀態下重疊來堆疊， 經濟部智慧財產局員工消費合作社印製 該第1第2以及第3半導體晶片的該焊接區與該基板 上的電極分別藉由導線電性連接， 該第1第2以及第3半導體晶片與該導線被樹脂密封 〇 9 .如申請專利範圍第8項之半導體裝置，其中沿著 主面之一邊形成有多數焊接區之第4半導體晶片，係沿該 第2半導體晶片之該主面之一邊之同一方向，且朝向與該 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -2 - 495953 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 第2半導體晶片之同一方向之狀態重疊狀堆疊在該第3半 導體晶片之主面上。 i 〇 .如申請專利範圍第9項之半導體裝置，其中在 該第4半導體晶片之主面上，堆疊有外形尺寸較該4半導 體晶片小之第5半導體晶片。 1 1 .如申請專利範圍第1 〇項之半導體裝置，其中 該第5半導體晶片係配置在，面對該第1及第3半導體晶 片之形成焊接區之該主面之一邊之另一邊，與面對該第2 及第4半導體晶片之形成焊接區之該主面之一邊之另一邊 所夾之領域。 1 2 .如申請專利範圍第9項之半導體裝置，其中該 第2及第4半導體晶片，係向平行於該第1及第3半導體 晶片之一邊之方向偏移之狀態堆疊之。 1 3 . —種半導體裝置之製造方法，包含有下列製程· (a )在基板上安裝，沿著主面之一邊形成有多數焊 接區之第1半導體晶片之製程： (b )將沿著主面之一邊形成有多數焊接區之第2半 導體晶片’以平行於該第1半導體晶片之一邊之方向，及 與之垂直之方向偏移之狀態，堆疊在其主面上之製程； (c )介由導線，以電氣方式連接形成在該第1及第 2半導體晶片之該多數焊接區，與形成在該基板上之電極 之製程； (d )以樹脂封裝該第1及第2半導體晶片及該導線 (請先閲讀背面之注意事項再填寫本灵) 本紙張尺度適用中國國家標準（CNS )以胁（2^〇><297公楚y -3- 495953 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 々、申請專利範圍 之製程。 14·如申請專利範圍第13項之半導體裝置之製造 方法，其中介由導線，以電氣方式連接形成在該第2半導 體晶片之該多數焊接區，與電極時，首先將該導線之一端 連接在該電極之表面，然後，將該導線之另一端連接在該 焊接區之表面。 1 5 ·如申請專利範圍第1 3項之半導體裝置之製造 方法，其中進一步包含，在該基板之另一面連接突塊電極 之製程。 · 1 6 · —種半導體裝置，係將沿著主面之一邊形成有多 數焊接區之第1半導體晶片安裝在基板上，在該第1半導 體晶片之主面上堆疊沿著主面之一邊形成有多數焊接區之 第2半導體晶片，介由多數條導線以電氣方式連接該第1 及第2半導體晶片之該焊接區與該基板上之多數個電極， 而以樹脂封裝該第1及第2半導體晶片及該導線之半導體 裝置，其特徵在於，該第2半導體晶片係以平行於該第1 半導體晶片之一*邊之方向，及與之垂直之方向偏移之狀態 ，堆疊在該第1半導體晶片之主面上， 該第1及第2半導體晶片係互相形成有同一功能的電 路之同一尺寸的半導體晶片， 與該第1半導體晶片的焊接區連接的導線之與該基板 上的電極連接的部分，係和與該第2半導體晶片的焊接區連 接的導線之與該基板上的電極連接的部分，距該第1半導體 晶片的一邊的距離不同。 ----------·! (請先閱讀背面之注意事項再填寫本頁) 訂 華· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 495953 A8 B8 C8 ___ D8 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 1 7 ·如申請專利範圍第1 6項之半導體裝置，其中與該 第1半導體晶片的焊接區連接的導線之與該基板上的電極 連接的部分，係配置於比與該第2半導體晶片的焊接區連接 的導線之與該基板上的電極連接的部分還接近該第1半導 體晶片的一邊的區域。 1 8 ·如申請專利範圍第1 7項之半導體裝置，其中該第 1半導體晶片的焊接區與中介導線連接的基板上的電極， 與該第2半導體晶片的焊接區與中介導線連接的基板上的電 極，在該基板上係電性連接。 · 1 9 .如申請專利範圍第1 8項之半導體裝置，其中該半 導體裝置係在該基板的背面上具有多數個外部連接端子之 I己'丨意一^ 。 20 ·如申請專利範圍第1 9項之半導體裝置，其中在該 弟1半導體晶片的主面以及第2半導體晶片的主面形成有快· 閃記憶器。 經濟部智慧財產局員工消費合作社印製 21 ·如申請專利範圍第20項之半導體裝置，其中在該 基板上安裝形成有於其主面控制該快閃記憶器的電路之第3 半導體晶片。 22 ·如申請專利範圍第2 1項之半導體裝置，其中該第3 半導體晶片在基板平面上安裝於該第i以及第2半導體晶片 與該外部連接端子之間的區域。 23 .如申請專利範圍第1 8項之半導體裝置，其中在該 基板的背面上具有由多數個焊錫所構成的突塊電極。 -5 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
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