TWI419240B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI419240B
TWI419240B TW096124032A TW96124032A TWI419240B TW I419240 B TWI419240 B TW I419240B TW 096124032 A TW096124032 A TW 096124032A TW 96124032 A TW96124032 A TW 96124032A TW I419240 B TWI419240 B TW I419240B
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TW
Taiwan
Prior art keywords
semiconductor wafer
semiconductor
semiconductor device
insulating film
thickness
Prior art date
Application number
TW096124032A
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English (en)
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TW200818351A (en
Inventor
Takashi Kikuchi
Koichi Kanemoto
Chuichi Miyazaki
Toshihiro Shiotsuki
Original Assignee
Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW200818351A publication Critical patent/TW200818351A/zh
Application granted granted Critical
Publication of TWI419240B publication Critical patent/TWI419240B/zh

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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Description

半導體裝置
本發明係關於一種半導體裝置技術，尤其係關於一種適用於具有如下構成之半導體裝置之有效技術，即，將平面尺寸不同之複數個半導體晶片以堆疊之狀態收納於相同密封體內。
於1個密封體中，具有收納記憶體電路用半導體晶片以及控制其動作之控制電路用半導體晶片，以建構預期系統之半導體裝置。
於上述構成之半導體裝置中，於配線基板上，以堆疊之狀態搭載記憶體電路用半導體晶片及控制電路用半導體晶片，以此實現半導體裝置之小型化。此時，一般而言，從實現增大儲存容量之觀點出發，記憶體電路用半導體晶片之平面尺寸大於控制電路用半導體晶片之平面尺寸，因此，於記憶體電路用半導體晶片上堆疊有控制電路用半導體晶片。
下層之記憶體電路用半導體晶片係經由附模組膠膜(Die Attach Film：以下，簡稱DAF)而搭載於配線基板上。上述記憶體電路用半導體晶片之電極通過接線而電連接於配線基板之電極上。上層之控制電路用半導體晶片係經由DAF而搭載於記憶體電路用半導體晶片上。上述控制電路用半導體晶片之電極通過接線而電連接於配線基板之電極上。
關於該種半導體裝置，在例如日本專利特開2004－146645號公報(專利文獻1)中有所記載。於上述專利文獻1之圖21及圖22中，揭示有將複數個半導體晶片經由DAF而積層之技術。
[專利文獻1]日本專利特開2004－146645號公報(圖21及圖22等)
然而，本發明者發現，於上述半導體裝置中存在以下問題。
由於上層之控制電路用半導體晶片之平面尺寸小於下層之記憶體電路用半導體晶片之平面尺寸，因此，利用正接方式(將半導體芯片側設為第1接合點，且將配線基板側設為第2接合點之方式)，將控制電路用半導體晶片之電極與配線基板之電極經由接線而電接合時，有時上述接線會接觸到下層之記憶體電路用半導體晶片之上面側周緣部。即使於上述專利文獻1所記載之半導體裝置中僅經由DAF來積層半導體晶片，亦無法避免接線之一部分與下層之半導體晶片之一部分相接觸之問題。
此處，若將控制電路用半導體晶片盡可能地接近於記憶體電路用半導體晶片之外周而配置，則可避免上述接線接觸到記憶體電路用半導體晶片之不良情形。然而，由於以下理由而導致接線之接合本身變得困難。第1個理由為，例如在使控制電路用半導體晶片接近於記憶體電路用半導體晶片之外周時，接線之環部變高。上述原因為，接線50之形成如圖19~圖21所示，將半導體晶片51C之電極52與配線基板53之電極54的間隔DA所相當之長度DB之接線50，從毛細管55引出到半導體晶片51C之電極52上其後，以描繪軌跡之方式使毛細管55朝向配線基板53之電極54移動。其後，使毛細管55在配線基板53之電極54之面上滑行，以將接線50連接到配線基板53之電極54上。即，如圖21所示，若使控制電路用半導體晶片51C接近於記憶體電路用半導體晶片51M之外周時，半導體晶片51C之電極52與配線基板53之電極54間之距離變近，因此，在第1接合點處引出之接線50長度短之狀態下，接線50會下落到第2接合點，所以，接線50之一部分不僅會接觸到配置於下段之記憶體電路用半導體晶片51M，而且接觸到控制電路用半導體晶片51C之上面側周緣部之可能性亦變高。因而，為避免與各半導體晶片51C、51M之周緣部產生接觸，可於第1接合點處引出長的接線50，但隨此會使環部形成得較高。並且，上述環部之一部分可透過密封體而看見或者露出。第2個理由為，例如在使控制電路用半導體晶片接近於記憶體電路用半導體晶片之外周時，接線從第1接合部下落到第2接合部之軌跡過於崎嶇，由此導致在第2接合部之接合變得困難，因此，導線之環部形狀難以穩定。第3個理由為，例如在使控制電路用半導體晶片越接近於記憶體電路用半導體晶片之外周之情況下，平面上所觀察到之接線之入射角度越會變為彎曲之銳角。即，在與設置有作為對象之半導體晶片之電極的一邊大致平行之方向上形成接線，因此，相鄰接之接線之間隔會變窄，故易產生接線彼此短路之不良情形。
另一方面，將上述接線之接合方式設為與上述正接方式相反之反接方式(將配線基板之電極設為第1接合點，且將半導體晶片之電極設為第2接合點之方式)時，可取得接線與下層之記憶體電路用半導體晶片之間之邊界，因此，可避免接線接觸到記憶體電路用半導體晶片之不良情形。然而，在導線接合步驟前，必須在第2接合部側(控制電路用半導體晶片之電極)形成金凸塊，因而產生下述問題，即，半導體裝置之裝配時間增加及裝配效率降低，且半導體裝置之製造成本增大。
因此，本發明之目的在於提供一種可使具有下述構成之半導體裝置之可靠性提高之技術，即，將平面尺寸不同之複數個半導體晶片經由具有黏著性之絕緣膜，以堆疊之狀態收納於相同密封體內之結構。
本發明之上述目的及其他目的與新穎之特徵，可根據本說明書之描述及隨附圖式而明確。
對本申請案所揭示之發明中代表性之內容概要，如下將進行簡單說明。
即，本發明之半導體裝置具有第1半導體晶片及第2半導體晶片，上述第1半導體晶片經由具有黏著性之第1絕緣膜而搭載於配線基板上，上述第2半導體晶片之平面尺寸小於上述第1半導體晶片之半導體晶片，且經由具有黏著性之第2絕緣膜而堆疊於上述第1半導體晶片上，上述第2絕緣膜之厚度大於上述第1絕緣膜之厚度。
對本申請案揭示之發明中代表性內容所取得之效果，如下將進行簡單說明。
即，使上述第2絕緣膜之厚度大於上述第1絕緣膜之厚度，藉此可使半導體裝置之可靠性提高。
以下實施形態中，為方便起見，必要時分割為複數個部分或實施形態而進行說明，但除特別明示之情形外，上述各部分或實施形態並非彼此無關，而是其中一者是另一者的一部分或全部變形例、詳細情形、補充說明等之關係。而且，於以下實施形態中，當言及要素之數量等(包含個數、數值、量、範圍等)時，除特別明示之情形以及原理上明確限定為特定數量之情形等之外，並非限定於上述特定數量，亦可為特定數量以下或以下。進而，於以下實施形態中，除特別明示之情況以及原理上明確認為必須之情形等外，上述構成要素(亦包含要素步驟等)當然未必為所必須。同樣地，於以下實施形態中，當言及構成要素等之形狀、位置關係等時，除特別明示之情形以及原理上明確認為並非如此之情形等之外，實質上包含近似或類似於上述形狀等之情形。此情形對於上述數值及範圍亦相同。而且，在用以說明本實施形態之全部圖式中，對具有相同功能之部分附以相同符號，盡可能省略重複之說明。以下，將根據圖式來詳細說明本發明之實施形態。
(實施形態1)
圖1係本實施形態1之半導體裝置之俯視圖，圖2係圖1之X1－X1線之剖面圖，圖3係圖1之X1－X1線之剖面圖，即，從與X1－X1線箭頭相反之方向觀察之剖面圖，圖4係圖2之區域A之放大剖面圖，圖5(a)係本發明者所研討之半導體裝置之主要部分剖面圖，圖5(b)係本實施形態1之半導體裝置之主要部分剖面圖。
再者，圖1中，為易於看見半導體裝置之內部構成而去除密封體。又，圖3中，為易於理解半導體裝置之構成，亦顯示有與X1－X1線未交叉之接線。
本實施形態1之半導體裝置1A係具有CSP(Chip Size Package，晶片尺寸封裝)結構之半導體裝置，上述CSP結構係將記憶體電路用半導體晶片2M1、2M2及控制其動作之控制電路用半導體晶片2C，以在配線基板3之主面上堆疊之狀態，收納於相同之密封體4內，整體建構儲存系統。本實施形態之半導體裝置1A使用於例如具有薄型化或小型化要求之移動機器、硬盤用控制機器、或控制器內置型儲存卡。
作為各半導體晶片2M1、2M2、2C之黏著構件，使用DAF(Die Attach Film，附模組膠膜)5a~5c。有時亦使用漿狀材作為上述黏著構件，但本實施形態1中，根據以下理由而使用DAF。
第1理由為，在確保半導體晶片之抗折強度方面情況良好。近年來，半導體晶片越來越薄，因此，如何確保半導體晶片之抗折強度成為重要課題。對於DAF而言，可將薄半導體晶圓分階段地黏貼於上述半導體晶片之背面，且在薄半導體晶圓之搬送步驟、切割步驟、以及每個半導體晶片之搬送步驟(拾取)等中，在保護薄半導體晶片方面之情況良好。
第2理由為，可使DAF之厚度較絕緣漿狀薄，因此在使半導體裝置1A之總厚度變薄方面之情況良好。近年來，要求半導體裝置小型輕薄化，因此，在積層複數片半導體晶片之構成中，較好的是黏著構件之厚度薄者。
第3理由為，DAF之厚度均勻性高於絕緣漿狀材，因此可與半導體晶片之面積增大相對應。對於漿狀材而言，在半導體晶片之面積增大時，難以在上述面內確保厚度均勻，有時半導體晶片會傾斜。相對於此，對於DAF而言，由於其厚度均勻性高，故即使半導體晶片之面積增大，亦可確保半導體晶片之平坦性。
第4理由為，與漿狀材相比，DAF可於低溫下黏著。對於漿狀材而言，為了使漿狀材硬化，必須在將半導體晶片搭載於配線基板3上之後，進行某種程度之熱處理，因此，有時會因上述熱量而使配線基板3翹曲，導致無法順利地搬送配線基板3等不良情形之產生。相對於此，對於DAF而言，由於可在低溫下黏著，且可抑制或防止配線基板3之翹曲，故可避免無法搬送配線基板3等不良情形。
第5理由為，半導體晶片之平面位置精度高。對於漿狀材而言，在半導體晶片黏著時，半導體晶片之平面位置有時會產生稍許偏移。相對於此，對於DAF而言，在半導體晶片黏著時，半導體晶片之平面位置不會產生偏移。
各半導體晶片2M1、2M2、2C係分別通過正接方式之接線(以下，僅稱為導線)6a~6c而電連接於配線基板3之配線上。正接方式係指，在半導體晶片之接合墊(以下，僅稱為墊)上進行導線之最初接合(第1接合)，且對配線基板之電極進行繼導線之第1接合後之接合(第2接合)。在與正接方式相反之反接方式中，必須於第2接合部側之半導體晶片之墊上形成金凸塊，因此擔心製造步驟及成本會增多。相對於此，本實施形態1中，採用正接方式而省去在半導體晶片之墊上形成金凸塊之步驟，因此可減少半導體裝置1A之製造步驟，故可降低半導體裝置1A之成本。
上述半導體晶片2M1與2M2及2C、DAF5a~5c、導線6a~6c係利用密封體4來覆蓋並密封。密封體4例如係由環氧系樹脂而形成。
上述配線基板(晶片搭載構件)3係由例如以玻璃環氧樹脂作為絕緣基材之印刷配線基板而形成之平面長方形之薄板所構成，且具有沿著其厚度方向位於彼此相反側之主面(第2主面)及背面(第1主面)。
在上述配線基板3之主面及背面，形成有阻焊劑SR。阻焊劑SR具有防止焊料接觸到無需焊接之導體圖案(配線及電極)之功能，以及防止因濕氣或污染而導致之導體圖案等劣化之功能，除此之外，還具有使配線基板3之主面及背面更平坦之功能。作為使配線基板3之主面及背面平坦之方法，具有如下：例如於阻焊劑SR之熱硬化處理前施加壓力，以使阻焊劑SR之表面平坦之方法，或者塗敷兩次阻焊劑SR，以使阻焊劑SR之表面平坦之方法。
配線基板3之主面係搭載有上述半導體晶片2M1、2M2、2C之面。於該配線基板3之主面上，配置有複數個電極7a、7b。電極7a係在配線基板3之單側短邊附近，沿著上述短邊並排地配置複數個。電極7b係在配線基板3之單側長邊附近，沿著上述長邊並排地配置複數個。
另一方面，配線基板3之背面係與搭載有半導體裝置1A之配線基板對向之面。於上述配線基板3之背面，以從上述阻焊劑SR露出之狀態行列狀地配置有複數個凸塊電極8。各凸塊電極8具有形成於配線基板3之背面之電極8a、以及與此接合之凸塊部8b。電極8a例如由銅而形成。凸塊部8b例如通過錫(Sn)－銀(Ag)－銅、錫－銀－銅－銻(Sb)、錫－銅等無鉛焊錫而形成。上述凸塊電極8(電極8a)通過配線基板3之內部配線而電連接於上述電極7a、7b。
上述最下層之半導體晶片(第1半導體晶片)2M1例如由包含單晶矽(Si)之平面長方形之半導體薄板而形成，且由DAF5a黏著並固定於配線基板3之主面(第2主面)上。
在上述半導體晶片2M1之單側短邊附近，沿著半導體晶片2M1之短邊並排配置有複數個墊9a。墊9a例如係由鋁(Al)或鋁合金而形成。上述半導體晶片2M1之複數個墊9a經由正接方式之複數個導線(第1接線)6a而電連接於配線基板3之電極7a。導線6a例如係由金(Au)而形成。
於上述半導體晶片2M1之主面上，利用DAF5b黏著並固定有半導體晶片(第1半導體晶片)2M2。該半導體晶片2M2例如係由包含單晶矽之平面長方形之半導體薄板而形成，在與下層之半導體晶片2M1之長度方向及寬度方向一致之狀態下，且在半導體晶片2M1之長度方向上偏移而使下層之半導體晶片2M1之複數個墊9a露出之狀態下，將上述半導體晶片2M2配置成覆蓋在下層之半導體晶片2M1之主面上。
在上述半導體晶片2M2之單側短邊附近，亦沿著半導體晶片2M2之短邊而並排配置有複數個墊9b。上述墊9b例如亦係由鋁或鋁合金而形成。上述半導體晶片2M2之複數個墊9b係經由正接方式之複數個導線(第1接線)6b而電連接於配線基板3之電極7a。導線6b例如亦係由金而形成。
上述2片半導體晶片2M1、2M2以彼此相同之尺寸(縱、橫及厚度dm1、dm2)而形成，於上述各主面上，形成具有相同儲存容量之快閃記憶體(例如4GB(千兆字節)之輔助閘極AND型快閃記憶體)。半導體晶片2M1、2M2各自之厚度dm1、dm2例如為80 μm~90 μm左右。採用AND型儲存器可提高電路動作之速度。
此處，一般而言，作為將半導體晶片2M1固定於配線基板3上之黏著構件，因考慮到配線基板3之主面上配線或電極之凹凸而使用漿狀材，另一方面，作為固定半導體晶片2M2之黏著構件，使用DAF。然而，當相同半導體晶片2M1、2M2中之黏著構件不同時，會產生裝配繁雜之問題。
對此，本實施形態1中，如上所述，利用阻焊劑SR可確保配線基板3之主面之平坦性，因此，可使用DAF5a作為最下層之半導體晶片2M1之黏著構件。即，可使用相同之DAF5a、5b作為相同半導體晶片2M1、2M2之黏著構件，因此，可使半導體裝置1A之裝配步驟簡單化。上述DAF5a、5b之厚度df1、df2相等，例如為10 μm左右。
於上述半導體晶片2M2之主面上，利用DAF5c黏著並固定有半導體晶片(第2半導體晶片)2C。上述半導體晶片2C例如係由包含單晶矽之平面長方形之半導體薄板而形成，且於其主面上，形成控制上述半導體晶片2M1、2M2之記憶體電路動作之控制電路。
上述半導體晶片2C係以與下層之半導體晶片2M2之長度方向及寬度方向一致之狀態而配置於半導體晶片2M2之主面內。於上述半導體晶片2C之單側長邊附近，沿著半導體晶片2C之長邊並排配置有複數個墊9c。上述墊9c例如亦係由鋁或鋁合金而形成。上述半導體晶片2C之複數個墊9c經由正接方式之複數個導線(第2接線)6c而電連接於配線基板3之電極7b。導線6c例如亦係由金而形成。
上述最上層之半導體晶片2C之平面尺寸(縱及橫、面積)小於上述半導體晶片2M1、2M2各自之平面尺寸(縱及橫、面積)。因此，若不採取任何方法，則如圖5(a)之虛線所包圍之部分所示，會產生導線6c接近並接觸到半導體晶片2M2之主面角部之問題。再者，圖5(a)中例示有如下情形，即，半導體晶片2M1、2M2、2C之厚度相等，而且，使用相同之DAF5a作為各半導體晶片2M1、2M2、2C之黏著構件。
作為上述問題之對策，可採用增大導線6c之第1接合之高度(沿著與配線基板3之主面正交之方向離開上述配線基板3之主面之距離)。因此，一般而言，無論記憶體電路及控制電路，在考慮構件之供應及標準化時，較理想的是使DAF5a~5c之厚度相同，但本實施形態1中，使半導體晶片2C背面之DAF5c之厚度df3大於半導體晶片2M1、2M2背面之DAF5a、5b各自之厚度df1、df2。DAF5c之厚度df3例如為25 μm左右。
如上所述，藉由增加DAF5c之厚度而可增加導線6c之第1接合之高度，因此相應地，如圖5(b)之虛線所包圍之部分所示，可使導線6c遠離半導體晶片2M2之主面角部。所以，可降低導線6c接觸到半導體晶片2M2之主面角部之不良可能性，故可提高半導體裝置1A之裝配性及可靠性。
又，導線6c之環部亦不會因上述構成而增高，故亦不會透見導線6c或者露出導線6c。因此，可使半導體裝置1A之良率提高。再者，圖5(b)中例示有半導體晶片2M1、2M2、2C之厚度相等之情形。
此處，之所以使半導體晶片2M1、2M2背面之DAF5a、5b變薄，係例如下述理由。
即，從增加導線6c之第1接合之高度之觀點出發，考慮亦可使半導體晶片2M1、2M2背面之DAF5a、5b變厚。然而，在使DAF5a、5b變厚時，半導體晶片2M2之主面亦變高，因此，上述導線6c接觸到半導體晶片2M2之主面角部之不良可能性會增大。故使半導體晶片2M1、2M2背面之DAF5a、5b相對地變薄。
而且，伴隨如移動機器或數字家電等電子機器之多功能化，儲存器具有日益大容量化之傾向。為了與此對應，尤其必須將記憶體電路用半導體晶片堆疊為多層。此處，現狀是，為了實現在半導體裝置1A所決定之厚度(密封體4之厚度)中半導體晶片之多層化，基本上處於使所有DAF5a~5c均變薄之發展方向。相對於此，本實施形態1中，如上所述，從降低導線6c接觸到半導體晶片2M2之主面角部之不良情形之觀點出發，使半導體晶片2C背面之DAF5c變厚。因此，相應地使記憶體電路用半導體晶片2M1、2M2背面之DAF5a、5b變薄。
進而，使記憶體電路用半導體晶片變薄，由此可進一步在半導體裝置1A中堆疊半導體晶片，以實現大容量化。然而，當考慮確保在半導體晶片安裝步驟中之拾取性(裝配良率)時，記憶體電路用半導體晶片2M1、2M2之厚度會達到極限。因此，較好的是使記憶體電路用半導體晶片2M1、2M2背面之DAF5a、5b變薄。
上述最上層之半導體晶片2C係以其主面中心從下層之半導體晶片2M2之主面中心偏向半導體晶片2M2單側長邊之狀態而配置。然而，要考慮到使半導體晶片2C不會過分接近於下層之半導體晶片2M2之單側長邊。其理由可利用圖6及圖7而說明。再者，圖6係本發明者所研討之半導體裝置之主要部分剖面圖，圖7(a)、圖7(b)係表示最上層之半導體晶片2C之配置的半導體裝置之主要部分俯視圖。
如圖6所示，若將半導體晶片2C配置為盡可能接近於半導體晶片2M2之外周，則可避免上述導線6c接觸到半導體晶片2M2之不良情形。然而，此時會產生下述問題，即，導線6c之環部變高，上述環部可透過密封體4而看見或者露出。又，從導線6c之第1接合下落到第2接合之軌跡過於崎嶇而使第2接合時之接合變得困難。而且，如圖7(a)、圖7(b)所示，使半導體晶片2C越接近於半導體晶片2M2外周，則越會使複數個導線6c中於排列方向兩端之導線6c較平面觀察時更傾斜地進行導線接合，但由於上述導線6c之入射角度θ變為銳角，故鄰接之導線6c之間隔變窄，易產生鄰接之導線6c彼此短路之不良情形。
因此，本實施形態1中，將半導體晶片2C配置為不過分接近於下層之半導體晶片2M2之單側長邊。藉此，可將導線6c之第1接合與第2接合之間隔設定為適當之距離，故導線6c之環部高度不會變得過高，導線6c之軌跡亦不會變得過於崎嶇。又，導線6c之入射角度θ亦不會過分為銳角。因此，可使導線6c之穩定性提高。
而且，將通過導線6c而與半導體晶片2C電連接之電極7b配置於配線基板3之長邊側之原因在於，藉此容易引回配線基板3上之配線。又，若將導線6c所連接之電極7b配置於配線基板3之短邊側，則半導體裝置1A之長度方向之尺寸變得更長，半導體裝置1A之平面尺寸會變大，因此亦為了避免此情形。
又，本實施形態1中，半導體晶片2C之厚度dc形成為大於半導體晶片2M1、2M2各自之厚度dm1、dm2。半導體晶片2C之厚度dc例如為120 μm~150 μm左右。
使半導體晶片2C增厚之主要理由係用以抑制半導體裝置1A之翹曲。即，半導體裝置1A中之密封體(樹脂)4之量多時，由於密封體4之硬化收縮，半導體裝置1A有時會翹曲，因而難以實現半導體裝置1A之安裝。因此，本實施形態1中，使半導體晶片2C增厚。藉此，可增大密封體4中半導體晶片之體積，並可減少半導體裝置1A中密封體(樹脂)4之量，故可抑制半導體裝置1A之翹曲，且可減少或防止半導體裝置1A之安裝不良情形。
當僅考慮抑制翹曲時，亦可考慮使下層之半導體晶片2M1、2M2變厚，但當增厚下層之半導體晶片2M1、2M2時，半導體晶片2M2之主面高度會變高，由此容易產生上述導線6c與半導體晶片2M2之主面角部接觸不良。又，為避免上述導線6c之接觸問題而使導線6c之環部變高時，從防止導線6c可透見或露出之觀點，必須使密封體4變厚，因而半導體裝置1A變厚。進而，如上所述，為實現在半導體裝置1A所決定之厚度(密封體4之厚度)中半導體晶片之多層化，使必須進行多層化之記憶體電路用半導體晶片2M1、2M2變薄，此方法在實現半導體裝置1A之薄型化方面較佳。
因此，本實施形態1中，使最上層之半導體晶片2C之厚度大於其下層之半導體晶片2M1、2M2之厚度。藉此，可抑制半導體裝置1A之翹曲，而不會使半導體裝置1A變厚。又，使半導體晶片2C之厚度大於下層之半導體晶片2M1、2M2之厚度，藉此半導體晶片2C之第1接合點變高，故可進而降低導線6c接觸到半導體晶片2M2之主面角部之不良可能性。
此處，本發明者首次發現，在使半導體晶片2C變厚時，以下之新問題會變得顯著。
第1個問題係容易在半導體晶片2C之背面產生破裂之問題。
在對附帶DAF之半導體晶圓進行切割時，由於同時切斷硬部分及軟部分，因此容易在半導體晶片與DAF之邊界(半導體晶片之背面側角部)產生破裂。尤其是此破裂不良情況具有使半導體晶圓越發變厚之傾向。根據本發明者之分析結果，當半導體晶圓之厚度為90 μm左右時，不大會產生破裂，相對於此，當半導體晶圓之厚度為150 μm以上時，破裂會增多。若在如上所述破裂中之矽屑從半導體晶片2C之背面轉入並附著於DAF5c背面之狀態下，將半導體晶片2C堆疊於半導體晶片2M2之主面上，則會產生DAF5c背面之矽屑對半導體晶片2M2之主面造成損傷之問題。
對此，根據本實施形態1，即使由於使DAF5c變厚而在半導體晶片2C之背面產生破裂，亦可減少或防止上述破裂產生之矽屑轉入DAF5c之背面，因此，可減少或防止因破裂產生之矽屑而導致之對半導體晶片2M2主面之損傷不良。根據本發明者之研討可知，使DAF5c之厚度為20 μm以上，藉此可減少如上所述之破裂轉入DAF5c背面之現象。
第2個問題係由無法吸收半導體晶片2C之翹曲而產生。利用圖8及圖9來說明上述問題，並利用圖10來說明其解決結果。再者，圖8表示薄半導體晶片100A及搭載有該半導體晶片100A之搭載基板101之剖面圖。又，圖9表示厚度大於上述半導體晶片100A之半導體晶片100B及搭載有該半導體晶片100B之搭載基板101之剖面圖。半導體晶片100A、100B之黏著構件均使用薄DAF5a。圖10表示半導體晶片2C及搭載有該半導體晶片2C之搭載基板101之剖面圖。
如圖8(a)所示，當半導體晶片100A薄時，即使於搭載前之半導體晶片100A上產生彎曲，亦會由於其剛性低而如圖8(b)所示，使搭載後之半導體晶片100A利用DAF5a之黏著力在類似搭載面之大致平坦之狀態搭載。
然而，如圖9(a)所示，當半導體晶片100B變厚時，剛性會變強而勝過DAF5a之黏著力，因此如圖9(b)所示，以翹曲之狀態搭載有半導體晶片100B，故產生與半導體晶片100B之外周部(以虛線包圍之區域)未黏著之間隙。其結果為，於半導體裝置1A之裝配步驟中，以上述間隙為起點，半導體晶片100B剝離，或者於鑄模步驟中，填充樹脂從上述間隙進入半導體晶片100B之背面側，導致半導體晶片100B破損。
相對於此，根據本實施形態1，如圖10所示，通過增厚DAF5c而可以DAF5c來吸收半導體晶片2C之翹曲。藉此，可增大半導體晶片2C與搭載基板101(本實施形態1中相當於半導體晶片2M2)之密著面積，且可減少半導體晶片2C之外周部(以虛線包圍之區域)之間隙，故可減少或防止半導體晶片2C之剝離及破損。
根據本發明者之實驗．評價結果，對於應用10 μm厚度之DAF之半導體晶片，當其厚度達到DAF厚度之10倍時較佳，當超過上述厚度時，較好的是應用厚度大於10 μm之DAF。以10 μm厚度之DAF為1個基準之理由為，由於配線基板3之主面之平坦性。現狀為，配線基板3之主面之平坦性為3 μm，保證範圍為5 μm。又，DAF厚度製造方面之偏差為±2 μm。由此可認為，將半導體晶片固定於配線基板3上且無可靠性問題之DAF之厚度，最薄規格為10 μm左右。
其次，利用圖11及圖12來說明本實施形態1之半導體裝置1A之製造方法之一例。
首先，如圖11所示，利用磨石15來研削晶圓處理結束後之半導體晶圓2W之背面，使半導體晶圓2W形成為預期之厚度(圖11之背面研磨步驟200)。再者，此處表示1片半導體晶圓2W，但上述半導體晶片2M1、2M2及上述半導體晶片2C分別形成於各自之半導體晶圓上。再者，亦可於半導體晶圓2W之背面研削步驟之後，對半導體晶圓2W之背面實施研磨處理或蝕刻處理。
繼而，將半導體晶圓2W之背面黏貼於晶圓黏膠片16之DAF黏貼面上(圖11之晶圓安裝步驟201)。該晶圓黏膠片16係在切割膜之主面上黏貼DAF而形成之DAF/切割膜一體型薄片。半導體晶圓2W係以其主面朝向上方、且將半導體晶圓2W之背面直接黏貼於晶圓黏膠片16之主面之DAF上之狀態，搭載於晶圓黏膠片16上。
繼之，在將如包圍半導體晶圓2W之外周之晶圓環17黏貼於晶圓黏膠片16之主面上之後，將半導體晶圓2W搬送到切割裝置，進行切割處理(圖11之切割步驟202)。切割處理係指如下步驟：使高速旋轉之切割刀18沿著半導體晶圓2W之切斷線(半導體晶片之邊界線)切斷半導體晶圓2W，將其分割為一個個半導體晶片2M1、2M2或半導體晶片2C。
繼後，從切割步驟後之半導體晶圓2W中拾取半導體晶片2M1，並搭載於配線基板3之主面上。此時，利用上述背面之DAF5a，將半導體晶片2M1黏著固定在配線基板3上。此階段之配線基板3成為複數個半導體裝置之形成區域為一體之構成。其次，從相同半導體晶圓2W中拾取半導體晶片2M2，並將半導體晶片2M2搭載於半導體晶片2M1之主面上。此時，利用背面之DAF5b，將半導體晶片2M2黏著固定於半導體晶片2M1上(圖11之晶片安裝步驟203)。
此處，由於半導體晶片2M1、2M2為相同之儲存器，因此從相同之半導體晶圓2W中拾取半導體晶片2M1、2M2。藉此，可使半導體裝置之製造步驟簡單。而且，由於可搭載特性相似之儲存器，故可使半導體裝置1A之性能提高。再者，亦可從不同之半導體晶圓中拾取半導體晶片2M1、2M2。
繼而，從切割步驟後之半導體晶圓2W中拾取半導體晶片2C並搭載於半導體晶片2M2之主面上。此時，利用背面之DAF5c，將半導體晶片2C黏著固定於半導體晶片2M2上(圖11之晶片安裝步驟204)。
繼而，如圖12所示，藉由導線6a、6b、6c來連接配線基板3上之半導體晶片2M1、2M2、2C與配線基板3之電極(圖12之導線接合步驟205)。
繼而，利用由填充樹脂而形成的密封體4一併密封導線接合步驟後之配線基板3主面上之複數個半導體裝置區域之半導體晶片2M1、2M2、2C及導線6a、6b、6c等。(圖12之鑄模步驟206)。
繼而，翻轉配線基板3，於配線基板3背面之每個半導體裝置形成區域，將利用無鉛焊錫而形成之焊球8b1放在配置於上述背面上之複數個電極8a中之後，實施熱處理(回流加熱處理)，藉此於電極8a中形成凸塊部8b(圖12之焊球安裝步驟207)。
繼而，將高速旋轉之切割刀19從配線基板3之背面沿著配線基板3之切斷線(半導體裝置1A之邊界線)而切斷，分割為一個個半導體裝置1A(圖12之單片切斷步驟208)。
其後，經過選別．外觀檢查(圖12之步驟209)，製造半導體裝置1A。
(實施形態2)
在上述實施形態1中，對下述情況有進行說明：由於假設將半導體裝置1A應用於要求高速動作之電子機器中，因此半導體晶片2M1、2M2之快閃記憶體為AND型，但並非限定於此，亦可使用例如NAND型快閃記憶體。
圖13係本實施形態2之半導體裝置1A之主要部分剖面圖。虛線表示上述實施形態1中形成有AND型快閃記憶體之半導體晶片2M1、2M2。距離L1表示從形成有AND型快閃記憶體之半導體晶片2M2之主面角部至導線6c之距離。
當為NAND型快閃記憶體時，可使半導體晶片2M1、2M2之平面尺寸小於AND型(虛線)時之平面尺寸，故可使從半導體晶片2M2之主面角至導線6c之距離L2大於距離L1。因此，可減少導線6c接觸到半導體晶片2M2之主面角部之不良可能性，故可使半導體裝置1A之裝配性及可靠性提高。
(實施形態3)
於上述實施形態1、2中，說明了堆疊2個記憶體電路用半導體晶片之情形，但並非限定於此，亦可堆疊例如3個以上，亦可僅堆疊1個。
圖14(a)、圖14(b)係本發明者所研討之半導體裝置之主要部分剖面圖。圖14(a)表示記憶體電路用半導體晶片2M1、2M2為2個時之情形，圖14(b)表示記憶體電路用半導體晶片2M1為1個時之情形。任一情形下半導體晶片2C、2M1、2M2之背面之DAF5a均使用相同厚度之DAF。
於圖14(a)之構成中，將記憶體電路用半導體晶片設為1個時，控制電路用半導體晶片2C之下方之記憶體電路用半導體晶片之主面高度變低，因此，亦認為不會產生導線6c接觸到半導體晶片2C下方之記憶體電路用半導體晶片之主面角部之不良情形。
然而，實際上，於半導體裝置之總厚度不變之要求下，僅將記憶體電路用半導體晶片設為1個時，半導體裝置1A中之半導體晶片之數量會減少，密封體4(樹脂)之量會增多，故由製造步驟中之熱處理所引起之樹脂之硬化收縮或半導體晶片與樹脂之熱膨脹係數之差，而容易引起半導體裝置1A翹曲。因此，現狀是，如圖14(b)所示，使配線基板3之厚度大於圖14(a)時之厚度，藉此減少密封體4(樹脂)之量，以抑制或防止半導體裝置1A之翹曲。
然而，此時，必須在薄密封體4之範圍(厚度方向之範圍)內形成導線6c，因此如圖14(b)所示，若不採取任何方法，則導線6c接近並接觸到記憶體電路用半導體晶片2M1主面角部之不良可能性會增大。因此，在將記憶體電路用半導體晶片設為1個時，亦較好的是，使用與上述實施形態1中所說明之構成相同之構成。
圖15及圖16表示本實施形態3之半導體裝置1A之主要部分剖面圖。記憶體電路用半導體晶片2M1僅為1個。又，配線基板3之厚度大於上述實施形態1中所說明之厚度。藉此，可減少密封體4(樹脂)之量，故可抑制或防止半導體裝置1A之翹曲。
上層之控制電路用半導體晶片2C背面之DAF5c形成為，厚於下層之記憶體電路用半導體晶片2M1背面之DAF5a。藉此，與上述實施形態1相同，可減少導線6c接觸到半導體晶片2M1之主面角部之不良可能性。
又，上層之控制電路用半導體晶片2C之厚度形成為，厚於下層之記憶體電路用半導體晶片2M1。藉此，與上述實施形態1相同，可進一步減少導線6c接觸到半導體晶片2M1之主面角部之不良可能性。又，使半導體晶片2C變厚，可相應地減少密封體4(樹脂)之量，因此可進而抑制或防止半導體裝置1A之翹曲。
(實施形態4)
圖17係本實施形態4之半導體裝置之俯視圖，圖18係圖17之Y1－Y1線之剖面圖。再者，圖17中透視顯示半導體裝置之內部構成。
本實施形態4之半導體裝置1B係具有QFP(Quad Flat Package，四方扁平封裝)構成之半導體裝置，上述QFP構成係於導線架之接頭片(晶片墊)25a之主面上，將邏輯電路用半導體晶片2P及記憶體電路用半導體晶片2M3，以堆疊之狀態收納於相同密封體4內，整體建構微處理機系統。
本實施形態4中，使用導線架25作為晶片搭載構件。導線架25由例如銅或42合金等金屬薄板而構成，且具有接頭片25a、配置於上述接頭片25a外周之複數個引線25b、以及從接頭片25a之四角向外側延伸之懸垂接頭片之導線25c。
再者，引線25b一體地具有內部引線25bi及外部引線25bo。內部引線25bi係引線25b中密封體4內部之部分，外部引線25bo係引線25b中密封體4外部之部分。
於上述接頭片25a之主面上，利用DAF5a黏著並固定有半導體晶片(第1半導體晶片)2P。該半導體晶片2P例如係由以單晶矽而構成之平面正方形狀之半導體薄板所形成，且於其主面上，形成有例如微處理器或如ASIC(Application Specific Integrated Circuit，特殊應用積體電路)之邏輯電路。
於上述半導體晶片2P之外周附近，沿其外周配置有複數個墊。上述墊例如係利用鋁或鋁合金而形成。上述半導體晶片2P之複數個墊經由正接方式之複數個導線(第1接線)6d而電連接於內部引線25bi。導線6d例如係由金而形成。
於上述半導體晶片2P之主面上，利用DAF5c而黏著並固定有半導體晶片(第2半導體晶片)2M3。上述半導體晶片2M3例如係由以單晶矽而構成之平面長方形狀之半導體薄板所形成，且於其主面上，形成有例如16MG(兆字節)之SDRAM(Synchronous Dynamic Random Access Memory，同步動態隨機存取記憶體)。
上述半導體晶片2M3係偏向下層之半導體晶片2P之一邊而配置。於該半導體晶片2M3之單側長邊(沿著上述半導體晶片2P之一邊之邊)附近，沿著半導體晶片2M3之長邊並排配置有複數個墊。上述墊例如亦係由鋁或鋁合金而形成。上述半導體晶片2M3之複數個墊經由正接方式之複數個導線(第2接線)6e而電連接於內部引線25bi。導線6e例如係由金而形成。
又，本實施形態4中，上層之半導體晶片2M3之平面尺寸(縱及橫、面積)亦小於下層之半導體晶片2P之平面尺寸(縱及橫、面積)。本實施形態4中，連接於上層之半導體晶片2M3之導線6e並不會接觸到下層之半導體晶片2P之主面角部。然而，上述導線6e有時會接觸到連接於下層之半導體晶片2P之導線6d。
因此，本實施形態4中，亦使上層之半導體晶片2M3背面之DAF5c之厚度大於下層之半導體晶片2P背面之DAF5a之厚度。藉此，可增大導線6e之第1接合之高度，相應地可使上側之導線6e遠離下側之導線6d。因此，可減少上側之導線6e接觸到下側之導線6d之不良可能性，故可使半導體裝置1B之裝配性及可靠性提高。
又，導線6e之環部亦不會因上述構成而增高，因此，亦不會透見導線6e或者露出導線6e。故可使半導體裝置1B之良率提高。
而且，本實施形態4中，上層之半導體晶片2M3之厚度亦大於下層之半導體晶片2P之厚度。藉此，與上述實施形態1相同，可抑制半導體裝置1B之翹曲而不使半導體裝置1B變厚。
又，本實施形態4中，亦與上述實施形態1相同，即便使DAF5c變厚以於半導體晶片2M3之背面產生破裂，亦可減少或防止上述破裂產生之矽屑轉入DAF5c之背面，因此可減少或防止由矽屑導致之對半導體晶片2P主面之損傷不良。
又，藉由使DAF5c變厚，可與上述實施形態1相同，利用DAF5c來吸收半導體晶片2M3之翹曲。藉此，即便使半導體晶片2M3變厚，亦可擴大半導體晶片2M3與半導體晶片2P之密著面積，且可減小半導體晶片2M3外周部之間隙，因此可減少或防止半導體晶片2M3之剝離或破損。
以上，根據實施形態，具體說明由本發明者所完成之發明，但本發明並非限定於上述實施形態，當然可於不脫離上述要旨之範圍內進行各種變更。
例如於上述實施形態中，有說明應用於在半導體裝置之背面配置有複數個凸塊電極之封裝結構之半導體裝置之情形，但並非限定於此，亦可使用於例如在半導體裝置之背面將平坦之背面電極配置為陣列狀之LGA(Land Grid Array，接點柵格陣列)封裝結構之半導體裝置。
[產業上之可利用性]
本發明可應用於半導體裝置之製造業中。
1A,1B．．．半導體裝置
2C．．．半導體晶片(第2半導體晶片)
2M1,2M2．．．半導體晶片(第1半導體晶片)
2M3．．．半導體晶片(第2半導體晶片)
2P．．．半導體晶片(第1半導體晶片)
2W．．．半導體晶圓
3．．．配線基板(晶片搭載構件)
4．．．密封體
5a,5b．．．DAF(第1絕緣膜)
5c．．．DAF(第2絕緣膜)
6a,6b,6d．．．接線(第1接線)
6c,6e．．．接線(第2接線)
7a,7b．．．電極
8．．．凸塊電極
8a．．．電極
8b．．．凸塊部
9a,9b,9c．．．接合墊
15．．．磨石
16．．．晶圓黏膠片
17．．．晶圓環
18,19．．．切割刀
25．．．導線架
25a．．．接頭片
25b．．．引線
25bi．．．內部引線
25bo．．．外部引線
25c．．．懸垂接頭片之導線
100A．．．半導體晶片
100B．．．半導體晶片
101．．．搭載基板
SR．．．阻焊劑
圖1係作為本發明之一實施形態之半導體裝置之俯視圖。
圖2係圖1之X1－X1線之剖面圖。
圖3係圖1之X1－X1線之剖面圖，即，從與X1－X1線箭頭相反之方向觀察之剖面圖。
圖4係圖2之區域A之放大剖面圖。
圖5(a)係本發明者所研討之半導體裝置之主要部分剖面圖，圖5(b)係作為本發明實施形態之半導體裝置之主要部分剖面圖。
圖6係本發明者所研討之半導體裝置之主要部分剖面圖。
圖7(a)、圖7(b)係表示最上層半導體晶片之配置之半導體裝置之主要部分俯視圖。
圖8(a)、圖8(b)係薄半導體晶片與搭載其之搭載基板之剖面圖。
圖9(a)、(b)係厚半導體晶片與搭載其之搭載基板之剖面圖。
圖10係半導體晶片2C及搭載其之搭載基板之剖面圖。
圖11係作為本發明之一實施形態的半導體裝置之製造步驟之一例的說明圖。
圖12係繼圖11後的半導體裝置製造步驟之一例之說明圖。
圖13係作為本發明其他實施形態(實施形態2)之半導體裝置之主要部分剖面圖。
圖14(a)係記憶體電路用半導體晶片為2個時半導體裝置之主要部分剖面圖，圖14(b)係記憶體電路用半導體晶片為1個時半導體裝置之主要部分剖面圖。
圖15係作為本發明其他實施形態(實施形態3)之半導體裝置之主要部分剖面圖。
圖16係作為本發明其他實施形態(實施形態3)之半導體裝置之主要部分剖面圖。
圖17係本發明其他實施形態(實施形態4)之半導體裝置之俯視圖。
圖18係圖17之Y1－Y1線之剖面圖。
圖19係正接方式之接線形成之說明圖。
圖20係正接方式之接線形成之說明圖。
圖21係正接方式之接線形成之說明圖。
1A．．．半導體裝置
2C,2M1,2M2．．．半導體芯片
3．．．配線基板
4．．．密封體
5a,5b,5c．．．DFA
6a,6b．．．接合線
7a,8a．．．電極
8．．．凸塊電極
8b．．．凸塊部

Claims (8)

  1. 一種半導體裝置，其包括：配線基板，其具有一正面、形成於上述正面之複數個電極、電連接於上述複數電極之複數導線、與上述正面相反之背面、及形成於上述背面之複數個第二電極；第1半導體晶片，其具有一第1主面、形成於上述第1主面之複數個第1接合墊、與上述第1主面相反之第1背面；以使上述第1背面面對上述正面之方式，將上述第1半導體晶片介以具有黏著性之第1絕緣膜而搭載於上述配線基板之上述正面上；複數第1接線，其電連接上述第1半導體晶片之上述複數第1接合墊與上述配線基板之上述複數電極；第2半導體晶片，其具有一第2主面、形成於上述第2主面之複數個第2接合墊、與上述第2主面相反之第2背面；以使上述第2背面面對上述第1主面之方式，將上述第2半導體晶片介以具有黏著性之第2絕緣膜而搭載於上述第1半導體晶片之上述第1主面上，使得上述第1半導體晶片之上述第1接合墊於俯視時自上述第2半導體晶片露出；及複數第2接線，其電連接上述第2半導體晶片之上述複數第2接合墊與上述配線基板之上述複數電極；其中，於俯視時，上述第1半導體晶片之平面尺寸大於上述第2半導體晶片之平面尺寸； 上述第1絕緣膜具有一第1上表面、及與上述第1上表面相反之第1下表面；上述第2絕緣膜具有一第2上表面、及與上述第2上表面相反之第2下表面；上述第1絕緣膜之上述第1上表面係直接接觸於上述第1半導體晶片之上述第1背面；上述第1絕緣膜之上述第1下表面係直接接觸於上述配線基板；上述第2絕緣膜之上述第2上表面係直接接觸於上述第2半導體晶片之上述第2背面；上述第2絕緣膜之上述第2下表面係直接接觸於上述第1半導體晶片；上述第2絕緣膜之厚度大於上述第1絕緣膜之厚度；上述第1半導體晶片之平面形狀係包含一具有一對第1短邊與一對第1長邊之矩形；上述第2半導體晶片之平面形狀係包含一具有一對第2短邊與一對第2長邊之矩形；以使上述第2半導體晶片之上述一對第2長邊之一邊相鄰於上述第1半導體晶片之上述一對第1長邊之一邊且自其平移之方式，將上述第2半導體晶片搭載於上述第1半導體晶片上；上述配線基板之上述複數電極含有複數個第1電極及複數個第2電極，上述複數個第1電極沿著上述第1半導體晶片之上述一對第1長邊之一邊形成，上述複數個第2 電極沿著上述第1半導體晶片之上述一對第1短邊之一邊形成；上述第1半導體晶片之上述複數個第1接合墊沿著該第1半導體晶片之上述一對第1短邊之上述一邊形成；且上述第2半導體晶片之上述複數個第2接合墊沿著該第1半導體晶片之上述一對第1長邊之上述一邊形成。
  2. 如請求項1之半導體裝置，其中於上述第1半導體晶片中形成有記憶體電路，於上述第2半導體晶片中形成有邏輯電路。
  3. 如請求項1之半導體裝置，其中上述第2半導體晶片之厚度大於上述第1半導體晶片之厚度。
  4. 如請求項1之半導體裝置，其中於俯視時，上述第2半導體晶片被放置得較靠近上述一對第1長邊之上述一邊，而較不靠近上述一對第1長邊之另一邊。
  5. 如請求項4之半導體裝置，其中於俯視時，上述第1半導體晶片之上述複數個第1接合墊並非沿著上述第1半導體晶片之上述一對第1長邊之上述一邊形成。
  6. 如請求項5之半導體裝置，其中於俯視時，以將上述第2半導體晶片之每一邊放置至上述第1半導體晶片之相對應之邊之內部之方式，將上述第2半導體晶片搭載於上述第1半導體晶片上。
  7. 如請求項1之半導體裝置，其中上述第1半導體晶片係搭載於介以第3絕緣膜而搭載於上述配線基板之一第3半導體晶片上，且上述第2絕緣膜之厚度大於上述第3絕緣膜之厚度。
  8. 如請求項7之半導體裝置，其中上述第3半導體晶片與上述第1半導體晶片係同一種半導體晶片，且上述第3絕緣膜之厚度與上述第1絕緣膜之厚度相同。
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