JP4408042B2 - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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Description
なお、前記半導体薄膜を用いて集積回路を形成した半導体素子の膜厚は、50μm以下、好ましくは0.1μm以上1μm以下である。
本実施の形態では、本発明の半導体装置について図1を用いて示す。
本実施の形態では、実施の形態1で述べた半導体装置の作製方法に関して述べる。本実施の形態の半導体装置は、全ての半導体素子がフェイスアップ形態である。
本実施の形態では、実施の形態1及び実施の形態2と異なる構造の半導体装置に関して述べる。本実施の形態では、第1の半導体素子がフリップチップ形態(フェイスダウン形態)である点が実施の形態2と異なる。
本実施の形態では、実施の形態1〜実施の形態3と異なる構造の半導体装置の作製方法に関して述べる。本実施の形態では、全ての集積回路がフリップチップ形態(フェイスダウン形態)である点が実施の形態2及び実施の形態3と異なる。
実施の形態1乃至実施の形態4において、第1の半導体素子と第2の半導体素子の積層順序が異なる半導体装置について示す。
図9に示すように、絶縁性基板(インターポーザ)101上に、配線層102及び熱圧着シート等の接着層103を介して、半導体薄膜を用いて集積回路を形成した半導体素子106が設けられ、該半導体素子106上に熱圧着シート等の接着層105を介して、半導体基板を用いて集積回路を形成した半導体素子104が設けられている。
実施の形態2乃至実施形態5において、また、接着剤407、接着剤1407としては、有機材料からなる粘着剤を用いることができる。有機材料からなる粘着剤としては、反応剥離型粘着剤、熱剥離型粘着剤、紫外線剥離型粘着剤等の光剥離型粘着剤、嫌気剥離型粘着剤などの各種剥離型粘着剤が挙げられる。また、剥離可能な粘着剤で形成される粘着層を両面に有する部材(代表的には両面テープ、両面シート)を用いてもよい。
Claims (22)
- 絶縁性基板上に配線部と、第1の半導体素子と、第2の半導体素子とを順に積層した半導体装置の作製方法であって、
半導体基板を用いて前記第1の半導体素子の集積回路を形成し、前記絶縁性基板上に前記配線部を介して前記第1の半導体素子を接着する第1の工程と、
第1の基板表面に、金属膜と、金属酸化膜と、絶縁膜と、半導体薄膜とを順に積層し、加熱処理を施して前記金属酸化膜と前記半導体薄膜とを結晶化した後、該結晶化された半導体薄膜を用いて前記第2の半導体素子の集積回路を形成し、前記第1の基板と向かい合うように、前記第2の半導体素子上に第2の基板を第1の接着剤を用いて貼り合わせ、前記金属膜と前記結晶化された金属酸化膜との間、前記結晶化された金属酸化膜と前記絶縁膜との間、又は前記結晶化された金属酸化膜において物理的手段により剥離する第2の工程と、
前記第2の工程の後、前記第1の半導体素子上に、前記第2の半導体素子を接着し、前記第1の接着剤を除去して前記第2の基板を前記第2の半導体素子から剥離する第3の工程と、
前記第3の工程の後、前記第1の半導体素子と前記配線部とを電気的に接続する第4の工程と、
前記第4の工程の後、前記第2の半導体素子と前記配線部とを電気的に接続する第5の工程とを有することを特徴とする半導体装置の作製方法。 - 絶縁性基板上に配線部と、第1の半導体素子と、第2の半導体素子とを順に積層した半導体装置の作製方法であって、
半導体基板を用いて前記第1の半導体素子の集積回路を形成し、前記絶縁性基板上に形成された前記配線部と前記第1の半導体素子と電気的に接続する第1の工程と、
第1の基板表面に、金属膜と、金属酸化膜と、絶縁膜と、半導体薄膜とを順に積層し、加熱処理を施して前記金属酸化膜と前記半導体薄膜とを結晶化した後、該結晶化された半導体薄膜を用いて前記第2の半導体素子の集積回路を形成し、前記第1の基板と向かい合うように、前記第2の半導体素子上に第2の基板を第1の接着剤を用いて貼り合わせ、前記金属膜と前記結晶化された金属酸化膜との間、前記結晶化された金属酸化膜と前記絶縁膜との間、又は前記結晶化された金属酸化膜において物理的手段により剥離する第2の工程と、
前記第2の工程の後、前記第1の半導体素子上に、前記第2の半導体素子を接着し、前記第1の接着剤を除去して前記第2の基板を前記第2の半導体素子から剥離する第3の工程と、
前記第3の工程の後、前記第2の半導体素子と前記配線部とを電気的に接続する第4の工程とを有することを特徴とする半導体装置の作製方法。 - 絶縁性基板上に第1の配線部と、第1の半導体素子と、第2の配線部と、第2の半導体素子とを順に積層した半導体装置の作製方法であって、
半導体基板を用いて前記第1の半導体素子の集積回路を形成し、前記絶縁性基板上に形成された前記第1の配線部と、前記第1の半導体素子とを電気的に接続した後、前記第1の半導体素子上に絶縁膜を介して前記第2の配線部を形成する第1の工程と、
第1の基板表面に、金属膜と、金属酸化膜と、絶縁膜と、半導体薄膜とを順に積層し、加熱処理を施して前記金属酸化膜と前記半導体薄膜とを結晶化した後、該結晶化された半導体薄膜を用いて前記第2の半導体素子の集積回路を形成し、前記第1の基板と向かい合うように、前記第2の半導体素子上に第2の基板を第1の接着剤を用いて貼り合わせ、前記金属膜と前記結晶化された金属酸化膜との間、前記結晶化された金属酸化膜と前記絶縁膜との間、又は前記結晶化された金属酸化膜において物理的手段により剥離する第2の工程と、
前記第2の工程の後、前記第2の半導体素子に前記第2の基板と向かい合うように第3の基板を接着し、前記第1の接着剤を除去して前記第2の基板を前記第2の半導体素子から剥離する第3の工程と、
前記第3の工程の後、前記第2の配線部と前記第2の半導体素子とを電気的に接続する第4の工程とを有することを特徴とする半導体装置の作製方法。 - 絶縁性基板上に配線部と、第2の半導体素子と、第1の半導体素子とを順に積層した半導体装置の作製方法であって、
半導体基板を用いて前記第1の半導体素子の集積回路を形成する第1の工程と、
第1の基板表面に、金属膜と、金属酸化膜と、絶縁膜と、半導体薄膜とを順に積層し、加熱処理を施して前記金属酸化膜と前記半導体薄膜とを結晶化した後、該結晶化された半導体薄膜を用いて前記第2の半導体素子の集積回路を形成し、前記第1の基板と向かい合うように、前記第2の半導体素子上に第2の基板を第1の接着剤を用いて貼り合わせ、前記金属膜と前記結晶化された金属酸化膜との間、前記結晶化された金属酸化膜と前記絶縁膜との間、又は前記結晶化された金属酸化膜において物理的手段により剥離する第2の工程と、
前記第2の工程の後、前記第1の半導体素子上に、前記第2の半導体素子を接着し、前記第1の接着剤を除去して前記第2の基板を前記第2の半導体素子から剥離する第3の工程と、
前記第3の工程の後、前記第2の半導体素子と前記配線部とを電気的に接続する第4の工程と、
前記第4の工程の後、前記第1の半導体素子と前記配線部とを電気的に接続する第5の工程とを有することを特徴とする半導体装置の作製方法。 - 絶縁性基板上に第1の配線部と、第2の半導体素子と、第2の配線部と、第1の半導体素子とを順に積層した半導体装置の作製方法であって、
半導体基板を用いて前記第1の半導体素子の集積回路を形成する第1の工程と、
第1の基板表面に、金属膜と、金属酸化膜と、絶縁膜と、半導体薄膜とを順に積層し、加熱処理を施して前記金属酸化膜と前記半導体薄膜とを結晶化した後、該結晶化された半導体薄膜を用いて前記第2の半導体素子の集積回路を形成し、前記第1の基板と向かい合うように、前記第2の半導体素子上に第2の基板を第1の接着剤を用いて貼り合わせ、前記金属膜と前記結晶化された金属酸化膜との間、前記結晶化された金属酸化膜と前記絶縁膜との間、又は前記結晶化された金属酸化膜において物理的手段により剥離する第2の工程と、
前記第2の工程の後、前記第2の半導体素子に前記第2の基板と向かい合うように第3の基板を接着し、前記第1の接着剤を除去して前記第2の基板を前記第2の半導体素子から剥離する第3の工程と、
前記第3の工程の後、前記絶縁性基板に形成された前記第1の配線部と、前記第2の半導体素子とを電気的に接続した後、前記第2の半導体素子上に前記第3の基板を介して前記第2の配線部を形成する第4の工程と、
前記第4の工程の後、前記第2の配線部と前記第1の半導体素子とを電気的に接続する第5の工程とを有することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項5のいずれか一項において、前記半導体基板は、単結晶シリコン基板又は化合物半導体基板であることを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項5のいずれか一項において、前記半導体基板は、N型若しくはP型の単結晶シリコン基板、GaAs基板、InP基板、GaN基板、SiC基板、ZnSe基板、GaP基板、又はInSb基板であることを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項7のいずれか一項において、前記半導体薄膜は、シリコンを含む薄膜であることを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項8のいずれか一項において、前記第1の半導体素子は、電源回路、送受信回路、メモリ、又は音声処理回路のアンプを含むことを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項9のいずれか一項において、前記第2の半導体素子は、画素部の走査線駆動回路、信号線駆動回路、コントローラ、CPU、又は音声処理回路のコンバータを含むことを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項10のいずれか一項において、前記第1の接着剤は、剥離可能な粘着剤であることを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項11のいずれか一項において、前記絶縁性基板は、ポリイミド、アルミナ、セラミック、又はガラスエポキシ樹脂で形成されていることを特徴とする半導体装置の作製方法。
- 半導体基板を用いて集積回路を形成した半導体素子と、半導体薄膜を用いて集積回路を形成した半導体素子とが絶縁性基板上に有機樹脂又は接着剤を介して積層され、
前記半導体基板を用いて集積回路を形成した半導体素子は、前記半導体薄膜を用いて集積回路を形成した半導体素子と前記絶縁性基板との間に形成されていることを特徴とする半導体装置。 - 半導体基板を用いて集積回路を形成した半導体素子と、半導体薄膜を用いて集積回路を形成した半導体素子とが絶縁性基板上に有機樹脂又は接着剤を介して積層され、
前記半導体薄膜を用いて集積回路を形成した半導体素子は、前記半導体基板を用いて集積回路を形成した半導体素子と前記絶縁性基板との間に形成されていることを特徴とする半導体装置。 - 請求項13又は請求項14において、前記半導体薄膜を用いて集積回路を形成した半導体素子の膜厚は、50μm以下であることを特徴とする半導体装置。
- 請求項13又は請求項14において、前記半導体薄膜を用いて集積回路を形成した半導体素子の膜厚は、0.1μm以上1μm以下であることを特徴とする半導体装置。
- 請求項13乃至請求項16のいずれか一項において、前記半導体基板は、単結晶シリコン基板又は化合物半導体基板であることを特徴とする半導体装置。
- 請求項13乃至請求項16のいずれか一項において、前記半導体基板は、N型若しくはP型の単結晶シリコン基板、GaAs基板、InP基板、GaN基板、SiC基板、ZnSe基板、GaP基板、又はInSb基板であることを特徴とする半導体装置。
- 請求項13乃至請求項18のいずれか一項において、前記半導体薄膜は、シリコンを含む薄膜であることを特徴とする半導体装置。
- 請求項13乃至請求項19のいずれか一項において、前記半導体基板を用いて集積回路を形成した半導体素子は、電源回路、送受信回路、メモリ、又は音声処理回路のアンプを含むことを特徴とする半導体装置。
- 請求項13乃至請求項20のいずれか一項において、前記半導体薄膜を用いて集積回路を形成した半導体素子は、画素部の走査線駆動回路、信号線駆動回路、コントローラ、CPU、又は音声処理回路のコンバータを含むことを特徴とする半導体装置。
- 請求項13乃至請求項21のいずれか一項において、前記絶縁性基板は、ポリイミド、アルミナ、セラミック、又はガラスエポキシ樹脂で形成されていることを特徴とする半導体装置。
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