WO2008152730A1 - 積層型パッケージ及びその形成方法 - Google Patents

積層型パッケージ及びその形成方法 Download PDF

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Publication number
WO2008152730A1
WO2008152730A1 PCT/JP2007/062119 JP2007062119W WO2008152730A1 WO 2008152730 A1 WO2008152730 A1 WO 2008152730A1 JP 2007062119 W JP2007062119 W JP 2007062119W WO 2008152730 A1 WO2008152730 A1 WO 2008152730A1
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semiconductor chip
bonded
forming
same
semiconductor chips
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PCT/JP2007/062119
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English (en)
French (fr)
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Masashi Hasegawa
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Kabushiki Kaisha Nihon Micronics
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Priority to PCT/JP2007/062119 priority Critical patent/WO2008152730A1/ja
Priority to JP2009519123A priority patent/JPWO2008152730A1/ja
Publication of WO2008152730A1 publication Critical patent/WO2008152730A1/ja

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Abstract

　半導体チップにおける接続用端子の位置の制約や、各半導体チップに対する回路の割り当てに対する制約を、小さなものとすることができる半導体チップモジュールを提供する。 　複数の半導体チップを重ね合わせて結合した半導体チップモジュールに関する。そして、互いに結合される上下の層の半導体チップで段差部分を生じるように、少なくとも一部の上下の層の半導体チップが結合されている。また、各層の半導体チップの間の配線は、ミスト状の配線材料をノズルより噴射して直接形成されている。
PCT/JP2007/062119 2007-06-15 2007-06-15 積層型パッケージ及びその形成方法 WO2008152730A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217383A (ja) * 2000-01-31 2001-08-10 Hitachi Ltd 半導体装置およびその製造方法
JP2003303937A (ja) * 2002-04-05 2003-10-24 Nec Electronics Corp 半導体装置及びその製造方法
JP2004063569A (ja) * 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004158747A (ja) * 2002-11-08 2004-06-03 Sumitomo Bakelite Co Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217383A (ja) * 2000-01-31 2001-08-10 Hitachi Ltd 半導体装置およびその製造方法
JP2003303937A (ja) * 2002-04-05 2003-10-24 Nec Electronics Corp 半導体装置及びその製造方法
JP2004063569A (ja) * 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004158747A (ja) * 2002-11-08 2004-06-03 Sumitomo Bakelite Co Ltd 半導体装置の製造方法

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