TW201810260A - 非揮發性記憶體的驅動電路 - Google Patents
非揮發性記憶體的驅動電路 Download PDFInfo
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Abstract
一種驅動電路,包括:一第一驅動器、一切換電路與一第二驅動器。第一驅動器接收一輸入信號與一反相的輸入信號,並產生一驅動信號。切換電路,接收該驅動信號與一第一模式信號,並於一輸出端產生一輸出信號。第二驅動器,連接於該輸出端。
Description
本發明是有關於一種驅動電路,且特別是有關於一種運用於非揮發性記憶體的驅動電路。
眾所周知,非揮發性記憶體可在電源消失之後,仍可保存資料,因此非揮發性記憶體已經廣泛的運用於電子產品中。再者,非揮發性記憶體中包括多個非揮發性記憶胞(non-volatile cell)排列而成非揮發性記憶胞陣列(non-volatile cell array),而每個非揮發性記憶胞中皆包含一浮動閘電晶體(floating gate transistor)。
請參照第1圖,其所繪示為揮發性記憶體示意圖。非揮發性記憶體中包括一非揮發性記憶胞陣列110與一驅動電路(driving circuit)120。其中,驅動電路120連接至非揮發性記憶胞陣列110,且驅動電路120可在各種運作模式下提供各種驅動信號OUT至非揮發性記憶胞陣列110。
舉例來說,根據非揮發性記憶胞陣列的運作模式,驅動電路120提供適當的驅動信號OUT來操控非揮發性記憶胞陣
列110進行讀取運作(read operation)或者編程運作(program operation)。
本發明之主要目的係提出一種非揮發性記憶體中的驅動電路,可在高溫的環境下,穩定地提供驅動信號至非揮發性記憶胞陣列。
本發明係有關於一種驅動電路,包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2;一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至一第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;其中,該節點b2產生一驅動信號;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓、汲極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極
連接至一第四供應電壓;一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓;一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該第四節點;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該第二節點。
本發明係有關於一種驅動電路,包括:一第一驅動器,包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2;一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至一第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓(Vpp3)、汲
極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極連接至一第四供應電壓;一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓;一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該第四節點;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該第二節點;一第一切換電路,連接於該節點b2與一第一輸出端之間;以及一第二驅動器,連接於該第一輸出端,且該第一輸出端產生一第一輸出信號。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:
110‧‧‧非揮發性記憶胞陣列
120、200、300‧‧‧驅動電路
310、320、430、440‧‧‧偏壓電路
400、460、465‧‧‧驅動器
450、455‧‧‧切換電路
第1圖所所繪示為揮發性記憶體示意圖。
第2圖所繪示為本發明的第一實施例非揮發性記憶體的驅動電路。
第3A圖所繪示為本發明的第二實施例運用於非揮發性記憶體的驅動電路。
第3B圖所繪示為本發明第二實施例中的第一偏壓電路。
第3C圖所繪示為本發明第二實施例中的第二偏壓電路。
第4A圖所繪示為本發明的第三實施例運用於非揮發性記憶體的驅動電路。
第4B圖所繪示為本發明第三實施例中的第三偏壓電路。
第4C圖所繪示為本發明第三實施例中的第四偏壓電路。
第4D圖所繪示為本發明第三實施例驅動電路運作於各種模式時的真值表。
請參照第2圖,其所繪示為本發明的第一實施例非揮發性記憶體的驅動電路。驅動電路200可提供一驅動信號OUT至非揮發性記憶胞陣列(未繪示)。
驅動電路200包括:包括多個p型電晶體m1~m8,以及多個n型電晶體m9~m12。其中,電晶體m1~m4的體極(body terminal)連接至第一供應電壓Vpp1,電晶體m9~m12的體極連接至第四供應電壓Vnn,第一供應電壓Vpp1有最高的電壓值,第四供應電壓Vnn有最低的電壓值。
電晶體m1源極連接至第一供應電壓Vpp1、閘極連接至節點b2、汲極連接至節點a1;電晶體m2源極連接至第一供應電壓Vpp1、閘極連接至節點a2、汲極連接至節點b1;電晶體m3源極連接至第二供應電壓Vpp2、閘極與汲極連接至節點a1;電晶體m4源極連接至第二供應電壓Vpp2、閘極與汲極連接至節
點b1;電晶體m5源極與體極連接至節點a1、閘極連接至第二供應電壓Vpp2、汲極連接至節點a2;電晶體m6源極與體極連接至節點b1、閘極連接至第二供應電壓Vpp2、汲極連接至節點b2;其中,第二供應電壓Vpp2小於等於第一供應電壓Vpp1,且節點b2可產生驅動信號OUT。
再者,電晶體m7源極與體極連接至節點a2、閘極連接至第三供應電壓Vpp3、汲極連接至節點a3;電晶體m8源極與體極連接至節點b2、閘極連接至第三供應電壓Vpp3、汲極連接至節點b3;其中,第三供應電壓Vpp3小於等於第二供應電壓Vpp2。
電晶體m9汲極連接至節點a3、閘極連接至第三供應電壓Vpp3、源極連接至節點a4;電晶體m10汲極連接至節點b3、閘極連接至第三供應電壓Vpp3、源極連接至節點b4;電晶體m11汲極連接至節點a4、閘極連接至輸入信號IN、源極連接至第四供電壓Vnn;電晶體m12汲極連接至節點b4、閘極連接至反相的輸入信號INb、源極連接至第五供應電壓Vpr。其中,第五供應電壓Vpr小於等於第三供應電壓Vpp3,且第五供應電壓Vpr大於等於第四供應電壓Vnn。
舉例來說,第一供應電壓Vpp1為為非揮發性記憶體的編程電壓(program voltage),例如9V。第二供應電壓Vpp2為6V。第三供應電壓Vpp3為4.5V。第四供應電壓Vnn為0V。第五供應電壓Vpr為非揮發性記憶體的讀取電壓,例如1.5V。
基本上,第一實施例的驅動電路200操作在高溫的環境時,例如150℃~250℃。由於在操作的過程,節點a2或者b2可能會呈現浮接的狀態。舉例來說,於節點b2呈現浮接狀態時,電晶體m6的源極與汲極之間的電壓差(voltage difference)可能超過其安全運作區(safe operation area,簡稱SOA)。同理,電晶體m1的源極與閘極之間的電壓差也可能超過其安全運作區。另外,當電晶體m1、m6超過安全運作區後,會導致漏電流(leakage current)增加,進而影響供應電壓與驅動信號OUT,並使得非揮發性記憶胞陣列無法正常運作。
請參照第3A圖,其所繪示為本發明的第二實施例運用於非揮發性記憶體的驅動電路。與第一實施例的差異在於,第二實施例的驅動電路300中,增加一第一偏壓電路310與第二偏壓電路320分別連接至節點a2與b2。第一偏壓電路310可提供一特定電壓於節點a2,使得節點a2不會呈現浮接狀態。同理,第二偏壓電路320可提供一特定電壓於節點b2,使得節點b2不會呈現浮接狀態。
請參照第3B圖,其所繪示為本發明第二實施例中的第一偏壓電路。請參照第3C圖,其所繪示為本發明第二實施例中的第二偏壓電路。
第一偏壓電路310:包括p型電晶體m13與m14。電晶體m13源極連接至節點a2,閘極接收控制信號C1;以及,電晶體m14源極連接至電晶體m13汲極,閘極接收控制信號C1,
汲極接收特定電壓B1。根據本發明的實施例,控制信號C1為節點a3上的電壓,特定電壓B1為第三供應電壓Vpp3。亦即,電晶體m13與m14的閘極連接至節點a3,電晶體m14汲極連接至電晶體m9的閘極。因此,第一偏壓電路310可提供第三供應電壓Vpp3於節點a2。
第二偏壓電路320:包括p型電晶體m15與m16。電晶體m15源極連接至節點b2,閘極接收控制信號D1;以及,電晶體m16源極連接至電晶體m15汲極,閘極接收控制信號D1,汲極接收特定電壓B1。根據本發明的實施例,控制信號D1為節點b3上的電壓,特定電壓B1為第三供應電壓Vpp3。亦即,電晶體m15與m16的閘極連接至節點b3,電晶體m16汲極連接至電晶體m10的閘極。因此,第二偏壓電路320可提供第三供應電壓Vpp3於節點b2。
另外,在電晶體m13~m16可以順利運作的考量下,電晶體m13的體極與源極可以相互連接,而電晶體m14~m16也是相同的連接方式。或者,可將電晶體m13~m16的體極連接至第一供應電壓Vpp1或者其他的偏壓電壓(biasing voltage)。
以下以節點a2來做說明,當輸入信號IN為高邏輯準位且反相的輸入信號INb為低邏輯準位時,節點a3為第四供應電壓Vnn,亦即控制信號C1為第四供應電壓Vnn。再者,節點b2與b3為第一供應電壓Vpp1,亦即控制信號D1為第一供應電壓Vpp1,第二偏壓電路320不會運作。再者,由於控制信號
C1為第四供應電壓Vnn,使得第一偏壓電路310中電晶體m13與m14開啟,並且第三供應電壓Vpp3提供至節點a2。其中,高邏輯準位為Vdd,例如3.3V,低邏輯準位為接地電壓,例如0V。
反之,當輸入信號IN為低邏輯準位且反相的輸入信號INb為高邏輯準位時,節點a2與a3為第一供應電壓Vpp1,第一偏壓電路310不會運作。再者,節點b3為第五供應電壓Vpr,使得第二偏壓電路320中電晶體m15與m16開啟,節點b2即為第三供應電壓Vpp3。
由以上的說明可知,第二實施例的驅動電路300可以使得節點a2不會呈現浮接狀態。同理,第二實施例的驅動電路300也可以使得節點b2不會呈現浮接狀態。
請參照第4A圖,其所繪示為本發明的第三實施例運用於非揮發性記憶體的驅動電路。第三實施例的驅動電路包括一第一驅動器(driver)400、一第二驅動器460、一第三驅動器465、一第一切換電路(switching circuit)450與一第二切換電路455。其中,第一驅動器400與第二實施例之驅動電路300完全相同,此處不再贅述。
相較於第二實施例,第三實施例增加了第一切換電路450、第二切換電路455、第二驅動器460與第三驅動器465。其中,第一切換電路450連接於節點b2與一第一輸出端之間,且第一輸出端可產生第一輸出信號OUT1。第二切換電路455連接於節點b2與一第二輸出端之間,且第二輸出端可產生第二輸
出信號OUT2。再者,第二驅動器460連接至第一輸出端;第三驅動器465連接至第二輸出端。
第一切換電路450中,電晶體m17~m19係作為開關的用途。其中,電晶體m17源極接收驅動信號OUT、體極連接至源極、閘極接收模式信號(mode signal)M1、汲極連接至節點x1;電晶體m18源極連接至節點x1、體極連接至源極、閘極接收第二供應電壓Vpp2、汲極連接至節點x2;電晶體m19源極連接至節點x2、體極連接至源極、閘極接第三供應電壓Vpp3、汲極連接至第一輸出端以產生第一輸出信號OUT1。
第二驅動器460包括n型電晶體m20~m22,電晶體m20~m22的體極皆連接至第四供應電壓Vnn。電晶體m20汲極連接至第一輸出端以產生第一輸出信號OUT1,閘極接收第三供應電壓Vpp3;電晶體m21汲極連接至電晶體m20源極、閘極接收反相的輸入信號INb、源極連接至第五供應電壓Vpr;電晶體m22極汲極連接至電晶體m20源極、閘極接收模式信號M2、源極連接至第五供應電壓Vpr。
同理,為了防止節點x1與x2在驅動電路運作的過程呈現浮接狀態,本發明更提供一第三偏壓電路430連接於節點x1,以及提供一第四偏壓電路440連接於節點x2。
第二切換電路455中,電晶體m26係作為開關的用途。其中,電晶體m26源極接收驅動信號OUT、體極連接至源極、閘極接收第三供應電壓Vpp3、汲極連接至第二輸出端以產生第二
輸出信號OUT2。
第三驅動器465包括n型電晶體m27、m28,電晶體m27、28的體極皆連接至第四供應電壓Vnn。電晶體m27汲極連接至第二輸出端以產生第二輸出信號OUT2,閘極接收第三供應電壓Vpp3;電晶體m28汲極連接至電晶體m27源極、閘極接收反相的輸入信號INb、源極連接至第五供應電壓Vpr。
請參照第4B圖,其所繪示為本發明第三實施例中的第三偏壓電路。請參照第4C圖,其所繪示為本發明第三實施例中的第四偏壓電路。
第三偏壓電路430:包括p型電晶體m23。電晶體m23源極連接接收特定電壓B2、閘極與汲極皆連接至節點x1,體極連接至第一供應電壓Vpp1。根據本發明的實施例,特定電壓B2為第二供應電壓Vpp2。因此,第三偏壓電路430可供應(Vpp2-|Vthp|)至節點x1。其中,Vthp為電晶體m23的臨限電壓(threshold voltage)。
第四偏壓電路440:包括p型電晶體m24與m25。電晶體m24源極連接至節點x2,閘極接收第一輸出信號OUT1;以及,電晶體m25源極連接至電晶體m24汲極,閘極接收第一輸出信號OUT1,汲極接收特定電壓B3。根據本發明的實施例,特定電壓B3為第三供應電壓Vpp3。因此,第四偏壓電路440可提供第三供應電壓Vpp3於節點x2。
請參照第4D圖,其所繪示為本發明第三實施例驅
動電路運作於各種模式時的真值表。
其中,於第一模式時,模式信號M1為Vpp1,模式信號M2為Vdd;於第二模式時,模式信號M1與M2為0V;或者,於第二模式時,模式信號M1也可以是第三供應電壓Vp3用以降低電晶體m17的電壓應力(stress)。
在第一情況下,驅動電路處於第一模式、輸入信號IN為Vdd且反相的輸入信號INb為0V時,節點a2為第三供應電壓Vpp3、節點b2為第一供應電壓Vpp1、節點x1為(Vpp2-|Vthp|)、x2為第三供應電壓Vpp3、第一輸出信號OUT1為第五供應電壓Vpr。且第二輸出信號OUT2為第一供應電壓Vp1。
在第二情況下,驅動電路處於第二模式、輸入信號IN為Vdd且反相的輸入信號INb為0V時,節點a2為第三供應電壓Vpp3、節點b2為第一供應電壓Vpp1、節點x1、x2與第一輸出信號OUT1皆為第一供應電壓Vpp1。且第二輸出信號OUT2為第一供應電壓Vp1。
在第三情況下,驅動電路處於第一模式、輸入信號IN為0V且反相的輸入信號INb為Vdd時,節點a2為第一供應電壓Vpp1、節點b2為第三供應電壓Vpp3、節點x1為(Vpp2-|Vthp|)、x2為第三供應電壓Vpp3、第一輸出信號OUT1為第五供應電壓Vpr。且第二輸出信號OUT2為第五供應電壓Vpr。
在第四情況下,驅動電路處於第二模式、輸入信號IN為0V且反相的輸入信號INb為Vdd時,節點a2為第一供應
電壓Vpp1、節點b2為第三供應電壓Vpp3、節點x1為(Vpp2-|Vthp|)、節點x2為第三供應電壓Vpp3,第一輸出信號OUT1為第五供應電壓Vpr。且第二輸出信號OUT2為第五供應電壓Vpr。
由以上的說明可知,本發明第二實施例與第三實施例的驅動電路確實可以讓節點不會呈現浮接狀態。因此,第二實施例與第三實施例的驅動電路可以穩定地操作在高溫的環境,並使得非揮發性記憶胞陣列正常運作。
再者,在此技術領域的技術人員也可以對本發明進行修改並達成本發明所教示的功能。舉例來說,驅動電路可以修改為僅有第一驅動器、第二驅動器與第一切換電路。而驅動電路僅輸出第一輸出信號OUT1。而省略輸出第二驅動信號OUT2的第三驅動器與第二切換電路。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
310、320、430、440‧‧‧偏壓電路
400、460、465‧‧‧驅動器
450、455‧‧‧切換電路
Claims (19)
- 一種驅動電路,連接至一非揮發性記憶胞陣列,該驅動電路包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2;一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極連接至一第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極連接至該第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至該第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;其中,該節點b2產生一驅動信號;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓、汲極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極連接至一第四供應電壓; 一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓;一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該節點a2;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該節點b2。
- 如申請專利範圍第1項所述之驅動電路,其中該第一偏壓電路包括:一第十三電晶體,閘極連接至該節點a3、源極連接至該節點a2;以及一第十四電晶體,源極連接至該第十三電晶體的汲極、閘極連接至該節點a3、汲極連接至該第三供應電壓。
- 如申請專利範圍第2項所述之驅動電路,其中該第二偏壓電路包括:一第十五電晶體,閘極連接至該節點b3、源極連接至該節點 b2;以及一第十六電晶體,源極連接至該第十五電晶體的汲極、閘極連接至該節點b3、汲極連接至該第三供應電壓。
- 如申請專利範圍第3項所述之驅動電路,其中該第十三電晶體的體極與源極相互連接,該第十四電晶體的體極與源極相互連接,該第十五電晶體的體極與源極相互連接,該第十六電晶體的體極與源極相互連接。
- 如申請專利範圍第3項所述之驅動電路,其中該第十三電晶體、該第十四電晶體、該第十五電晶體與該第十六電晶體的體極連接至一偏壓電壓。
- 如申請專利範圍第1項所述之驅動電路,其中該第一供應電壓大於等於該第二供應電壓,該第二供應電壓大於等於該第三供應電壓,該第三供應電壓大於該第四供應電壓。
- 一種驅動電路,連接至一非揮發性記憶胞陣列,該驅動電路包括:一第一驅動器,包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2; 一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極連接至一第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極連接至該第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至該第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓、汲極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極連接至一第四供應電壓;一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓; 一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該節點a2;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該節點b2;一第一切換電路,連接於該節點b2與一第一輸出端之間;以及一第二驅動器,連接於該第一輸出端,且該第一輸出端產生一第一輸出信號。
- 如申請專利範圍第7項所述之驅動電路,其中該第一偏壓電路包括:一第十三電晶體,閘極連接至該節點a3、源極連接至該節點a2;以及一第十四電晶體,源極連接至該第十三電晶體的汲極、閘極連接至該節點a3、汲極連接至該第三供應電壓。
- 如申請專利範圍第8項所述之驅動電路,其中該第二偏壓電路包括:一第十五電晶體,閘極連接至該節點b3、源極連接至該節點 b2;以及一第十六電晶體,源極連接至該第十五電晶體的汲極、閘極連接至該節點b3、源極連接至該第三供應電壓。
- 如申請專利範圍第9項所述之驅動電路,其中該第十三電晶體的體極與源極相互連接,該第十四電晶體的體極與源極相互連接,該第十五電晶體的體極與源極相互連接,該第十六電晶體的體極與源極相互連接。
- 如申請專利範圍第9項所述之驅動電路,其中該第十三電晶體、該第十四電晶體、該第十五電晶體與該第十六電晶體的體極連接至一偏壓電壓。
- 如申請專利範圍第7項所述之驅動電路,其中該第一供應電壓大於等於該第二供應電壓,該第二供應電壓大於等於該第三供應電壓,該第三供應電壓大於該第四供應電壓。
- 如申請專利範圍第7項所述之驅動電路,其中該第一切換電路包括:一第十七電晶體,其源極與體極連接至該節點b2、閘極接收一第一模式信號、汲極連接至一節點x1;一第十八電晶體,其源極與體極連接至該節點x1、閘極接收 該第二供應電壓、汲極連接至一節點x2;一第十九電晶體,其源極與體極連接至該節點x2、閘極接收該第三供應電壓、汲極連接至該第一輸出端;一第三偏壓電路,連接至該節點x1;以及一第四偏壓電路,連接至該節點x2。
- 如申請專利範圍第13項所述之驅動電路,其中該第二驅動器包括:一第二十電晶體,汲極連接至該第一輸出端、閘極連接至該第三供應電壓、體極連接至該第四供應電壓;一第二十一電晶體,汲極連接至該第二十電晶體的源極、閘極接收該反相的輸入信號、體極連接至該第四供應電壓、源極連接至該第五供應電壓;以及一第二十二電晶體,汲極連接至該第二十電晶體的源極、閘極接收一第二模式信號、體極連接至該第四供應電壓、源極連接至該第五供應電壓。
- 如申請專利範圍第13項所述之驅動電路,其中該第三偏壓電路包括:一第二十三電晶體,源極連接至該第二供應電壓、閘極與汲極連接至該節點x1、體極連接至該第一供應電壓。
- 如申請專利範圍第15項所述之驅動電路,其中該第四偏壓電路包括:一第二十四電晶體,源極連接至該節點x2、閘極連接至該第一輸出端;一第二十五電晶體,源極連接至該第二十四電晶體的汲極、閘極連接至該第一輸出端、汲極連接至該第三供應電壓。
- 如申請專利範圍第7項所述之驅動電路,更包括:一第二切換電路,連接於該節點b2與一第二輸出端之間;以及一第三驅動器,連接於該第二輸出端,且該第二輸出端產生一第二輸出信號。
- 如申請專利範圍第17項所述之驅動電路,其中該第二切換電路包括:一第二十六電晶體,其源極與體極連接至該節點b2、閘極接收該第三供應電壓、汲極連接至該第二輸出端。
- 如申請專利範圍第17項所述之驅動電路,其中該第三驅動器包括:一第二十七電晶體,汲極連接至該第二輸出端、閘極連接至該第三供應電壓、體極連接至該第四供應電壓; 一第二十八電晶體,汲極連接至該第二十七電晶體的源極、閘極接收該反相的輸入信號、體極連接至該第四供應電壓、源極連接至該第五供應電壓。
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- 2016-12-06 JP JP2016236457A patent/JP6316393B2/ja active Active
- 2016-12-08 TW TW105140642A patent/TWI587310B/zh active
- 2016-12-19 TW TW105142017A patent/TWI593221B/zh active
- 2016-12-29 TW TW105143779A patent/TWI637489B/zh active
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2017
- 2017-01-11 CN CN201710019400.0A patent/CN107623438B/zh active Active
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CN107634059A (zh) | 2018-01-26 |
CN107622782A (zh) | 2018-01-23 |
TWI593221B (zh) | 2017-07-21 |
TWI649858B (zh) | 2019-02-01 |
JP6316393B2 (ja) | 2018-04-25 |
TW201803259A (zh) | 2018-01-16 |
CN109119377A (zh) | 2019-01-01 |
TWI637489B (zh) | 2018-10-01 |
US20180019250A1 (en) | 2018-01-18 |
US20180019252A1 (en) | 2018-01-18 |
TWI587310B (zh) | 2017-06-11 |
JP2018010708A (ja) | 2018-01-18 |
CN107622782B (zh) | 2020-07-14 |
JP6389294B2 (ja) | 2018-09-12 |
TW201909392A (zh) | 2019-03-01 |
CN107634059B (zh) | 2019-12-20 |
US9633734B1 (en) | 2017-04-25 |
CN107623438B (zh) | 2019-10-25 |
US10103157B2 (en) | 2018-10-16 |
TW201803090A (zh) | 2018-01-16 |
CN107623438A (zh) | 2018-01-23 |
JP2018011498A (ja) | 2018-01-18 |
TW201906140A (zh) | 2019-02-01 |
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