US20180019250A1 - Uv-erasable memory device with uv transmitting window and fabrication method thereof - Google Patents
Uv-erasable memory device with uv transmitting window and fabrication method thereof Download PDFInfo
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- US20180019250A1 US20180019250A1 US15/630,927 US201715630927A US2018019250A1 US 20180019250 A1 US20180019250 A1 US 20180019250A1 US 201715630927 A US201715630927 A US 201715630927A US 2018019250 A1 US2018019250 A1 US 2018019250A1
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- 238000000034 method Methods 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims 4
- 230000008569 process Effects 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L27/11524—
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/326—Application of electric currents or fields, e.g. for electroforming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
Definitions
- the present invention relates to a nonvolatile memory cell and, more particularly, to a single-poly one-time programmable (OTP) memory cell that is capable of improving UV erase performance.
- OTP one-time programmable
- logic non-volatile memory Demands of diversified markets and applications drive embedded logic non-volatile memory (logic NVM) for distinct functions.
- logic NVM is single-poly NVM or single-poly OTP memory technology, which is fully compatible with CMOS processes and is widely used in various chip designs for data storage.
- a single-poly OTP memory cell typically includes two serially connected transistors.
- the first transistor acts as select transistor.
- a gate of the second transistor serves as a floating gate.
- the single-poly OTP memory cell is typically capped by dielectric materials, which are transparent to ultraviolet (UV) light.
- the state in which hot carriers (electrons) are injected into the single-poly floating gate is called a “programmed” state and data is stored in this state, and in contrast, the state in which electrons are not injected into the single-poly floating gate is called an “erased” state and data is cleared in this state.
- the above-described single-poly OTP memory cell may be erased by UV light.
- a method for fabricating a UV-erasable memory device with a UV transmitting window is disclosed.
- a substrate is provided.
- Two serially connected PMOS transistors are formed on the substrate.
- the two PMOS transistors are then covered with an interlayer dielectric (ILD) layer.
- a first intermetal dielectric (IMD) layer is then deposited on the ILD layer.
- An intermediate layer is deposited on the first IMD layer.
- a UV transmitting window is formed in the intermediate layer.
- a second intermetal dielectric (IMD) layer is then deposited on the first IMD layer and into the UV transmitting window.
- the two serially connected PMOS transistors comprise a select transistor and a floating gate transistor.
- the floating gate transistor comprises a polysilicon gate for charge storage.
- the UV transmitting window is positioned directly above the polysilicon gate for charge storage.
- a UV-erasable memory device with a UV transmitting window includes a substrate, two serially connected PMOS transistors on the substrate, an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.
- ILD interlayer dielectric
- FIG. 1 to FIG. 3 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a UV-erasable memory device in accordance with one embodiment of the invention.
- the present invention pertains to a UV-erasable memory device such as an UV-erasable electrically programmable read only memory (EPROM) device or a single-poly one-time programmable (OTP) memory device with improved UV erase performance.
- a UV-erasable memory device such as an UV-erasable electrically programmable read only memory (EPROM) device or a single-poly one-time programmable (OTP) memory device with improved UV erase performance.
- EPROM electrically programmable read only memory
- OTP single-poly one-time programmable
- FIG. 1 to FIG. 3 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a UV-erasable memory device 1 in accordance with one embodiment of the invention.
- a substrate 10 is provided.
- the substrate 10 may be a semiconductor substrate such as a silicon substrate, but is not limited thereto.
- the substrate 10 may be a P type silicon substrate and an N well 101 may be provided in the substrate 10 within a memory array region.
- the first MOS transistor 11 acts as a select transistor and may be a PMOS transistor.
- a polysilicon gate 111 of the first MOS transistor 11 may be coupled to a select gate voltage V SG .
- a select gate dielectric layer 112 may be provided between the polysilicon gate 111 and the substrate 10 .
- a first node such as a doping region 103 of the first MOS transistor 11 may be coupled to a source line voltage V SL .
- the doping region 103 may be a P + doping region.
- a second node such as a doping region 105 of the first MOS transistor 11 is coupled to a first node of the second MOS transistor. That is, the first MOS transistor 11 is serially connected to the second MOS transistor 12 through the commonly shared doping region 105 .
- the doping region 105 may be a P + doping region.
- a spacer 113 may be provided on each sidewall of the polysilicon gate 111 .
- Lightly doped drain (LDD) regions 103 a and 105 a may be formed in the N well 101 and are disposed directly under the spacers 113 , respectively.
- the LDD regions 103 a and 105 a may be P-type LDD regions.
- a second node such as a doping region 107 of the second MOS transistor 12 is coupled to a bit line voltage V BL .
- the doping region 107 may be a P + doping region.
- the second MOS transistor 12 is a floating gate transistor and may be a PMOS transistor.
- a polysilicon gate 121 of the second MOS transistor 12 serves as a floating gate for charge storage.
- a floating gate dielectric layer 122 may be provided between the polysilicon gate 121 and the substrate 10 .
- a spacer 123 may be provided on each sidewall of the polysilicon gate 121 .
- Lightly doped drain (LDD) regions 105 b and 107 a may be formed in the N well 101 and are disposed directly under the spacers 123 , respectively.
- the LDD regions 105 b and 107 a may be P-type LDD regions.
- a self-aligned silicidation process may be performed to form a silicide layer 131 on the polysilicon gate 111 , a silicide layer 133 on the doping region 103 , a silicide layer 135 on the doping region, and a silicide layer 137 on the doping region 107 .
- no silicide layer is formed on the polysilicon gate 121 because the polysilicon gate 121 is covered with a salicide block (SAB) layer 130 during the self-aligned silicidation process.
- SAB salicide block
- a contact etch stop layer (CESL) 210 is conformally deposited on the substrate 10 to cover the silicide layers 131 , 133 , 135 , and 137 , the first MOS transistor 11 , and the second MOS transistor 12 .
- the CESL 210 also covers the SAB layer 130 and is not in direct contact with the polysilicon gate 121 .
- an interlayer dielectric (ILD) layer 220 is deposited on the CESL 210 .
- the ILD layer 220 may comprise BSG, BPSG, or low dielectric constant (low-k) dielectric materials. Although only one ILD layer 220 is illustrated, it is understood that the ILD layer 220 may comprise more than one layer of dielectric materials. Contact elements (not shown) may be formed in the ILD layer 220 .
- an etch stop layer 230 such as a silicon nitride layer may be deposited on the ILD layer 220 .
- a first inter-metal dielectric (IMD) layer 240 may be deposited on the etch stop layer 230 .
- the IMD layer 240 may comprise silicon oxide or low-k materials.
- An intermediate layer 250 is deposited on the first IMD layer 240 .
- the intermediate layer 250 may be a silicon oxy-nitride layer having a thickness ranging between 1500 angstroms and 2500 angstroms, for example, 2000 angstroms.
- the relatively thick intermediate layer 250 comprised of silicon oxy-nitride is necessary to the copper dual damascene process such as a via-first copper dual damascene process. However, the relatively thick intermediate layer 250 that is comprised of silicon oxy-nitride blocks UV light during the UV erase operation, which reduces the efficiency of the UV erasure.
- a photoresist pattern 260 is then formed on the intermediate layer 250 by using a lithographic process.
- the photoresist pattern 260 may be defined by using a photo mask that is typically used in a copper dual damascene process, for example, the photo mask used to define the via-first hole pattern in a copper dual damascene process. Therefore, no extra mask is required.
- the photoresist pattern 260 comprises an opening 260 a that is aligned with and positioned directly above the polysilicon gate 121 .
- a dry etching process is performed to etch the intermediate layer 250 through the opening 260 a , thereby forming a recessed trench 250 a that penetrates through the intermediate layer 250 and may partially extend into the first IMD layer 240 .
- the photoresist pattern 260 is removed.
- a UV transmitting window 300 is formed.
- a second intermetal dielectric (IMD) layer 270 is deposited on the intermediate layer 250 .
- the recessed trench 250 a is completely filled with the second IMD layer 270 .
- a copper dual damascene structure may be formed in the first IMD layer 240 , the intermediate layer 250 , and the second IMD layer 270 outside the memory array.
- the copper dual damascene structure may be formed within a peripheral circuit region (not shown).
- the UV-erasable memory device 1 is exposed to a short-wavelength radiation 400 such UV light.
- a short-wavelength radiation 400 such UV light.
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Abstract
A UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate; an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.
Description
- This application claims the benefit of U.S. provisional application No. 62/362,068 filed Jul. 14, 2016.
- The present invention relates to a nonvolatile memory cell and, more particularly, to a single-poly one-time programmable (OTP) memory cell that is capable of improving UV erase performance.
- Demands of diversified markets and applications drive embedded logic non-volatile memory (logic NVM) for distinct functions. One of the well-known logic NVM is single-poly NVM or single-poly OTP memory technology, which is fully compatible with CMOS processes and is widely used in various chip designs for data storage.
- Typically, a single-poly OTP memory cell includes two serially connected transistors. The first transistor acts as select transistor. A gate of the second transistor serves as a floating gate. The single-poly OTP memory cell is typically capped by dielectric materials, which are transparent to ultraviolet (UV) light.
- The state in which hot carriers (electrons) are injected into the single-poly floating gate is called a “programmed” state and data is stored in this state, and in contrast, the state in which electrons are not injected into the single-poly floating gate is called an “erased” state and data is cleared in this state. The above-described single-poly OTP memory cell may be erased by UV light.
- It is one object of the invention to provide a UV-erasable memory device with improved UV erase efficiency.
- It is another object of the invention to provide a method for fabricating a UV-erasable memory device with a UV transmitting window.
- According to one embodiment of the invention, a method for fabricating a UV-erasable memory device with a UV transmitting window is disclosed. A substrate is provided. Two serially connected PMOS transistors are formed on the substrate. The two PMOS transistors are then covered with an interlayer dielectric (ILD) layer. A first intermetal dielectric (IMD) layer is then deposited on the ILD layer. An intermediate layer is deposited on the first IMD layer. A UV transmitting window is formed in the intermediate layer. A second intermetal dielectric (IMD) layer is then deposited on the first IMD layer and into the UV transmitting window.
- According to one embodiment of the invention, the two serially connected PMOS transistors comprise a select transistor and a floating gate transistor. The floating gate transistor comprises a polysilicon gate for charge storage. The UV transmitting window is positioned directly above the polysilicon gate for charge storage.
- According to another aspect of the invention, a UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate, an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
- The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
-
FIG. 1 toFIG. 3 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a UV-erasable memory device in accordance with one embodiment of the invention. - It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings are exaggerated or reduced in size, for the sake of clarity and convenience. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
- In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one skilled in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations or process steps are not disclosed in detail, as these should be well-known to those skilled in the art.
- Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and some dimensions are exaggerated in the figures for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with like reference numerals for ease of illustration and description thereof.
- The present invention pertains to a UV-erasable memory device such as an UV-erasable electrically programmable read only memory (EPROM) device or a single-poly one-time programmable (OTP) memory device with improved UV erase performance.
- Please refer to
FIG. 1 toFIG. 3 .FIG. 1 toFIG. 3 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a UV-erasable memory device 1 in accordance with one embodiment of the invention. As shown inFIG. 1 , asubstrate 10 is provided. Thesubstrate 10 may be a semiconductor substrate such as a silicon substrate, but is not limited thereto. For example, thesubstrate 10 may be a P type silicon substrate and an N well 101 may be provided in thesubstrate 10 within a memory array region. - According to one embodiment of the invention, two serially connected
MOS transistors substrate 10. Thefirst MOS transistor 11 acts as a select transistor and may be a PMOS transistor. Apolysilicon gate 111 of thefirst MOS transistor 11 may be coupled to a select gate voltage VSG. A select gatedielectric layer 112 may be provided between thepolysilicon gate 111 and thesubstrate 10. A first node such as adoping region 103 of thefirst MOS transistor 11 may be coupled to a source line voltage VSL. Thedoping region 103 may be a P+ doping region. - A second node such as a
doping region 105 of thefirst MOS transistor 11 is coupled to a first node of the second MOS transistor. That is, thefirst MOS transistor 11 is serially connected to thesecond MOS transistor 12 through the commonly shareddoping region 105. Thedoping region 105 may be a P+ doping region. - On each sidewall of the
polysilicon gate 111, aspacer 113 may be provided. Lightly doped drain (LDD)regions N well 101 and are disposed directly under thespacers 113, respectively. TheLDD regions - A second node such as a
doping region 107 of thesecond MOS transistor 12 is coupled to a bit line voltage VBL. Thedoping region 107 may be a P+ doping region. Thesecond MOS transistor 12 is a floating gate transistor and may be a PMOS transistor. Apolysilicon gate 121 of thesecond MOS transistor 12 serves as a floating gate for charge storage. A floatinggate dielectric layer 122 may be provided between thepolysilicon gate 121 and thesubstrate 10. - Likewise, on each sidewall of the
polysilicon gate 121, aspacer 123 may be provided. Lightly doped drain (LDD)regions spacers 123, respectively. TheLDD regions - Optionally, a self-aligned silicidation process may be performed to form a
silicide layer 131 on thepolysilicon gate 111, asilicide layer 133 on thedoping region 103, asilicide layer 135 on the doping region, and asilicide layer 137 on thedoping region 107. According to one embodiment of the invention, no silicide layer is formed on thepolysilicon gate 121 because thepolysilicon gate 121 is covered with a salicide block (SAB)layer 130 during the self-aligned silicidation process. - After the formation of the silicide layers 131, 133, 135, and 137, a contact etch stop layer (CESL) 210 is conformally deposited on the
substrate 10 to cover the silicide layers 131, 133, 135, and 137, thefirst MOS transistor 11, and thesecond MOS transistor 12. According to one embodiment of the invention, theCESL 210 also covers theSAB layer 130 and is not in direct contact with thepolysilicon gate 121. - After the deposition of the
CESL 210, an interlayer dielectric (ILD)layer 220 is deposited on theCESL 210. For example, theILD layer 220 may comprise BSG, BPSG, or low dielectric constant (low-k) dielectric materials. Although only oneILD layer 220 is illustrated, it is understood that theILD layer 220 may comprise more than one layer of dielectric materials. Contact elements (not shown) may be formed in theILD layer 220. - Subsequently, an
etch stop layer 230 such as a silicon nitride layer may be deposited on theILD layer 220. A first inter-metal dielectric (IMD)layer 240 may be deposited on theetch stop layer 230. TheIMD layer 240 may comprise silicon oxide or low-k materials. Anintermediate layer 250 is deposited on thefirst IMD layer 240. According to one embodiment of the invention, theintermediate layer 250 may be a silicon oxy-nitride layer having a thickness ranging between 1500 angstroms and 2500 angstroms, for example, 2000 angstroms. - The relatively thick
intermediate layer 250 comprised of silicon oxy-nitride is necessary to the copper dual damascene process such as a via-first copper dual damascene process. However, the relatively thickintermediate layer 250 that is comprised of silicon oxy-nitride blocks UV light during the UV erase operation, which reduces the efficiency of the UV erasure. - As shown in
FIG. 2 , according to one embodiment of the invention, aphotoresist pattern 260 is then formed on theintermediate layer 250 by using a lithographic process. Thephotoresist pattern 260 may be defined by using a photo mask that is typically used in a copper dual damascene process, for example, the photo mask used to define the via-first hole pattern in a copper dual damascene process. Therefore, no extra mask is required. - The
photoresist pattern 260 comprises anopening 260 a that is aligned with and positioned directly above thepolysilicon gate 121. A dry etching process is performed to etch theintermediate layer 250 through the opening 260 a, thereby forming a recessedtrench 250 a that penetrates through theintermediate layer 250 and may partially extend into thefirst IMD layer 240. Subsequently, thephotoresist pattern 260 is removed. - By removing the portion of the
intermediate layer 250 that is directly above thepolysilicon gate 121, aUV transmitting window 300 is formed. - As shown in
FIG. 3 , after removing thephotoresist pattern 260, a second intermetal dielectric (IMD)layer 270 is deposited on theintermediate layer 250. The recessedtrench 250 a is completely filled with thesecond IMD layer 270. Although not shown in this figure, it is understood that a copper dual damascene structure may be formed in thefirst IMD layer 240, theintermediate layer 250, and thesecond IMD layer 270 outside the memory array. For example, the copper dual damascene structure may be formed within a peripheral circuit region (not shown). - During UV erase operation, the UV-
erasable memory device 1 is exposed to a short-wavelength radiation 400 such UV light. By providing theUV transmitting window 300 between the IMD layers, the efficiency of the UV erasure is significantly improved. - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (20)
1. A method for fabricating a UV-erasable memory device with a UV transmitting window, comprising:
providing a substrate;
forming two serially connected MOS transistors on said substrate;
covering said two MOS transistors with an interlayer dielectric (ILD) layer;
depositing a first intermetal dielectric (IMD) layer on said ILD layer;
depositing an intermediate layer on said first IMD layer;
forming a UV transmitting window in said intermediate layer; and
depositing a second intermetal dielectric (IMD) layer on said first IMD layer and into said UV transmitting window.
2. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 1 , wherein said two serially connected MOS transistors comprise a select transistor and a floating gate transistor.
3. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 2 , wherein said floating gate transistor comprises a polysilicon gate for charge storage.
4. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 3 , wherein said UV transmitting window is positioned directly above said polysilicon gate for charge storage.
5. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 1 , wherein said substrate is a P type silicon substrate with an N well.
6. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 2 further comprising:
forming a salicide block (SAB) layer covering said polysilicon gate for charge storage.
7. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 6 further comprising:
depositing a contact etch stop layer on said two serially connected MOS transistors and on said SAB layer.
8. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 7 , wherein said ILD layer is deposited on the contact etch stop layer.
9. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 1 , wherein said intermediate layer is a silicon oxy-nitride layer.
10. The method for fabricating a UV-erasable memory device with a UV transmitting window according to claim 1 , wherein said intermediate layer has a thickness ranging between 1500 angstroms and 2500 angstroms.
11. A UV-erasable memory device with a UV transmitting window, comprising:
a substrate;
two serially connected PMOS transistors on said substrate;
an interlayer dielectric (ILD) layer covering said two PMOS transistors;
a first intermetal dielectric (IMD) layer on said ILD layer;
an intermediate layer on said first IMD layer;
a UV transmitting window in said intermediate layer; and
a second intermetal dielectric (IMD) layer on said first IMD layer and in said UV transmitting window.
12. The UV-erasable memory device with a UV transmitting window according to claim 11 , wherein said two serially connected PMOS transistors comprise a select transistor and a floating gate transistor.
13. The UV-erasable memory device with a UV transmitting window according to claim 12 , wherein said floating gate transistor comprises a polysilicon gate for charge storage.
14. The UV-erasable memory device with a UV transmitting window according to claim 13 , wherein said UV transmitting window is positioned directly above said polysilicon gate for charge storage.
15. The UV-erasable memory device with a UV transmitting window according to claim 11 , wherein said substrate is a P type silicon substrate with an N well.
16. The UV-erasable memory device with a UV transmitting window according to claim 12 further comprising:
a salicide block (SAB) layer covering said polysilicon gate for charge storage.
17. The UV-erasable memory device with a UV transmitting window according to claim 16 further comprising:
a contact etch stop layer on said two serially connected PMOS transistors and on said SAB layer.
18. The UV-erasable memory device with a UV transmitting window according to claim 17 , wherein said ILD layer is deposited on the contact etch stop layer.
19. The UV-erasable memory device with a UV transmitting window according to claim 11 , wherein said intermediate layer is a silicon oxy-nitride layer.
20. The UV-erasable memory device with a UV transmitting window according to claim 11 , wherein said intermediate layer has a thickness ranging between 1500 angstroms and 2500 angstroms.
Priority Applications (3)
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---|---|---|---|
US15/630,927 US20180019250A1 (en) | 2016-07-14 | 2017-06-22 | Uv-erasable memory device with uv transmitting window and fabrication method thereof |
TW106127876A TW201906140A (en) | 2016-07-14 | 2017-08-17 | UV erasable memory element with UV transmission window and manufacturing method thereof |
CN201710737673.9A CN109119377A (en) | 2016-07-14 | 2017-08-24 | UV erasable memory component and its manufacturing method with UV transmissive window |
Applications Claiming Priority (2)
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---|---|---|---|
US201662362068P | 2016-07-14 | 2016-07-14 | |
US15/630,927 US20180019250A1 (en) | 2016-07-14 | 2017-06-22 | Uv-erasable memory device with uv transmitting window and fabrication method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20180019250A1 true US20180019250A1 (en) | 2018-01-18 |
Family
ID=57909468
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/348,369 Active US9633734B1 (en) | 2016-07-14 | 2016-11-10 | Driving circuit for non-volatile memory |
US15/630,927 Abandoned US20180019250A1 (en) | 2016-07-14 | 2017-06-22 | Uv-erasable memory device with uv transmitting window and fabrication method thereof |
US15/648,464 Active US10103157B2 (en) | 2016-07-14 | 2017-07-13 | Nonvolatile memory having a shallow junction diffusion region |
Family Applications Before (1)
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US15/348,369 Active US9633734B1 (en) | 2016-07-14 | 2016-11-10 | Driving circuit for non-volatile memory |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US15/648,464 Active US10103157B2 (en) | 2016-07-14 | 2017-07-13 | Nonvolatile memory having a shallow junction diffusion region |
Country Status (4)
Country | Link |
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US (3) | US9633734B1 (en) |
JP (2) | JP6316393B2 (en) |
CN (4) | CN107623438B (en) |
TW (5) | TWI587310B (en) |
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CN107634059A (en) | 2018-01-26 |
CN107622782A (en) | 2018-01-23 |
TWI593221B (en) | 2017-07-21 |
TWI649858B (en) | 2019-02-01 |
JP6316393B2 (en) | 2018-04-25 |
TW201803259A (en) | 2018-01-16 |
CN109119377A (en) | 2019-01-01 |
TWI637489B (en) | 2018-10-01 |
US20180019252A1 (en) | 2018-01-18 |
TWI587310B (en) | 2017-06-11 |
JP2018010708A (en) | 2018-01-18 |
CN107622782B (en) | 2020-07-14 |
JP6389294B2 (en) | 2018-09-12 |
TW201909392A (en) | 2019-03-01 |
CN107634059B (en) | 2019-12-20 |
US9633734B1 (en) | 2017-04-25 |
CN107623438B (en) | 2019-10-25 |
US10103157B2 (en) | 2018-10-16 |
TW201803090A (en) | 2018-01-16 |
CN107623438A (en) | 2018-01-23 |
TW201810260A (en) | 2018-03-16 |
JP2018011498A (en) | 2018-01-18 |
TW201906140A (en) | 2019-02-01 |
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