JP2012059777A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of improving the operating speed of a semiconductor device by reducing the resistance in an extension region on the source side of an FET formed on a semiconductor substrate.SOLUTION: A first sidewall 6w and a second sidewall 6n having different widths in the gate length direction of a gate electrode 4d are formed, respectively, on the sidewall of the gate electrode 4d. Consequently, extension regions 37 and 38 are formed in self-alignment mannar under the first sidewall 6w and the second sidewall 6n with different widths on the upper surface of a semiconductor substrate SB.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high breakdown voltage MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a technique effective when applied to the manufacturing method thereof.

  In an integrated circuit on a semiconductor substrate, for example, as a semiconductor element, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that operates at a low voltage and requires a large current driving force, or operates at a voltage higher than the MISFET and operates at a high voltage. In some cases, MISFETs that require a withstand voltage (hereinafter simply referred to as high withstand voltage MISFETs) are mixed.

  One of the high voltage MISFETs is a rewritable nonvolatile memory (hereinafter simply referred to as a MONOS memory) having a MONOS structure. The MONOS memory has an insulating film made of an ONO (Oxide Nitride Oxide) film in which a silicon nitride film layer as a charge storage layer is formed between two silicon oxide films, for example, between a gate electrode and a semiconductor substrate. The FET is widely used as a memory cell of a nonvolatile memory such as a flash memory.

  In recent years, with the miniaturization of the MISFET, an extension region to which an impurity having a lower concentration than the source / drain region of the MISFET is added is formed on the main surface of the semiconductor substrate as a gate electrode for the purpose of improving reliability such as breakdown voltage. The diffusion layer has an LDD (Lightly Doped Drain) structure, which is mainly formed from the lower part of the end portion to the source / drain region. The width of the extension region of the MISFET having the LDD structure is usually determined by the width (spacer length) of the side wall formed on the side wall of the gate electrode of the MISFET.

  In the sidewalls of the high breakdown voltage MISFET and the MONOS memory, it is desirable that the spacer length be different from the spacer length of the MISFET of the peripheral circuit operating at a low voltage. In a conventional general semiconductor device manufacturing method, a photoresist film is formed using a special mask for forming two types of LDDs in order to form two or more types of sidewalls having different spacer lengths on the same semiconductor substrate. They are selectively formed to create side walls. Here, the two-type LDD or the two-type LDD structure refers to a structure of a semiconductor device including a MISFET having sidewalls having different widths and extension regions having different widths formed on the same semiconductor substrate. As a technique for realizing the two-type LDD structure, for example, Japanese Patent Application Laid-Open No. 2004-349680 discloses a method thereof.

JP 2004-349680 A JP-A-5-62994 JP-A-9-213713 JP 2001-274259 A

  By the process of forming the two-type LDD, the sidewalls on both sides of the high breakdown voltage MISFET or MONOS memory are formed on the sidewalls of the gate electrode of the MISFET that operates at a lower voltage than the high breakdown voltage MISFET (hereinafter simply referred to as the low breakdown voltage MISFET). A sidewall having a spacer length longer than that of the sidewall is formed.

  In a high breakdown voltage MISFET or MONOS memory, it is conceivable that an extension region having a long width is formed below the side wall by forming a wide side wall on both side walls of the gate electrode. This is because when a high voltage is applied to both the source region and the drain region of the high breakdown voltage MISFET or MONOS memory and a high potential difference is generated between the source / drain region and the gate or well (semiconductor substrate), This is effective in improving the breakdown voltage of the drain region.

  However, in some high-breakdown-voltage MISFETs or MONOS memories, there are elements that require a high breakdown voltage, for example, in the drain region and well, and a breakdown voltage in the source region that is lower than that in the drain region. That is, in this FET, a high potential difference is generated between the drain region and the gate or between the drain region and the well, but a high potential difference is not generated between the source region and the gate or between the source region and the well as in the drain region.

  In such an FET, forming an extension region having a long width even in a source region that does not require a high breakdown voltage causes a reduction in current flowing between the source and the drain. That is, the extension region is a region having a higher resistance than the source region, and if the width of the extension region is increased, the resistance value between the source and the drain is increased correspondingly, which hinders the speeding up of the operation of the semiconductor device. .

  In addition, a contact plug that is a connection member that supplies a specific potential to the source region must be arranged away from the gate electrode by the width of the extension region. Therefore, in the FET where the drain region requires a high breakdown voltage and the source region does not require a high breakdown voltage, when the extension region having a long width is formed in the source region, the extension region of the source region is long. Therefore, it is necessary to ensure a long distance between the gate electrode and the contact plug, and it becomes difficult to miniaturize the semiconductor device.

Patent Document 2 (Japanese Patent Laid-Open No. 5-62994) describes forming a transistor from which a source-side extension region (n ⁻ layer) is removed. Specifically, after forming a gate electrode, an extension region, and sidewalls on both sides of the gate insulating film on the main surface of the semiconductor substrate, a part of the sidewall on the source side is removed by using a photolithography technique and an etching method. Then, by forming an n ⁺ layer (source / drain region) having an impurity concentration higher than that of the extension region on the semiconductor substrate, the extension region on the source side is changed to the n ⁺ layer.

  In Patent Document 2, in addition to the transistor from which the extension region on the source side is removed, the transistor is used for a different purpose, for example, operates at a lower voltage than the transistor and has a relatively short sidewall and extension region. There is no description as to whether or not a transistor or the like having n is formed.

Patent Document 3 (Japanese Patent Laid-Open No. 9-213713) describes forming a field effect transistor in which the width of the extension region on the source side is shorter than the width of the extension region on the drain side. Specifically, after forming the gate electrode and the extension region on the main surface of the semiconductor substrate, a first through film (insulating film) is deposited on the main surface of the semiconductor substrate, and then the first through the source forming region side. The through film is removed. Thereafter, a second through film (insulating film) is formed on the main surface of the semiconductor substrate, and n ⁺ layers (source / drain regions) are formed on the main surface of the semiconductor substrate via the first and second through films. . Here, the first and second through films are formed on the side wall of the drain side gate electrode, and only the second through film is formed on the side wall of the source side gate electrode. The width of the extension region on the source side is shorter than the width of the extension region.

  In Patent Document 3, in addition to a field effect transistor in which the extension region on the source side is shortened, the transistor is used for a different purpose, for example, operates at a lower voltage than the field effect transistor and has a shorter width and extension. There is no description as to whether or not a transistor having a region is formed.

Patent Document 4 (Japanese Patent Laid-Open No. 2001-274259) describes forming a transistor in which the width of the extension region on the source side is shorter than the width of the extension region on the drain side. Specifically, an insulating film is formed on the main surface of the semiconductor substrate on which the gate electrode and the extension region are formed, a resist mask is formed on the insulating film on the drain forming region side, and then the main surface of the semiconductor substrate is By etching back the insulating film, a sidewall having a long width is formed on the sidewall of the gate electrode on the drain formation region side. Subsequently, an n ⁺ diffusion layer is formed on the main surface of the semiconductor substrate using this sidewall as a mask, thereby forming a transistor having an extension region on the source side that is shorter than the drain side.

  In Patent Document 4, in addition to a field effect transistor having a source-side extension region shortened, the transistor is used for a different purpose. For example, the transistor operates at a lower voltage than the field effect transistor, and has a short sidewall and extension region. There is no description on whether or not a transistor or the like is formed.

  An object of the present invention is to improve the operation speed of a semiconductor device.

  Another object of the present invention is to miniaturize a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to a preferred embodiment of the present invention includes:
A first field effect transistor formed in a first region of the main surface of the semiconductor substrate and a second electric field formed in a second region of the main surface of the semiconductor substrate and operating at a higher voltage than the first field effect transistor. A semiconductor device having an effect transistor,
The first field effect transistor is:
A first gate electrode formed on the semiconductor substrate via a first gate insulating film;
First sidewalls respectively formed on sidewalls on both sides of the first gate electrode;
A first extension region formed on an upper surface of the semiconductor substrate below the first sidewall;
A first diffusion layer electrically connected to the first extension region, formed on an upper surface of the semiconductor substrate, and having a higher impurity concentration than the first extension region;
Have
The second field effect transistor is:
A second gate electrode formed on the semiconductor substrate via a second gate insulating film;
The second gate electrode is formed on one of the sidewalls on both sides of the second gate electrode in the same layer as the first sidewall and has the same width as the width of the first sidewall in the gate length direction of the first gate electrode. Side walls,
A third sidewall formed on the other side wall on both sides of the second gate electrode and having a width in the gate length direction larger than the second sidewall;
A second extension region formed on the upper surface of the semiconductor substrate below the second sidewall;
A third extension region formed on an upper surface of the semiconductor substrate below the third sidewall and having a width in the gate length direction larger than the second extension region;
A second diffusion layer formed on the upper surface of the semiconductor substrate, electrically connected to the second extension region, and having a higher impurity concentration than the second extension region;
A third diffusion layer formed on the upper surface of the semiconductor substrate, electrically connected to the third extension region, and having an impurity concentration higher than that of the third extension region;
It is what has.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the preferred embodiment of the present invention described above, the operation speed of the semiconductor device can be improved.

  In addition, the semiconductor device can be miniaturized.

It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing which shows the manufacturing method of a semiconductor device. (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.2 (a). FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. (A) is sectional drawing which shows the manufacturing method of the semiconductor device following FIG. (B) is sectional drawing which shows the manufacturing method of the semiconductor device following Fig.4 (a). FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 10 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12; FIG. 14 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 13; It is sectional drawing which shows the semiconductor device which is Embodiment 2 of this invention. It is a figure explaining erasure | elimination operation | movement of the MONOS memory of Embodiment 1 and 2 of this invention. (A) is a circuit diagram of a MONOS memory. (B) is a cross-sectional view of a MONOS memory. It is a figure explaining the write-in operation | movement of the MONOS memory of Embodiment 1 and 2 of this invention. (A) is a circuit diagram of a MONOS memory. (B) is a cross-sectional view of a MONOS memory. It is a figure explaining the write-in operation | movement of the MONOS memory of Embodiment 1 and 2 of this invention. (A) is a circuit diagram of a MONOS memory. (B) is a cross-sectional view of a MONOS memory. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. FIG. 20 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 19; FIG. 21 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 20; FIG. 22 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 21;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
An example of the structure of the MISFET according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a plurality of FETs formed on the same substrate. In order from the left of the figure, a MONOS type memory cell (MONOS memory) Mn, a low breakdown voltage MISFET Ln, a first high breakdown voltage MISFET H1, a second A high voltage MISFET H2 is shown.

  For example, p wells 2a, 2b, 2c and 2d into which p type impurities (for example, B (boron)) are introduced are formed on the upper surface of the semiconductor substrate SB made of p type single crystal silicon. Are separated by an element isolation layer 1. The element isolation layer 1 is formed of an insulating film embedded in a groove (element isolation groove) 1a formed on the main surface of the semiconductor substrate SB.

  The MONOS memory Mn shown in FIG. 1 is a non-volatile memory, and a bottom oxide film 3g, a charge storage layer 3h, a top oxide formed in this order on the main surface of the semiconductor substrate SB on which the p-well 2a is formed, from the semiconductor substrate SB side. A charge storage layer 3h having a film 3i, a gate electrode 4a, a diffusion layer 42 forming a source region and a diffusion layer 41 forming a drain region formed on the main surface of the semiconductor substrate SB on both sides of the gate electrode 4a; Charge (information) is stored in the. The bottom oxide film 3g and the top oxide film 3i function as a potential barrier film. During the writing operation of the MONOS memory Mn, a high potential difference (for example, about 5 V to 12 V) is generated between the drain and gate or the drain and well (semiconductor substrate) in the memory MONOS memory Mn. Mn needs to be a relatively high breakdown voltage FET.

  The low breakdown voltage MISFET Ln is a field effect transistor that operates at a relatively low voltage, and a gate formed on the main surface of the semiconductor substrate SB on which the p-well 2b is formed via the gate insulating film 3b in order from the semiconductor substrate SB side. The electrode 4b includes a diffusion layer 43 constituting a source region and a diffusion layer 44 constituting a drain region formed on the main surface of the semiconductor substrate SB on both sides of the gate electrode 4b. The low withstand voltage MISFET Ln is an FET constituting a peripheral circuit that performs, for example, a selection operation of the MONOS memory Mn. Here, it is assumed that the low breakdown voltage MISFET Ln is an FET that operates at a voltage lower than that of the MONOS memory Mn.

  The first high breakdown voltage MISFET H1 includes a gate electrode 4c formed on the main surface of the semiconductor substrate SB on which the p-well 2c is formed via the gate insulating film 3c in this order from the semiconductor substrate SB side, and semiconductors on both sides of the gate electrode 4c. A diffusion layer 45 constituting a source region and a diffusion layer 46 constituting a drain region are formed on the main surface of the substrate SB. The first high withstand voltage MISFET H1 is an FET that operates at a voltage higher than that of the low withstand voltage MISFET Ln, and is used for a protection element of a circuit through which an input current or an output current of a semiconductor device flows or a booster circuit of a power supply.

  Similarly to the first high breakdown voltage MISFET H1, the second high breakdown voltage MISFET H2 is formed on the main surface of the semiconductor substrate SB on which the p-well 2d is formed via the gate insulating film 3d sequentially from the semiconductor substrate SB side. And a diffusion layer 47 constituting a source region and a diffusion layer 48 constituting a drain region formed on the main surface of the semiconductor substrate SB on both sides of the gate electrode 4d. The second high withstand voltage MISFET H2 is an FET that operates at a voltage higher than that of the low withstand voltage MISFET Ln, and is used for a protection element of a circuit through which an input current or an output current of a semiconductor device flows, a booster circuit of a power supply, or the like.

  The first high breakdown voltage MISFET H1 is a MISFET used for, for example, a detection circuit or a level shifter, and the second high breakdown voltage MISFET H2 is a MISFET used for, for example, a booster circuit or a direct peripheral circuit.

  The detection circuit in which the first high withstand voltage MISFET H1 is considered to be used is, for example, a microcomputer (microcomputer) for an IC card for security, and a voltage outside the specified range for the purpose of illegal use of the IC card. Alternatively, it refers to a circuit for detecting when a temperature is applied or a current having a frequency outside the specified range flows, and stopping the operation of the circuit in the microcomputer. The level shifter is a circuit that is located between two systems and changes the magnitude of the signal voltage when two digital systems having different magnitudes of the signal voltage are connected. Such a level shifter is used particularly when the size of the signal voltage is changed from a small voltage range to a large voltage range.

  On the other hand, a booster circuit in which the second high-breakdown-voltage MISFET H2 is considered to be used is a circuit that extracts a voltage having a different value from a certain power supply voltage, such as a DC / DC converter. A direct peripheral circuit refers to a circuit to which a high voltage is applied, such as a decoder or a sense amplifier.

  The first high breakdown voltage MISFET H1 is a MISFET in which a high voltage is applied to both the source region and the drain region during operation. Similarly, the second high breakdown voltage MISFET H2 operates in the drain region of the second high breakdown voltage MISFET H2. In doing so, a relatively high voltage is applied. However, during the operation of the second high voltage MISFET H2, the source region of the second high voltage MISFET H2 includes the source region and drain region of the first high voltage MISFET H1, or the drain region and the gate electrodes 4c and 4d of the second high voltage MISFET H2. Alternatively, a high potential difference that occurs between the p-wells 2c and 2d does not occur.

  The first high breakdown voltage MISFET H1 and the second high breakdown voltage MISFET H2 are FETs that operate at a higher voltage than the low breakdown voltage MISFET Ln. The high withstand voltage MISFET requires a gate insulating film thicker than the gate insulating film 3b of the low withstand voltage MISFET Ln because, for example, a relatively high potential difference is generated between the drain and the gate during operation in the same manner as the MONOS memory. . The gate lengths of the gate electrodes 4a, 4c and 4d are longer than the gate length of the gate electrode 4b. The gate electrodes 4a, 4c and 4d of the MONOS memory Mn, the first high breakdown voltage MISFET H1 and the second high breakdown voltage MISFET H2 have a longer gate length than the low breakdown voltage MISFET Ln. 2 because the high breakdown voltage MISFET H2 operates at a higher voltage than the low breakdown voltage MISFET Ln.

  Side walls made of an insulating film are formed on the side walls on both sides of each of the gate electrodes 4a to 4d, and n-type impurities (for example, P (phosphorus)) are formed on the main surface of the semiconductor substrate SB below each side wall. ) Is introduced at a low concentration, and an extension region which is a semiconductor region formed is formed. Further, a diffusion layer which is a semiconductor region into which an n-type impurity (for example, P (phosphorus)) is introduced at a higher concentration than the extension region is formed on the upper surface of the semiconductor substrate SB in the region outside each sidewall. Has been. That is, each of the source / drain regions of the MONOS memory Mn, the low breakdown voltage MISFET Ln, the first high breakdown voltage MISFET H1, and the second high breakdown voltage MISFET H2 has a low resistance diffusion layer having a high impurity concentration, and a lower resistance concentration and a higher resistance than the diffusion layer. An extension region and an LDD structure.

  A first side wall 6w made of a laminated film composed of the insulating film 6a, the insulating film 6 and the insulating film 7 is formed on each side wall of the gate electrodes 4a and 4c and one side wall of the gate electrode 4d. ing. That is, the insulating film 6a is formed on the upper surface of the semiconductor substrate SB, the side walls on both sides of the gate electrodes 4a and 4c, and one side wall of the gate electrode 4d, and the insulating film 6 is formed on the insulating film 6a. An insulating film 7 is formed on the insulating film 6.

  In other words, the insulating film 6a is continuously formed from the main surface of the semiconductor substrate SB on the side walls on both sides of the gate electrode 4a of the MONOS memory Mn. On the side wall of the gate electrode 4a on the semiconductor substrate SB, An insulating film 6 and an insulating film 7 formed through the insulating film 6a are sequentially formed. In addition, an insulating film 6a is continuously formed on the side walls on both sides of the gate electrode 4b of the low breakdown voltage MISFET Ln from the main surface of the semiconductor substrate SB, and an insulating film is formed on the side wall of the gate electrode 4b on the semiconductor substrate SB. An insulating film 6 is formed through the film 6a. In addition, an insulating film 6a is formed on both side walls of the gate electrode 4c of the first high breakdown voltage MISFET H1 continuously from the main surface of the semiconductor substrate SB, and on the side wall of the gate electrode 4c on the semiconductor substrate SB. The insulating film 6 and the insulating film 7 are sequentially formed through the insulating film 6a. Also, an insulating film 6a is formed on one of the side walls on both sides of the gate electrode 4d of the second high breakdown voltage MISFET H2 from the main surface of the semiconductor substrate SB, and the gate electrode 4d is formed on the semiconductor substrate SB. On one side wall, the insulating film 6 and the insulating film 7 are formed in order via the insulating film 6a. Further, an insulating film 6a is formed on the other side wall on both sides of the gate electrode 4d of the second high breakdown voltage MISFET H2 from the main surface of the semiconductor substrate SB, and the gate electrode 4d is formed on the semiconductor substrate SB. An insulating film 6 is formed on the other side wall through an insulating film 6a.

  Here, since the insulating film 6 is formed on the side wall of each gate electrode through the insulating film 6a, the insulating film 6 is not in contact with the side walls of the gate electrodes 4a, 4c and 4d. The insulating film 6a and the insulating film 7 are made of, for example, a silicon oxide film, and the insulating film 7 is made of, for example, a silicon nitride film.

  On the other hand, on the side wall on both sides of the gate electrode 4b and the side wall on the opposite side of the side wall of the gate electrode 4c where the first side wall 6w is formed, a stacked layer composed of the insulating film 6a and the insulating film 6 is formed. Second sidewalls 6n made of a film are formed respectively. That is, a continuous insulating film is formed on the upper surface of the semiconductor substrate SB, the side walls on both sides of the gate electrode 4b, and the side wall of the gate electrode 4c opposite to the side wall on which the first side wall 6w is formed. 6a is formed, and the insulating film 6 is formed on the insulating film 6a. That is, the first sidewall 6w has a stacked structure in which the number of stacked layers is larger than that of the second sidewall 6n. Since the insulating film 6 is formed on the side walls of the gate electrodes via the insulating film 6a, the insulating film 6 is not in contact with the side walls of the gate electrodes 4a, 4c and 4d.

  The sidewalls on both sides of the gate electrode 4b and the second sidewalls 6n formed on the sidewalls of the gate electrode 4c opposite to the sidewalls on which the first sidewalls 6w are formed are the same in the manufacturing process. It is the insulating film of the same layer comprised by the same insulating laminated film, and was formed of the same process.

  The first sidewall 6w and the second sidewall 6n are sidewall spacers formed in a self-aligned manner on the sidewalls of the gate electrodes by anisotropic etching, and the gates to which the first sidewall 6w and the second sidewall 6n are in contact, respectively. The width (spacer length) of the first sidewall 6w and the second sidewall 6n in the gate length direction of the electrode is larger in the first sidewall 6w than in the second sidewall 6n.

  That is, the first side wall 6w is formed on one side wall of the gate electrode 4c of the second high breakdown voltage MISFET H2, and the second side wall having a spacer length smaller than that of the first side wall 6w is formed on the other side wall of the gate electrode 4c. A side wall 6n is formed, and a side wall having a different width is formed on each side wall of the gate electrode 4c.

  In addition, an extension region 32 and a diffusion layer 42 are formed on the upper surface of the semiconductor substrate SB in one of the regions on both sides of the gate electrode 4a of the MONOS memory Mn, and the semiconductor substrate SB in the other region is formed. An extension region 31 and a diffusion layer 41 are formed on the upper surface. The extension regions 31 and 32 have a deeper junction depth from the upper surface of the semiconductor substrate SB than the diffusion layers 41 and 42, and are formed from the lower portion of the side wall of the gate electrode 4a to the side surface of the element isolation layer 1. The diffusion layers 41 and 42 are on the extension regions 31 and 32 from the lower part of the side wall of the first side wall 6w formed on the side wall of the gate electrode 4a and not in contact with the gate electrode 4a to the side surface of the element isolation layer 1. Are formed respectively. The extension region 31 and the diffusion layer 41 constitute a source region of the MONOS memory Mn, and the extension region 32 and the diffusion layer 42 constitute a drain region of the MONOS memory Mn.

The extension regions 31 and 32 are n ⁻ type semiconductor regions having an impurity concentration lower than that of the diffusion layers 41 and 42 which are n ⁺ type semiconductor regions, and have a resistance value higher than that of the diffusion layers 41 and 42. The extension regions 31 and 32 are in contact with the lower surface of the first sidewall 6w formed on the sidewall of the gate electrode 4a on the upper surface of the semiconductor substrate SB, and the extension regions on the upper surface of the semiconductor substrate SB in the gate length direction of the gate electrode 4a. The widths 31 and 32 are substantially the same as the width of the first sidewall 6w in the same direction. The width of the extension region on the upper surface of the semiconductor substrate SB here refers to the length from the end of the extension region to the other end of the upper surface of the semiconductor substrate SB in the gate length direction of the gate electrode.

  Similarly, extension regions 35 and 36 and diffusion layers 45 and 46 are formed on the upper surface of the semiconductor substrate SB in regions on both sides of the gate electrode 4c of the first high breakdown voltage MISFET H1, and the extension region 35 and the diffusion layer 45 are The source region of the first high voltage MISFET H1 is configured, and the extension region 36 and the diffusion layer 46 configure the drain region of the first high voltage MISFET H1. Furthermore, extension regions 37 and 38 and diffusion layers 47 and 48 are formed on the upper surface of the semiconductor substrate SB in the regions on both sides of the gate electrode 4d of the second high breakdown voltage MISFET H2, and the extension region 37 and the diffusion layer 47 are formed in the first region. 2 constitutes the source region of the high voltage MISFET H2, and the extension region 38 and the diffusion layer 48 constitute the drain region of the second high voltage MISFET H2.

  The widths of the extension regions 37 and 38 on the upper surface of the semiconductor substrate SB in the gate length direction of the gate electrode 4d are substantially the same as the widths of the second sidewall 6n and the first sidewall 6w formed on the respective upper portions. It has become. That is, as described above, since the width (spacer length) of the second side wall 6n is smaller than the width (spacer length) of the first side wall 6w, the semiconductor below the second side wall 6n on the side wall of the gate electrode 4d. The width of the extension region 37 on the upper surface of the substrate SB is shorter than the width of the extension region 38 on the upper surface of the semiconductor substrate SB below the first sidewall 6w on the side wall of the gate electrode 4d.

  Similarly, extension regions 33 and 34 and diffusion layers 43 and 44 are formed on the upper surface of the semiconductor substrate SB in the regions on both sides of the gate electrode 4b of the low breakdown voltage MISFET Ln. The source region of the low breakdown voltage MISFET Ln is configured, and the extension region 34 and the diffusion layer 44 configure the drain region of the low breakdown voltage MISFET Ln. However, in the low breakdown voltage MISFET Ln, the junction depths of the extension regions 33 and 34 are formed shallower than the junction depths of the diffusion layers 43 and 44.

  As shown in FIG. 1, a silicide layer 9 is formed on each of the gate electrodes 4a to 4d and the diffusion layers 41 to 48, and the silicide layer 9, the MONOS memory Mn, the low breakdown voltage MISFET Ln, and the first high breakdown voltage MISFET H1. The main surface of the semiconductor substrate SB including the second high voltage MISFET H2 is covered with a laminated film of the stopper insulating film 10 and the interlayer insulating film 11. In the stopper insulating film 10 and the interlayer insulating film 11, contact holes 12 reaching from the upper surface of the interlayer insulating film 11 to the upper surfaces of the silicide layers 9 are formed, and contact plugs 13 made of a conductive film are formed in the respective contact holes 12. Is formed. FIG. 1 does not show a region where the contact hole 12 and the contact plug 13 are formed on the gate electrodes 4a to 4d.

  An interlayer insulating film 15 is formed on the interlayer insulating film 11 via a stopper insulating film 14. The stopper insulating film 14 and the interlayer insulating film 15 reach the upper surface of the contact plug 13 from the upper surface of the interlayer insulating film 15. A wiring groove 16 is formed, and a metal wiring 17 made of a conductor film is formed in the wiring groove 16.

  The silicide layer 9 has a function of reducing the contact resistance between the diffusion layers 41 to 46 and the contact plug 13 by being interposed between the diffusion layers 41 to 46 and the contact plug 13. The silicide layer 9 is a reaction layer of metal and silicon, and as its material, for example, nickel silicide, cobalt silicide, platinum silicide or titanium silicide can be used.

  The contact plug 13 is a connection member formed through a barrier conductor film (not shown) formed on the inner wall and bottom of the contact hole 12, and includes a MONOS memory Mn, a low withstand voltage MISFET Ln, a first high withstand voltage MISFET H1, and a second. The source / drain regions of the high breakdown voltage MISFET H2 and the metal wiring 17 are electrically connected. The contact plug 13 is made of, for example, tungsten, and the barrier conductor film formed on the side wall and the bottom thereof is made of, for example, titanium nitride. Note that, in a region not shown, the gate electrodes 4a to 4d are electrically connected to a metal wiring (not shown) through a silicide layer 9 and a contact plug 13 formed on each of the gate electrodes 4a to 4d.

  The stopper insulating film 10 is made of, for example, a silicon nitride film, and functions as an etching stopper film when the contact hole 12 is formed. The interlayer insulating films 11 and 15 are made of an insulating film such as a silicon oxide film or a SiOC film. The stopper insulating film 14 is made of, for example, a silicon nitride film, and functions as an etching stopper film when the wiring trench 16 is formed.

  The metal wiring 17 is a wiring for supplying a predetermined potential to the MONOS memory Mn, the low breakdown voltage MISFET Ln, the first high breakdown voltage MISFET H1, and the second high breakdown voltage MISFET H2, and is formed by a known damascene process. The metal wiring 17 includes a barrier conductor film formed on the inner wall and the bottom of the wiring groove 16 and a metal film filled in the wiring groove 16 through the barrier conductor film. The barrier conductor film is made of a laminated film of Ta (tantalum) and TaN (tantalum nitride), for example, and the metal film is a film mainly made of Cu (copper). The barrier film is provided for the purpose of preventing the metal element in the metal film from diffusing into the interlayer insulating film 15 or the like. In addition to tantalum, titanium (Ti), ruthenium (Ru), manganese (Mn), or a compound thereof may be used as a member of the barrier conductor film.

  The metal wiring 17 is not limited to the damascene structure, and may be a wiring structure formed by patterning a conductor film mainly composed of aluminum.

  The MONOS memory Mn can perform information writing and erasing by putting electrons into and out of the charge storage layer 3h below the gate electrode 4a. There are two ways to put in and out the electrons. The writing and erasing is performed by putting electrons into and out of the entire lower surface of the charge storage layer 3h with a tunnel current, and the extension region 32 constituting the drain region using hot carriers. There is a method in which writing is performed by putting electrons into the end of the charge storage layer 3h in the vicinity, and erasing is performed by hot holes generated at the end of the extension region 32. The method using the tunnel current can increase the number of times of rewriting and ensure high reliability. On the other hand, in the method using the hot carrier, the operation voltage for writing / erasing can be lowered and the operation speed can be increased. can do.

  Hereinafter, the circuit operation of the MONOS memory Mn will be described with reference to FIGS. FIGS. 16A, 17A, and 18A are circuit diagrams of the MONOS memory Mn. FIGS. 16B, 17B, and 18B are cross-sectional views of the MONOS memory Mn.

  The MONOS memory has a high potential difference between the drain region and the semiconductor substrate, and between the drain region and the semiconductor substrate, depending on the method of writing and erasing information, and between the drain region and the semiconductor substrate. This is different from the case where a potential difference does not occur between the source region and the semiconductor substrate. That is, depending on the memory writing and erasing methods, the breakdown voltage between the source region and the well can be maintained even when the source region has a lower breakdown voltage than the drain region.

  Here, in a part of a plurality of MONOS memories, information is erased by injecting holes into the entire surface of the channel, and information is written by injecting electrons into the entire surface of the channel. This will be described with reference to 16 (a) and (b).

  Of the four memory cells M1 to M4 shown in FIG. 16 (b), the leftmost memory cell M1 corresponds to the memory cell M1 shown in FIG. 16 (a), and 2 from the left in FIG. 16 (b). The th memory cell M2 corresponds to the memory cell M2 shown in FIG. The second memory cell M3 from the right in FIG. 16B corresponds to the memory cell M3 shown in FIG. 16A, and the rightmost memory cell M4 in FIG. Corresponds to the memory cell M4 shown in FIG.

  As shown in FIGS. 16A and 16B, the memory cell M1 is formed on the semiconductor substrate SB via the ONO film 3 having the charge storage layer and the upper surface of the semiconductor substrate SB. This is an n-channel type memory cell having a source S1 and a drain D1. Similarly, the memory cell M2 has a gate G1, a source S2, and a drain D2, the memory cell M3 has a gate G2, a source S1, and a drain D1, and the memory cell M4 has a gate G2, a source S2, and a drain D2. Note that here, the memory cells M1 to M4 all have sidewalls having the same width on both sides of the gate, and extension regions having the same width are formed on both sides of the gate below the sidewall. . The memory cell M1 has extension regions 31b and 32b, the memory cell M2 has extension regions 33b and 34b, the memory cell M3 has extension regions 35b and 36b, and the memory cell M4 has extension regions 37b and 38b. . The memory cells M1 to M4 are n-channel MONOS memories, and the memory cells M1 to M4 are all formed on a p-type well formed on the main surface of the semiconductor substrate SB.

  The memory cells M1 to M4 are respectively formed on the same substrate, and the potential of the semiconductor substrate (p well) SB has the same potential below the memory cells M1 to M4. The gates G1 of the memory cells M1 and M2 are electrically connected, and the gates G2 of the memory cells M3 and M4 are electrically connected. Further, the source S1 of the memory cell M1 and the memory cell M3 is electrically connected, and the source S2 of the memory cell M2 and the memory cell M4 is electrically connected. The drains D1 of the memory cells M1 and M3 are electrically connected, and the drains D2 of the memory cells M2 and M4 are electrically connected.

  Note that the circuits shown in FIGS. 17A and 18A have the same structure as the circuit shown in FIG. 16A, and the semiconductor device shown in FIGS. 17B and 18B. 16 has the same structure as that of the semiconductor device shown in FIG. 16B, but FIGS. 16A and 16B, FIGS. 17A and 17B, and FIGS. 18A and 18B. And the voltage application conditions are different.

  First, the erase operation of the MONOS memory will be described. In the erase operation of the MONOS memory, information is erased in units of word lines as shown in FIG. That is, one or a plurality of MONOS memories connected to the same word line (gate) are selected, and the information written in each memory is erased by this erasing operation. In FIG. 16A, a selected memory cell from which information is erased by an erase operation is surrounded by a broken line.

  At this time, for example, a voltage of −8.5V is applied to the gates G1 of the selected memory cells (selected memory cells) M1 and M2, and 1.5V is applied to the sources S1 and S2, the drains D1 and D2, and the semiconductor substrate SB. Are respectively applied. Further, for example, a voltage of 1.5 V is applied to the gate G2, the sources S1 and S2, the drains D1 and D2, and the semiconductor substrate SB of the unselected memory cells (non-selected memory cells) M3 and M4.

  In this erasing operation, as shown in FIG. 16B, holes are injected into the charge storage layer in the ONO film 3 from the channel regions of the memory cells M1 and M2 through the entire lower surface of the ONO film 3. The information in the cells M1 and M2 is erased. At this time, since a voltage of 1.5 V is applied to the sources S1 and S2, the drains D1 and D2, and the semiconductor substrate SB of the memory cells M1 to M4, respectively, between each source / drain region and the semiconductor substrate SB. Almost no potential difference occurs. That is, there is almost no potential difference between the source / drain region and the well, so that the source / drain region does not require a high breakdown voltage in this erase operation.

  Next, the write operation of the MONOS memory will be described. The writing operation includes a method of injecting electrons from the entire surface of the channel into the charge storage layer of the MONOS memory and a method of performing hot electron injection into the charge storage layer of the MONOS memory near the drain.

  When writing is performed by injecting electrons into the charge storage layer of the MONOS memory from the entire channel surface, a voltage of 1.5 V, for example, is applied to the gate G1 of the memory cell M1, which is the selected memory cell, as shown in FIG. The voltage of −11.0 V is applied to the source S1, the drain D1, and the semiconductor substrate SB. Further, for example, a voltage of 1.5 V is applied to the source S2 and the drain D2 of the memory cells M2 and M4 which are non-selected memory cells. Further, for example, a voltage of −11.0 V is applied to the gates G2 of the memory cells M3 and M4 which are non-selected memory cells. In FIG. 17A, a selected memory cell into which information is written by a write operation is surrounded by a broken line.

  In this write operation, as shown in FIG. 17B, electrons are emitted from the channel region of the memory cell M1, which is the selected memory cell, to the charge storage layer in the ONO film 3 through the entire lower surface of the ONO film 3. The information is written into the memory cell M1.

  At this time, since a voltage of −11.0 V is applied to the source S1, the drain D1 and the semiconductor substrate SB of the memory cell M1, a potential difference is almost generated between the source / drain region and the semiconductor substrate SB. Absent.

  In the memory cell M2, which is a non-selected memory cell, a voltage of 1.5V is applied to the source S2 and the drain D2, and a voltage of -11.0V is applied to the semiconductor substrate SB. A positive voltage of 5 V is applied, and a channel is formed between the source S2 and the drain D2 in the memory cell M2, and the junction breakdown between the source S2 and the semiconductor substrate SB and between the drain D2 and the semiconductor substrate SB is formed. The potential difference between the source / drain regions and the semiconductor substrate SB does not cause a problem because the electric field under the edge of the gate G2 that causes the decrease is weakened.

  In addition, in the memory cell M3 that is a non-selected memory cell, a voltage of −11.0 V is applied to the source S1, the drain D1, and the semiconductor substrate SB, respectively, and therefore, between the source / drain region and the semiconductor substrate SB. Almost no potential difference occurs.

  That is, in the memory cells M1 to M3, there is almost no potential difference between the source / drain region and the well, or the electric field is alleviated. Therefore, in this write operation, each source / drain region requires a high breakdown voltage. And not.

  However, on the other hand, in the memory cell M4 which is a non-selected memory cell, a voltage of 1.5V is applied to the source S2 and the drain D2, and a voltage of -11.0V is applied to the semiconductor substrate SB. Further, since a negative voltage of -11.0 V is applied to the gate G4 of the memory cell M4, the electric field between the source and the drain is strengthened. In such a case, in particular, the channel region in the vicinity of the end of the gate G4 in the gate length direction shown in FIG. 17B, that is, the well between the extension region 37b and the extension region 38b, and the extension regions 37b, 38b. The electric field in the vicinity of the end of the is increased. Therefore, the potential difference between the source and the well and the potential difference between the drain and the well are about 12V. That is, since a high potential difference is generated between the source / drain region and the well in the memory cell M4, both the source region and the drain region of the memory cell M4 require a high breakdown voltage in this writing operation. Therefore, it is desirable to use a wide sidewall 6W for the MONOS memory.

  Next, a method for writing in the MONOS memory by injecting hot electrons into the charge storage layer of the MONOS memory near the drain will be described. In this case, as shown in FIG. 18A, for example, a voltage of 7.0 V is applied to the gate G1 of the memory cell M1, which is the selected memory cell, and a voltage of 0 V is applied to the source S1 and the semiconductor substrate SB, respectively. A voltage of 5.0 V is applied to the drain D1. Further, a voltage of, for example, 0V is applied to the source S2 and the drain D2 of the memory cells M2, M4 that are non-selected memory cells, and a voltage of, for example, 0V is applied to the gate G2 of the memory cells M3, M4 that are non-selected memory cells. A voltage is applied. In FIG. 18A, a selected memory cell into which information is written by a write operation is surrounded by a broken line.

  In this write operation, as shown in FIG. 18B, hot electrons are applied from the channel region in the vicinity of the drain D1 of the memory cell M1, which is the selected memory cell, to the charge storage layer in the ONO film 3 in the vicinity of the drain region. The information is written into the memory cell M1.

  At this time, a voltage of 0V is applied to the source S1 and the semiconductor substrate SB of the memory cell M1, a voltage of 5V is applied to the drain D1, and a positive voltage of 7V is applied to the gate G1. Yes. In this state, the channel in the vicinity of the drain D1 is in a pinch-off state, and the electric field between the drain D1 and the semiconductor substrate SB is positively increased and hot electrons are easily generated.

  Further, since a voltage of 0 V is applied to the source S2, the drain D2 and the semiconductor substrate SB of the memory cells M2 and M4 which are non-selected memory cells, respectively, between each source / drain region and the semiconductor substrate SB. Almost no potential difference occurs. Further, in the memory cell M3 that is a non-selected memory cell, a voltage of 0 V is applied to the source S1 and the semiconductor substrate SB, respectively, and a voltage of 5 V is applied to the drain D1. At this time, almost no potential difference is generated between the source S1 of the memory cell M3 and the semiconductor substrate SB, but a relatively high potential difference of about 5 V is generated between the drain D1 and the semiconductor substrate SB. At this time, although the gate G2 is 0 V, a weak write state (disturb) is caused by hot electrons generated in the vicinity of the drain D1. However, on the drain D1 side, since a wide sidewall and extension region are applied, the structure is resistant to disturbance.

  That is, in the memory cells M1, M2 and M4, there is almost no potential difference between the source / drain region and the well. Therefore, in this write operation, each source / drain region does not require a high breakdown voltage. However, in the memory cell M3, almost no potential difference is generated between the source region and the well, whereas a relatively high potential difference is generated between the drain region and the well. Therefore, the drain D2 is high between the well and the well. Requires pressure resistance. Therefore, it is desirable to use a wide sidewall 6W for the MONOS memory.

  Next, effects of the low breakdown voltage MISFET Ln, the first high breakdown voltage MISFET H1, and the first high breakdown voltage MISFET H2 of the present embodiment will be described.

  When a plurality of elements operating at different voltages are formed on the same semiconductor substrate SB, such as the low breakdown voltage MISFET Ln and the first high breakdown voltage MISFET H1 or the low breakdown voltage MISFET Ln and the MONOS memory Mn shown in FIG. It is preferable to form extension regions having different widths in the respective elements using.

  For example, as in the low breakdown voltage MISFET Ln and the first high breakdown voltage MISFET H1, the first side having different widths (spacer lengths) in the gate length direction of the gate electrodes 4b and 4c is formed on the sidewalls of the gate electrode 4b and the gate electrode 4c. By forming the wall 6w and the second sidewall 6n, respectively, the width of the extension region formed below the first sidewall 6w and the second sidewall 6n is different between the low breakdown voltage MISFET Ln and the first high breakdown voltage MISFET H1. Can be length. As shown in FIG. 1, the widths of the extension regions 33 and 34 are smaller than the widths of the extension regions 35 and 36. Therefore, the resistance values of the extension regions 35 and 36 between the diffusion layer 45 and the diffusion layer 46 are higher than the resistance values of the extension regions 33 and 34 between the diffusion layer 43 and the diffusion layer 44.

  Thereby, even when a voltage higher than the voltage applied to the diffusion layer 43 or the diffusion layer 44 of the low breakdown voltage MISFET Ln is applied to the diffusion layer 45 or the diffusion layer 46 of the first high breakdown voltage MISFET H1, the first high breakdown voltage MISFET H1 Since the extension regions 35 and 36 having a relatively long width and a high resistance are provided, it is possible to prevent a leakage current from being generated between the diffusion layer 45 or the diffusion layer 46 and the gate electrode 4c. For the same reason, the breakdown voltage between the diffusion layer 45 or the diffusion layer 46 and the p-well 2c can be maintained.

  Further, by separately forming the extension regions 33 and 34 and the extension regions 35 and 36 having different widths by using the two kinds of LDD processes, the high breakdown voltage is not required while ensuring the breakdown voltage of the first high breakdown voltage MISFET H1. It is possible to prevent the current between the diffusion layer 43 and the diffusion layer 44 from being reduced by the resistance of the extension regions 33 and 34 of the low breakdown voltage MISFET Ln.

  Thus, a voltage higher than that of the low breakdown voltage MISFET is applied to both the source region and the drain region, and a MISFET that requires a relatively high breakdown voltage in both the source region and the drain region has a longer width than the low breakdown voltage MISFET. It is desirable to have an LDD structure in which extension regions having s are provided in both the source region and the drain region.

  However, even in a MISFET that requires a higher breakdown voltage than the low breakdown voltage MISFET Ln, a high breakdown voltage is required in the drain region, but a MISFET that does not require a high breakdown voltage like the drain region is also formed in the source region. May be. That is, the source region of the MISFET that does not require a high breakdown voltage in the source region does not require a breakdown voltage as high as that of the diffusion layer 45 constituting the source region of the second high breakdown voltage MISFET H2, and thus the extension region 33 of the low breakdown voltage MISFET Ln. Similarly to the above, there is no problem even if an extension region having a small width is provided.

  That is, some high breakdown voltage MISFETs, like the second high breakdown voltage MISFET H2, require a high breakdown voltage in the drain region and do not require a high breakdown voltage in the source region. When an extension region having a long width is formed in the source region of such a high breakdown voltage MISFET, the current flowing between the source and the drain becomes smaller than necessary. That is, the extension region is a region having a higher resistance than the source region, and if the width of the extension region is increased, the resistance value between the source and the drain is increased correspondingly, which hinders the speeding up of the operation of the semiconductor device. .

  In addition, the contact plug for supplying a specific potential to the source region must be arranged away from the gate electrode by the width of the extension region. Therefore, when the extension region having a long width is formed even in the source region of the MISFET that does not require a high breakdown voltage in the drain region and the source region does not need a high breakdown voltage, the extension region of the source region has a long width. Therefore, it is necessary to ensure a long distance between the contact plug and the contact plug, which makes it difficult to miniaturize the semiconductor device.

  On the other hand, in the semiconductor device of the present embodiment, like the second high breakdown voltage MISFET H2 shown in FIG. 1, among the side walls on both sides of the gate electrode 4d, on one side wall on the diffusion layer 48 side constituting the drain region. A first sidewall 6w having a large width (spacer length) is formed, and a second sidewall having a width (spacer length) smaller than that of the first sidewall 6w is formed on the side wall on the diffusion layer 47 side constituting the other source region. Sidewalls 6n are formed. As will be described later, since the width of the extension region is substantially defined by the width of the upper sidewall, the width of the extension region 38 below the first sidewall 6w is equal to the extension region 37 below the second sidewall 6n. Greater than the width of

  Since the second high breakdown voltage MISFET H2 is a MISFET having a drain region that requires a high breakdown voltage and a source region that does not require a high breakdown voltage, as described above, the second high breakdown voltage MISFET H2 is an extension region 37 on the diffusion layer 47 side that constitutes the source region. By making the width smaller than the width of the extension region 38 on the diffusion layer 48 side constituting the drain region, the current flowing between the source and the drain is prevented from being reduced. Thereby, since the current flowing between the source and the drain can be increased, the operation speed of the semiconductor device can be increased.

  The second high breakdown voltage MISFET H2 has a longer extension region like the first high breakdown voltage MISFET H1 by making the width of the extension region 37 on the diffusion layer 47 side smaller than the width of the extension region 38 on the diffusion layer 48 side. Compared with the case of forming 35, the contact plug 13 for supplying a potential to the diffusion layer 47 can be disposed closer to the gate electrode 4d. As a result, the semiconductor device can be miniaturized in the gate length direction of the gate electrode 4d by narrowing the width of the extension region 37 of the second high voltage MISFET H2.

  Next, the manufacturing method of this Embodiment is demonstrated using FIGS. 2 to 14 are cross-sectional views showing a method of manufacturing a semiconductor device when the MONOS memory, the low breakdown voltage MISFET, the first high breakdown voltage MISFET, and the second high breakdown voltage MISFET are formed on the same substrate. 2 to 14 show the MONOS memory formation region 1A, the low breakdown voltage MISFET formation region 1B, the first high breakdown voltage MISFET formation region 1C, and the second high breakdown voltage MISFET formation region 1D in order from the left. 2A is a cross-sectional view showing a method for manufacturing a semiconductor device, and FIG. 2B is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 2A. 4A is a cross-sectional view showing a method for manufacturing the semiconductor device subsequent to FIG. 3, and FIG. 4B is a cross-sectional view showing a method for manufacturing the semiconductor device subsequent to FIG. 4A.

  First, as shown in FIG. 2A, a semiconductor substrate (semiconductor wafer) SB made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. Subsequently, the element isolation layer 1 is formed on the main surface of the semiconductor substrate SB. The element isolation layer 1 is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation layer 1 can be formed of an insulating film embedded in a groove (element isolation groove) 1a formed in the semiconductor substrate SB.

  Next, a region for forming a MONOS memory (MONOS memory formation region 1A), a region for forming a low breakdown voltage MISFET (low breakdown voltage MISFET formation region 1B), and a region for forming a first high breakdown voltage MISFET (first high breakdown voltage). The p wells 2a, 2b, 2c, and 2d are formed in the breakdown voltage MISFET formation region 1C) and the second high breakdown voltage MISFET formation region (second high breakdown voltage MISFET formation region 1D), respectively. At this time, the p wells 2a, 2b, 2c and 2d are formed by ion-implanting a p-type impurity such as boron (B) into the upper surface of the semiconductor substrate SB. The p wells 2a, 2b, 2c, and 2d can be made to have different impurity concentrations by allocating impurities in separate steps using photolithography technology.

  Here, it is desirable to form a silicon oxide film OX as a through film on the upper surface of the semiconductor substrate SB before ion implantation for forming the p wells 2a, 2b, 2c and 2d. The silicon oxide film OX is an insulating film formed by heat treatment, for example, and functions to prevent the semiconductor substrate SB from being damaged by ion implantation when forming the p wells 2a, 2b, 2c, and 2d.

  Next, as shown in FIG. 2B, the silicon oxide film OX on the semiconductor substrate SB is removed by dry etching or wet etching, and the first high-breakdown-voltage MISFET formation region 1C and the first 2 After the thick film insulating film 3f is formed in the high breakdown voltage MISFET formation region 1D, the thin film insulation film 3e is formed in the MONOS memory formation region 1A and the low breakdown voltage MISFET formation region 1B.

  That is, a thick silicon oxide film is formed (deposited) on the entire main surface of the semiconductor substrate SB from which the silicon oxide film OX has been removed by thermal oxidation or CVD (Chemical Vapor Deposition). The first high breakdown voltage MISFET formation region 1C and the second high breakdown voltage MISFET formation region 1D are covered with a photoresist film. Subsequently, the thick silicon oxide film in the MONOS memory formation region 1A and the low breakdown voltage MISFET formation region 1B is selectively removed by dry etching or wet etching using the photoresist film as a mask, and the first high breakdown voltage MISFET formation region 1C and After forming the thick insulating film 3f made of the thick silicon oxide film in the second high breakdown voltage MISFET formation region 1D, the photoresist film is removed by ashing. Thereafter, the surface of the semiconductor substrate SB is thermally oxidized to form a thin film insulating film 3e on the upper surface of the semiconductor substrate SB in the MONOS memory formation region 1A and the low breakdown voltage MISFET formation region 1B, thereby performing two-type gate oxidation. The thin film insulating film 3e is composed of a silicon oxide film having a thickness smaller than that of the thick film insulating film 3f. At this time, the upper surfaces of the p wells 2c and 2d under the thick insulating film 3f in the first high breakdown voltage MISFET formation region 1C and the second high breakdown voltage MISFET formation region 1D are also slightly oxidized. Moreover, the manufacturing method of the thin film insulating film 3e and the silicon oxide film OX shown in FIG. 2A is not limited to the thermal oxidation method, and may be formed by ISSG (In-Situ Steam Generation) oxidation treatment or CVD method.

  As a result, a thick insulating film 3f having a relatively large thickness is formed in the first high breakdown voltage MISFET formation region 1C and the second high breakdown voltage MISFET formation region 1D, and in the MONOS memory formation region 1A and the low breakdown voltage MISFET formation region 1B. A relatively thin thin film insulating film 3e is formed. Thereafter, a polysilicon film 4f as a conductor film is deposited on the entire main surface of the semiconductor substrate SB by a CVD method or the like.

  Next, as shown in FIG. 3, after selectively removing the polysilicon film 4f and the thin film insulating film 3e in the MONOS memory formation region 1A using photolithography technology and dry etching, the entire upper surface of the semiconductor substrate SB is formed. Further, a bottom oxide film 3g made of a silicon oxide film, a charge storage layer 3h made of a silicon nitride film, a top oxide film 3i made of a silicon oxide film, and a polysilicon film 4e are sequentially formed by a thermal oxidation method or a CVD method.

  Next, as shown in FIG. 4A, the polysilicon film 4e, the top oxide film 3i, the charge storage layer 3h, and the bottom oxide film 3g in the MONOS memory formation region 1A are patterned using photolithography and dry etching. Then, the gate electrode 4a made of the polysilicon film 4e and the ONO film 3a made of the bottom oxide film 3g, the charge storage layer 3h, and the top oxide film 3i are formed. At this time, the top oxide film 3i, the charge storage layer 3h, and the bottom oxide film on the polysilicon film 4f formed in the low breakdown voltage MISFET formation region 1B, the first high breakdown voltage MISFET formation region 1C, and the second high breakdown voltage MISFET formation region 1D. 3 g is removed.

  Subsequently, using the photolithography technique and dry etching, the polysilicon film 4f, the thin film insulating film 3e, and the thick film in the low breakdown voltage MISFET formation region 1B, the first high breakdown voltage MISFET formation region 1C, and the second high breakdown voltage MISFET formation region 1D. The insulating film 3f is patterned. Thus, gate electrodes 4b, 4c and 4d made of the polysilicon film 4f are formed in the low breakdown voltage MISFET formation region 1B, the first high breakdown voltage MISFET formation region 1C and the second high breakdown voltage MISFET formation region 1D, respectively. Further, a gate insulating film 3b made of a thin film insulating film 3e is formed on the semiconductor substrate SB in the low breakdown voltage MISFET formation region 1B, and on the semiconductor substrate SB in the first high breakdown voltage MISFET formation region 1C and the second high breakdown voltage MISFET formation region 1D. Then, gate insulating films 3c and 3d made of the thick film insulating film 3f are respectively formed.

  In other words, in the MONOS memory formation region 1A, the gate electrode 4a serving as the memory gate of the MONOS memory is formed on the upper surface of the semiconductor substrate SB on which the p well 2a is formed via the ONO film 3a. In the low breakdown voltage MISFET formation region 1B, a gate electrode 4b is formed on the upper surface of the semiconductor substrate SB on which the p-well 2b is formed via a gate insulating film 3b. In the first high breakdown voltage MISFET formation region 1C, a gate electrode 4c is formed on the upper surface of the semiconductor substrate SB on which the p well 2c is formed via the gate insulating film 3c, and the second high breakdown voltage MISFET formation region 1D is formed. A gate electrode 4d is formed on the upper surface of the semiconductor substrate SB on which the p-well 2d is formed via a gate insulating film 3d. The gate insulating film 3b is thinner than either the gate insulating film 3c or 3d, and the gate length of the gate electrode 4b is shorter than either of the gate electrodes 4c or 4d.

Next, as shown in FIG. 4B, an n-type impurity (for example, P (phosphorus)) is ion-implanted into the main surface of the semiconductor substrate SB, whereby the main surface of the semiconductor substrate SB in the MONOS memory formation region 1A. Then, extension regions 31 and 32 which are n ⁻ type semiconductor regions are formed. The extension region 31 is formed on the upper surface of the semiconductor substrate SB in one region on both sides of the gate electrode 4a, and the extension region 32 is formed on the upper surface of the semiconductor substrate SB in the other region of the gate electrode 4a.

Similarly, extension regions 33 and 34, which are n ⁻ type semiconductor regions, are formed on the main surface of the semiconductor substrate SB in the low breakdown voltage MISFET formation region 1B, and are formed on the main surface of the semiconductor substrate SB in the first high breakdown voltage MISFET formation region 1C. n ^- to form extension regions 35 and 36 is a type of semiconductor region, n on the main surface of the semiconductor substrate SB of the second high breakdown voltage MISFET formation region 1D ^- to form extension regions 37 and 38 is a type of semiconductor regions. Note that the extension regions 31 and 32 of the MONOS memory formation region 1A may be formed individually.

  Next, as shown in FIG. 5, the insulating film 6a made of a silicon oxide film, the insulating film 6 made of a silicon nitride film, and the insulating film 7 made of a silicon oxide film are formed on the entire main surface of the semiconductor substrate SB by, for example, the CVD method. Are sequentially formed.

  Next, as shown in FIG. 6, a part of the insulating film 7 is removed by anisotropic etching to expose a part of the surface of the insulating film 6. Thereby, the insulating film 7 remains in a sidewall shape on the side wall of the insulating film 6 covering the gate electrodes 4a to 4d.

  Next, as shown in FIG. 7, a photoresist film PR is formed on the semiconductor substrate SB so that the low breakdown voltage MISFET formation region 1B and a part of the second high breakdown voltage MISFET H2 are exposed. At this time, the MONOS memory formation region 1A and the first high breakdown voltage MISFET formation region 1C are completely covered with the photoresist film PR, and the low breakdown voltage MISFET formation region 1B is not covered with the photoresist film PR but is exposed. In the second high breakdown voltage MISFET formation region 1D, the side wall of the gate electrode 4d on which the extension region 38 is formed is covered with the insulating film 7 formed in a sidewall shape via the insulating films 6a and 6. A photoresist film PR is formed. On the other hand, the insulating film 7 formed in a sidewall shape on the side wall of the gate electrode 4d where the extension region 37 of the second high breakdown voltage MISFET forming region 1D is formed is formed as a photoresist film PR via the insulating films 6a and 6. Do not cover and expose.

  Here, for example, it is assumed that the photoresist film PR exposes a region from directly above the gate electrode 4d to directly above the element isolation layer 1 in contact with the extension region 37.

  Next, as shown in FIG. 8, using the photoresist film PR as a mask, dry etching or wet etching is used to form both sides of the gate electrode 4b of the low breakdown voltage MISFET formation region 1B exposed from the photoresist film PR. The insulating film 7 and the insulating film 7 formed on one side wall of the gate electrode 4d in the second high breakdown voltage MISFET formation region 1D are selectively removed.

  Next, as shown in FIG. 9, after the photoresist film PR is removed by ashing, a part of each of the insulating films 7, 6 and 6a is removed by dry etching, and gate electrodes 4a to 4d, extension regions are removed. The upper surfaces of 31 to 38 are exposed.

  As a result, in the MONOS memory formation region 1A, the first sidewalls 6w made of the insulating films 6a, 6 and 7 are formed on the sidewalls on both sides of the gate electrode 4a. In the low breakdown voltage MISFET formation region 1B, second sidewalls 6n made of insulating films 6a and 6 are formed on the sidewalls on both sides of the gate electrode 4b. In the first high breakdown voltage MISFET formation region 1C, first sidewalls 6w made of insulating films 6a, 6 and 7 are formed on the sidewalls on both sides of the gate electrode 4c. In the second high breakdown voltage MISFET formation region 1D, the insulating films 6a and 6 are formed on one side wall on the side where the extension region 37 is formed on the upper surface of the semiconductor substrate SB among the side walls on both sides of the gate electrode 4d. A second sidewall 6n is formed, and a first sidewall 6w made of insulating films 6a, 6 and 7 is formed on the other sidewall on the side where the extension region 38 is formed on the upper surface of the semiconductor substrate SB.

  In this etching process, since the insulating films 6 and 6a formed under the insulating film 7 remain without being removed, the width (spacer length) of the first sidewall 6w in the gate length direction of the adjacent gate electrode is as shown in FIG. 5 is almost the same as the total length of the insulating films 6a, 6 and 7 in the film forming process described with reference to FIG. On the other hand, the side walls on both sides of the gate electrode 4b of the low breakdown voltage MISFET formation region 1B from which the insulating film 7 has been removed in the step described with reference to FIG. 8 and one of the gate electrodes 4d of the second high breakdown voltage MISFET formation region 1D. The second side wall 6n (see FIG. 9) formed on the side wall has a width (spacer length) in the gate length direction of the adjacent gate electrode of the insulating films 6a and 6 in the film forming process described with reference to FIG. It is almost the same as the total length of each film thickness.

  That is, since the second sidewall 6n does not have the insulating film 7, the width (spacer length) is smaller than that of the first sidewall 6w.

  Thus, the sidewalls on both sides of the gate electrode 4b in the low breakdown voltage MISFET formation region 1B are formed on the sidewalls on both sides of the gate electrode 4a in the MONOS memory formation region 1A and the sidewalls on both sides of the gate electrode 4c in the first high breakdown voltage MISFET formation region 1C. A second side wall 6n having a smaller width (spacer length) than the first side wall 6w formed is formed.

  In addition, the insulating film 7 on one side wall of the gate electrode 4d in the second high breakdown voltage MISFET formation region 1D is removed by the etching process described with reference to FIG. 8, and one of the gate electrodes 4d is removed in the etching process shown in FIG. A second side wall 6n is formed on the side wall, and a first side wall 6w is formed on the other side wall. That is, sidewalls having the same width (spacer length) are formed on both sidewalls of the gate electrodes 4a to 4c, but the first sidewall having a different width (spacer length) is formed on both sidewalls of the gate electrode 4d. 6w and the second sidewall 6n are formed.

Next, as shown in FIG. 10, an n-type impurity (for example, P (phosphorus)) is ion-implanted into the upper surface of the semiconductor substrate SB at a relatively high concentration, so that the semiconductor substrate SB in the MONOS memory formation region 1A is formed. Diffusion layers 41 and 42 which are n ⁺ type semiconductor regions are formed on the main surface. Similarly, diffusion layers 43 and 44, which are n ⁺ type semiconductor regions, are formed on the main surface of the semiconductor substrate SB in the low breakdown voltage MISFET formation region 1B, and on the main surface of the semiconductor substrate SB in the first high breakdown voltage MISFET formation region 1C. the n ⁺ -type diffusion layer 45, 46 is a semiconductor region formed to form a second high breakdown voltage MISFET formation region 1D of the semiconductor substrate SB diffusion layers 47 and 48 is a semiconductor region of the ^{n +} -type on the main surface of the. Since the diffusion layers 41 to 48 have a higher impurity concentration than the extension regions 31 to 38, the diffusion layers 41 to 48 have a higher conductivity than the extension regions 31 to 38.

  Here, the diffusion layers 41, 42 and 45 to 48 are formed with a shallower junction depth than the adjacent extension regions 31, 32 and 35 to 38, respectively. Accordingly, the extension layers 31, 32, and 35 to 38 having higher resistance than the respective diffusion layers are interposed between the low resistance diffusion layers 41, 42, and 45 to 48 and the semiconductor substrate SB, respectively. The withstand voltage between 41, 42 and 45 to 48 and the semiconductor substrate SB can be increased. For the same reason, the breakdown voltage between the diffusion layers 41 and 42 and the gate electrode 4a, between the diffusion layers 45 and 46 and the gate electrode 4c, and between the diffusion layers 47 and 48 and the gate electrode 4d can be increased.

  On the other hand, in the low breakdown voltage MISFET formation region 1B, there is no high potential difference between the diffusion layers 43 and 44 and the p well 2b, unlike the source / drain region and the well of the first high breakdown voltage MISFET H1. It is not necessary to make the junction depth of the layers 43 and 44 shallower than the extension regions 33 and 34. Here, the diffusion layers 43 and 44 are formed deeper from the upper surface of the semiconductor substrate SB than the extension regions 33 and 34.

  In the present embodiment, the diffusion depths of the diffusion layers 41, 42 and 45 to 48 are formed to be shallower than the extension regions 31, 32 and 35 to 38, respectively. If the breakdown voltage between 45 and 48 and the semiconductor substrate SB can be secured, the junction depths of the diffusion layers 41, 42 and 45 to 48 are deeper than the extension regions 31, 32 and 35 to 38, respectively. It may be formed.

  Through the above steps, the MONOS memory Mn having the ONO film 3a, the gate electrode 4a, the extension regions 31 and 32, and the diffusion layers 41 and 42 is formed in the MONOS memory formation region 1A. In the low breakdown voltage MISFET formation region 1B, the low breakdown voltage MISFET Ln having the gate electrode 4b, the extension regions 33 and 34, and the diffusion layers 43 and 44 is formed. In the first high breakdown voltage MISFET formation region 1C, the first high breakdown voltage MISFET H1 having the gate electrode 4c, the extension regions 35 and 36, and the diffusion layers 45 and 46 is formed. In the second high breakdown voltage MISFET formation region 1D, a second high breakdown voltage MISFET H2 having a gate electrode 4d, extension regions 37 and 38, and diffusion layers 47 and 48 is formed.

  The diffusion layer 41 and the extension region 31 function as a source region of the MONOS memory Mn, and the diffusion layer 42 and the extension region 32 are semiconductor regions that function as a drain region of the MONOS memory Mn. Further, the diffusion layer 43 and the extension region 33 function as a source region region of the low breakdown voltage MISFET Ln, and the diffusion layer 44 and the extension region 34 are semiconductor regions that function as a drain region of the low breakdown voltage MISFET Ln. The diffusion layer 45 and the extension region 35 function as a source region of the first high voltage MISFET H1, and the diffusion layer 46 and the extension region 36 are semiconductor regions that function as a drain region of the first high voltage MISFET H1. The diffusion layer 47 and the extension region 37 function as a source region of the second high breakdown voltage MISFET H2, and the diffusion layer 48 and the extension region 38 are semiconductor regions that function as a drain region of the second high breakdown voltage MISFET H2.

  Here, the diffusion layers 41, 43, and 45 function as source regions, and the diffusion layers 42, 44, and 46 function as drain regions. Conversely, the diffusion layers 41, 43, and 45 serve as drain regions. The diffusion layers 42, 44 and 46 may function as source regions.

  Further, since the diffusion layers 41 to 48 are formed on the exposed upper surface of the semiconductor substrate SB, all the extension regions 31 to 38 remain below the second sidewall 6n or 6w, and the diffusion layers 41 to 48 are The extension regions 31 to 38 are formed in contact with each other. For example, on the upper surface of the semiconductor substrate SB, the end of the extension region 31 in the gate length direction of the gate electrode 4a opposite to the end in contact with the diffusion layer 41 is the end of the gate electrode 4a. Located near the bottom. Further, the other end of the extension region 31 on the upper surface of the semiconductor substrate SB is in contact with the diffusion layer 41, and is an end of the first sidewall 6w and a lower portion of the end that is not in contact with the gate electrode 4a. It is arranged in the vicinity. That is, the width of the extension region 31 on the upper surface of the semiconductor substrate SB is substantially defined by the width of the first sidewall 6w formed on the extension region 31.

  As described above, the low breakdown voltage MISFET Ln has the second sidewall 6n having a relatively small width, whereas the MONOS memory Mn and the first high breakdown voltage MISFET H1 have the first side having a width larger than that of the second sidewall 6n. It has a wall 6w. Since the width of the extension region on the upper surface of the semiconductor substrate SB below the sidewall is substantially defined by the width of the sidewall above the sidewall, the semiconductor substrate of the extension regions 33 and 34 formed below the second sidewall 6n. The width of the upper surface of the SB is smaller than the width of the upper surface of the semiconductor substrate SB of the extension regions 31, 32, 35, and 36 formed in the lower portion of the first sidewall 6w.

  That is, the low breakdown voltage MISFET Ln has extension regions 32 and 33 having a smaller width on the upper surface of the semiconductor substrate SB than the extension regions 31, 32, 35 and 36 of the MONOS memory Mn and the first high breakdown voltage MISFET H1. In this way, extension regions 33 and 34 having a short width are formed in the low breakdown voltage MISFET Ln that does not require a high breakdown voltage in the source / drain regions, and the MONOS memory Mn that requires a breakdown voltage higher than that of the low breakdown voltage MISFET Ln is formed. The extension regions 31 and 32 having a width larger than the extension regions 33 and 34 are formed. Similarly, extension regions 35 and 36 having a width wider than the extension regions 33 and 34 are formed in the first high breakdown voltage MISFET H1.

  As a result, the extension regions 31 to 38 have a lower impurity concentration than the diffusion layers 41 to 48 and are high resistance semiconductor regions. Therefore, by forming the extension regions 31, 32, 35, and 36 having relatively large widths, The breakdown voltage between the gate electrodes 4a and 4b of the MONOS memory Mn and the first high breakdown voltage MISFET H1 and the source / drain regions can be increased. Further, by forming extension regions 33 and 34 having relatively small widths in the low breakdown voltage MISFET Ln that does not require a high breakdown voltage in the source / drain regions, it is possible to suppress the resistance value of the extension region from becoming higher than necessary, The current flowing between the source and the drain is prevented from becoming small. In this manner, by forming extension regions having different lengths for elements having different required withstand voltages, a two-type LDD structure can be formed.

  On the other hand, in the second high voltage MISFET H2, the second sidewall 6n is formed on one of the side walls on both sides of the gate electrode 4d, and the first sidewall 6w is formed on the other side wall. The width of the extension region 37 on the upper surface is smaller than the width of the extension region 38. That is, between the diffusion layer 47 and the diffusion layer 48, the extension region 38 having a width longer than the extension region 37 has a higher resistance value than the extension region 37. Accordingly, the diffusion layer 47 and the extension region 37 function as the source region of the second high breakdown voltage MISFET H2, and the diffusion layer 48 and the extension region 38 are the semiconductor regions that function as the drain region of the second high breakdown voltage MISFET H2. The drain region of the breakdown voltage MISFET H2 has a higher resistance value and a higher breakdown voltage than the source region.

  Next, as shown in FIG. 11, silicide layers 9 are formed on the surfaces of the gate electrodes 4a to 4d and the diffusion layers 41 to 48 by a known salicide process. As a silicidation procedure, first, a metal film is deposited on the main surface of the semiconductor substrate SB by sputtering, and then the semiconductor substrate SB is heat treated, and then the unreacted metal film is removed by wet etching, thereby forming a silicide layer. 9 is formed. Examples of the member of the silicide layer 9 include nickel silicide, cobalt silicide, titanium silicide, and platinum silicide.

  Next, as shown in FIG. 12, a stopper insulating film 10 made of a silicon nitride film and an interlayer insulating film 11 made of a silicon oxide film are sequentially formed (deposited) on the entire main surface of the semiconductor substrate SB by, eg, CVD. To do.

  Next, as shown in FIG. 13, contact holes 12 reaching the silicide layers 9 formed on the upper surfaces of the diffusion layers 41 to 48 from the upper surface of the interlayer insulating film 11 are formed.

  Subsequently, after forming a thin barrier conductor film such as titanium or titanium nitride in the contact hole 12, the contact hole 12 is filled with a tungsten film, thereby forming the contact plug 13 made of the tungsten film. In other regions not shown, contact holes and contact plugs reaching the silicide layers 9 formed on the respective upper portions of the gate electrodes 4a to 4d from the upper surface of the interlayer insulating film 11 are formed by the same process.

  Next, as shown in FIG. 14, the stopper insulating film 14, the interlayer insulating film 15 and the metal wiring 17 are formed on the interlayer insulating film 11 and the contact plug 13 by a damascene process which is a well-known technique. A semiconductor device of the form is completed.

  That is, after the stopper insulating film 14 and the interlayer insulating film 15 are sequentially formed on the interlayer insulating film 11 and the contact plug 13 by the CVD method or the like, the interlayer insulating film 15 and the stopper insulating film 14 are used by photolithography and dry etching. Then, a wiring trench 16 exposing the upper surfaces of the interlayer insulating film 11 and the contact plug 13 is formed.

  Thereafter, a barrier conductor film made of tantalum, tantalum nitride, or the like or a laminated film thereof, and a conductor film mainly composed of copper are formed on the upper surface of the interlayer insulating film 15 and the inner wall and bottom of the wiring groove 16 by sputtering or the like. . Subsequently, the barrier conductor film and the conductor film are polished by a CMP (Chemical Mechanical Polishing) method to expose the upper surface of the interlayer insulating film 15, so that the barrier conductor film and the conductor film are formed inside the wiring groove 16. A metal wiring 17 made of is formed.

  In the present embodiment, as described above, when the extension regions having different widths are formed in the low breakdown voltage MISFET Ln, the MONOS memory Mn, and the first high breakdown voltage MISFET H1, the second high breakdown voltage MISFET formation region is formed in the process shown in FIG. One insulating film 7 on the side wall of the 1D gate electrode 4d is exposed, and the insulating film 7 is removed in the etching step shown in FIG. Thus, when the sidewalls are formed on the sidewalls of the gate electrodes by the etching process shown in FIG. 9, the second sidewall 6n having a short width and the first sidewall 6w having a large width are formed on the sidewall of the gate electrode 4d. After that, extension regions 37 and 38 having different widths are formed on the upper surface of the semiconductor substrate SB on both sides of the gate electrode 4d by the process shown in FIG.

  The drain region of the second high breakdown voltage MISFET H2 requires a higher breakdown voltage than the source region, and between the diffusion layer 47 constituting the source region and the p well 4d, the diffusion layer 48 constituting the drain region and the p well 4d Only a potential difference lower than the highest potential difference occurring during That is, no high potential difference occurs between the source and well of the second high breakdown voltage MISFET H2 as between the drain and well of the second high breakdown voltage MISFET H2. Similarly, no high potential difference occurs between the source and gate of the second high voltage MISFET H2 as between the drain and gate of the second high voltage MISFET H2.

  Therefore, even if the width of the extension region 37 on the diffusion layer 47 side is made smaller than the width of the extension region 38 on the diffusion layer 48 side, the region between the diffusion layer 47 (source region) and the p-well 2d or the diffusion layer 47 (source The breakdown voltage can be maintained between the region) and the gate electrode 4d. Thus, by making the width of the extension region 37 smaller than the width of the extension region 38 on the diffusion layer 48 side, it is possible to prevent the current flowing between the source and the drain from being reduced. That is, since the current flowing between the source and the drain can be increased, the operation speed of the semiconductor device can be increased.

  The second high breakdown voltage MISFET H2 has a longer extension region like the first high breakdown voltage MISFET H1 by making the width of the extension region 37 on the diffusion layer 47 side smaller than the width of the extension region 38 on the diffusion layer 48 side. Compared with the case of forming 35, the contact plug 13 for supplying a potential to the diffusion layer 47 can be disposed closer to the gate electrode 4d. That is, by narrowing the width of the extension region 37 of the second high breakdown voltage MISFET H2 on the upper surface of the semiconductor substrate SB, the semiconductor device can be miniaturized in the gate length direction of the gate electrode 4d.

  Note that although a semiconductor device having an n-channel MISFET and a MONOS memory is described as an example in this embodiment, the present invention may be applied to a p-channel MISFET. In this case, the p wells 2a to 2d shown in FIG. 1 are formed as n type wells, and the extension regions 31 to 38 and the diffusion layers 41 to 48 are formed as p type semiconductor regions.

  The present invention may be applied to a semiconductor device having an n-channel type MISFET and a MONOS memory and a p-channel type MISFET and a MONOS memory. That is, the present invention can be applied to a CMISFET (Complementary MISFET) having an n-channel MISFET and a p-channel MISFET.

(Embodiment 2)
In the first embodiment, the semiconductor device including the high breakdown voltage MISFET having the extension regions having different widths in the drain region and the source region has been described. In the present embodiment, similarly to the second high breakdown voltage MISFET H2 shown in FIG. 1 of the first embodiment, the source region and the drain region have extension regions having different widths, and the drain region requiring high breakdown voltage A semiconductor device including a MONOS memory having a source region that does not require a high breakdown voltage such as the drain region will be described.

  FIG. 15 is a cross-sectional view of the semiconductor device of this embodiment. As shown in FIG. 15, the MONOS memory Mn, the low breakdown voltage MISFET Ln, the first high breakdown voltage MISFET H1, and the second high breakdown voltage MISFET H2 are formed on the semiconductor substrate SB as in the first embodiment, and the low breakdown voltage MISFET Ln, The first high breakdown voltage MISFET H1 and the second high breakdown voltage MISFET H2 have the same structure as in the first embodiment.

  On the other hand, the MONOS memory Mn has a gate electrode 4a formed on the semiconductor substrate SB on which the p-well 2a is formed via the ONO film 3a, and one of the side walls of the gate electrode 4a has the above-described first embodiment. As in the first embodiment, a first sidewall 6w made of insulating films 6a, 6 and 7 is formed, and the other side wall of the gate electrode 4a is made of insulating films 6a and 6 unlike the first embodiment. A second sidewall 6n is formed.

  Of the upper surface of the semiconductor substrate SB on both sides of the gate electrode 4a, the extension region 31a and the diffusion layer 41a are formed on the side where the second sidewall 6n is formed, and the other first sidewall 6w is formed. An extension region 32 and a diffusion layer 42 are formed on the upper surface of the formed semiconductor substrate SB, as in the first embodiment.

  That is, in the semiconductor device according to the present embodiment, as shown in FIG. 15, the first sidewall 6w and the second sidewall 6n having different widths are formed on both sidewalls of the gate electrode 4a constituting the MONOS memory Mn. Is formed. 15 is formed on the upper surface of the semiconductor substrate SB below the first sidewall 6w and the extension region 31a formed on the upper surface of the semiconductor substrate SB below the second sidewall 6n. The semiconductor region has an extension region 32 that is narrower than the extension region 31a on the upper surface of the semiconductor substrate SB.

  That is, like the second high breakdown voltage MISFET H2 (see FIG. 1) described in the first embodiment, the MONOS memory Mn (see FIG. 15) of the present embodiment has a higher breakdown voltage in the drain region than in the source region. Since it is a required element and has the extension regions 31a and 32 having different widths on the upper surface of the semiconductor substrate SB, the same effect as in the first embodiment can be obtained for the MONOS memory Mn. In the first embodiment, the width of the extension region on the source side of some high-breakdown-voltage MISFETs has been described. However, the width of the MONOS memory is narrower than that on the drain side as in this embodiment, and the drain side An extension region having a lower resistance than that can be formed on the source side.

  Accordingly, the current flowing between the source and the drain of the MONOS memory Mn (that is, the read current of the MONOS memory Mn) can be increased, not limited to the second high breakdown voltage MISFET H2 shown in FIG. In addition, the operation speed of the semiconductor device can be increased.

  Further, the MONOS memory Mn has a longer extension region 35 as in the first high breakdown voltage MISFET H1 by making the width of the extension region 31a on the diffusion layer 41a side smaller than the width of the extension region 32 on the diffusion layer 42 side. Compared to the formation, the contact plug 13 for supplying a potential to the diffusion layer 41a can be disposed closer to the gate electrode 4a. That is, the semiconductor device can be miniaturized in the gate length direction of the gate electrode 4a by narrowing the width of the extension region 31a of the second high breakdown voltage MISFET H2 on the upper surface of the semiconductor substrate SB.

  The write and erase operations of the MONOS memory according to the present embodiment are the same as those in the first embodiment. In other words, the present embodiment has the same effects as those of the first embodiment and can reduce the size of each MONOS memory.

  Further, as described below, it is particularly useful when the write operation of each MONOS memory is performed by hot electron injection.

  As described above, in the writing method in which electrons are injected from the entire surface of the channel into the charge storage layer of the MONOS memory described with reference to FIGS. 17A and 17B, some non-selected cells (FIG. 17A ) And (b) corresponding to the memory cell M4), a high breakdown voltage is required for both the source region and the drain region. On the other hand, in the writing method in which hot electrons are injected into the charge storage layer of the MONOS memory in the vicinity of the drain described with reference to FIGS. 18A and 18B, some non-selected cells (FIG. 17A ) And (b) corresponding to the memory cell M3), a high breakdown voltage is required only for the drain region. Further, in the erase operation described with reference to FIGS. 16A and 16B, in each memory cell, there is almost no potential difference between the source / drain region and the well, and each source / drain region is Should have a relatively low breakdown voltage.

  That is, when the MONOS memory is operated using the erase operation described with reference to FIGS. 16A and 16B and the write operation described with reference to FIGS. The drain region of the memory needs to have a high breakdown voltage with respect to the well and the gate electrode, but the source region of each MONOS memory does not need to have a high breakdown voltage like the drain region.

  Therefore, in the MONOS memory in which there is no problem even if the breakdown voltage of the source region is lower than the breakdown voltage of the drain region, the widths of the sidewalls and extension regions on the source region side are set to be the same as the MONOS memory Mn shown in FIG. A structure shorter than the width of the side wall and the extension region on the region side can be applied. Thereby, as described above, by reducing the resistance value of the extension region on the source side, the current between the source and the drain can be increased, the operation speed of the semiconductor device can be improved, and the semiconductor device can be miniaturized. .

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 19 to 22 are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the second embodiment. The manufacturing method of the semiconductor device of the present embodiment is almost the same as that of the first embodiment. However, a relatively narrow sidewall is formed on one of the sidewalls of the gate electrode of the MONOS memory, and the width is formed below the sidewall. The manufacturing method is different from that of the first embodiment in that a narrow extension region is formed.

  First, since the first manufacturing process is performed in the same manner up to FIG. 6 of the first embodiment, detailed description is omitted. That is, a plurality of gate electrodes are formed on a semiconductor substrate via an insulating film, an extension region is formed on the upper surface of the semiconductor substrate on both sides of each gate electrode, and then a plurality of insulating films are deposited on the semiconductor substrate.

  Next, as shown in FIG. 19, after obtaining the structure of FIG. 6, a photoresist film PR is formed on the semiconductor substrate SB. At this time, unlike the first embodiment, one of the insulating films 7 on both sides of the gate electrode 4a in the MONOS memory formation region 1A is exposed, and the other insulating film 7 is covered with the photoresist film PR. Here, an extension region 31a is formed on one of the upper surfaces of the semiconductor substrate SB on both sides of the gate electrode 4a of the MONOS memory formation region 1A, and an extension region 32 is formed on the other. Similar to the extension region 31 shown in FIG. 6, the extension region 31a is a semiconductor region into which a low-concentration n-type impurity (for example, P (phosphorus)) is introduced.

  Next, as shown in FIG. 20, the same steps as those described with reference to FIGS. 8 and 9 are performed to form sidewalls on the side walls of the gate electrodes 4a to 4d. That is, after the insulating film 7 is removed using the photoresist film PR shown in FIG. 19 as a mask, the photoresist film PR is removed, and then the insulating films 7, 6 and 6a are etched by dry etching, thereby forming each gate. Sidewalls made of insulating films 6a, 6 and 7 are formed on the side walls on both sides of the electrode.

  At this time, since one insulating film 7 on the side wall of the gate electrode 4a is removed, in the subsequent step of etching the insulating films 7, 6 and 6a, one side wall of the gate electrode 4a is formed on the one side wall from the insulating films 6a and 6a. The second side wall 6n is formed, and the other side wall is an insulating film made of the insulating films 6a, 6 and 7, and the first side wall 6w wider than the second side wall 6n is formed. .

  Next, as shown in FIG. 21, n-type impurities (for example, P (phosphorus)) are ion-implanted into the upper surface of the semiconductor substrate SB at a relatively high concentration, as in the process described with reference to FIG. The diffusion layers 41a and 42 to 48 are formed on the upper surface of the semiconductor substrate SB. Here, the diffusion layer 41a is formed in a part of the upper surface of the extension region 31a with a junction depth shallower than that of the extension region 31a, and the other diffusion layers 42 to 48 are formed in the same manner as in the first embodiment.

  Since the subsequent steps are the same as those in the first embodiment, detailed description thereof is omitted. That is, as shown in FIG. 22, after the silicide layers 9 are respectively formed on the upper surfaces of the diffusion layers 41a, 42 to 48 and the gate electrodes 4a to 4d, the stopper insulating film 10 and the interlayer insulating film 11 are sequentially formed on the semiconductor substrate SB. Form. Subsequently, after forming a contact hole 12 reaching the silicide layer 9 from the upper surface of the interlayer insulating film 11, a contact plug 13 is embedded in the contact hole 12, and the upper surface of the interlayer insulating film 11 is exposed by CMP. Subsequently, a stopper insulating film 14 and an interlayer insulating film 15 are sequentially formed on the interlayer insulating film 11 and the contact plug 13, and then the stopper insulating film 14 and the interlayer insulating film on the contact plug 13 by a known damascene method. By forming the metal wiring 17 in the wiring groove 16 formed in 15, the semiconductor device of the present embodiment is completed.

  In the present embodiment, similar to the formation process of the second high breakdown voltage MISFET H2 shown in FIG. 1 of the first embodiment, in the process shown in FIG. 19, the insulating films on both sides of the gate electrode 4a in the MONOS memory formation region 1A. 7, one insulating film 7 is covered with the photoresist film PR, and the other insulating film 7 is exposed from the photoresist film PR, so that it is exposed from the photoresist film PR by the process shown in FIG. 20. Only the insulating film 7 is removed. Therefore, after that, when the insulating films 6a, 6 and 7 are etched to form the first sidewall 6w and the second sidewall 6n, the first sidewall 6w having a different width between a region where the insulating film 7 is not present and a region where the insulating film 7 is not present. The second sidewall 6n can be made separately.

  The widths of the extension regions 31a and 32 to 38 shown in FIG. 15 on the upper surface of the semiconductor substrate SB are defined by the width of the upper sidewalls of the extension regions 31a and 32 to 38. Therefore, by forming the second sidewall 6n having a narrow width and the first sidewall 6w having a width wider than the second sidewall 6n, the semiconductor substrate SB on both sides of the gate electrode 4a constituting the MONOS memory Mn is formed. Extension regions 31a and 32 having different widths can be formed on the upper surface, respectively.

  Accordingly, as described above, the source-drain width of the source-side extension region 31a is narrower than that of the drain-side extension region 32, thereby reducing the resistance value of the extension region 31a. Therefore, it is possible to increase the current between the source and the drain and improve the operation speed of the semiconductor device, and it is possible to miniaturize the semiconductor device by reducing the width of the extension region 31a.

  In this embodiment, a semiconductor device having an n-channel MISFET and a MONOS memory is described as an example. However, the present invention may be applied to a p-channel MISFET and a MONOS memory. The present invention may be applied to a semiconductor device having an n-channel type MISFET and a MONOS memory and a p-channel type MISFET and a MONOS memory.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is widely used for semiconductor devices having a plurality of MISFETs.

1 element isolation layer 1A MONOS memory formation region 1B low breakdown voltage MISFET formation region 1C first high breakdown voltage MISFET formation region 1D second high breakdown voltage MISFET formation region 2a to 2d p well 3 ONO film 3a ONO film 3b to 3d gate insulating film 3e thin film Insulating film 3f Thick film insulating film 3g Bottom oxide film 3h Charge storage layer 3i Top oxide films 4a to 4d Gate electrode 4e Polysilicon film 4f Polysilicon film 6 Insulating film 6a Insulating film 6n Second sidewall 6w First sidewall 7 Insulating Film 9 Silicide layer 10 Stopper insulating film 11 Interlayer insulating film 12 Contact hole 13 Contact plug 14 Stopper insulating film 15 Interlayer insulating film 16 Wiring groove 17 Metal wiring 31 to 38 Extension region 31a Extension region 31b to 38b Extension region 41 to 48 Expansion Layer 41a diffusion layers D1 drain D2 drain G1 gate G2 gate H1 first high voltage MISFET
H2 Second high voltage MISFET
Ln Low voltage MISFET
M1-M4 memory cell Mn MONOS memory OX silicon oxide film PR photoresist film S1 source

Claims (13)

A first field effect transistor formed in a first region of the main surface of the semiconductor substrate and a second electric field formed in a second region of the main surface of the semiconductor substrate and operating at a higher voltage than the first field effect transistor. A semiconductor device having an effect transistor,
The first field effect transistor is:
A first gate electrode formed on the semiconductor substrate via a first gate insulating film;
First sidewalls respectively formed on sidewalls on both sides of the first gate electrode;
A first extension region formed on an upper surface of the semiconductor substrate below the first sidewall;
A first diffusion layer electrically connected to the first extension region, formed on an upper surface of the semiconductor substrate, and having a higher impurity concentration than the first extension region;
Have
The second field effect transistor is:
A second gate electrode formed on the semiconductor substrate via a second gate insulating film;
The second gate electrode is formed on one of the sidewalls on both sides of the second gate electrode in the same layer as the first sidewall and has the same width as the width of the first sidewall in the gate length direction of the first gate electrode. Side walls,
A third sidewall formed on the other side wall on both sides of the second gate electrode and having a width in the gate length direction larger than the second sidewall;
A second extension region formed on the upper surface of the semiconductor substrate below the second sidewall;
A third extension region formed on an upper surface of the semiconductor substrate below the third sidewall and having a width in the gate length direction larger than the second extension region;
A second diffusion layer formed on the upper surface of the semiconductor substrate, electrically connected to the second extension region, and having a higher impurity concentration than the second extension region;
A third diffusion layer formed on the upper surface of the semiconductor substrate, electrically connected to the third extension region, and having an impurity concentration higher than that of the third extension region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the n-channel type second field effect transistor and the p-channel type second field effect transistor are formed on the semiconductor substrate. A third field effect transistor that operates at a higher voltage than the first field effect transistor and has a different use from the second field effect transistor is formed in the third region on the semiconductor substrate,
The third field effect transistor is:
A third gate electrode formed on the semiconductor substrate via a third gate insulating film;
A fourth sidewall formed on sidewalls on both sides of the third gate electrode and having the same width in the gate length direction as the third sidewall;
A fourth extension region formed on the upper surface of the semiconductor substrate below the fourth sidewall;
A fourth diffusion layer formed on the upper surface of the semiconductor substrate, electrically connected to the fourth extension region, and having a higher impurity concentration than the fourth extension region;
The semiconductor device according to claim 1, comprising: The first sidewall has a laminated structure in which a first silicon oxide film and a silicon nitride film are formed in order from the semiconductor substrate side and the first gate electrode side,
The second sidewall has a laminated structure in which the first silicon oxide film and the silicon nitride film are formed in order from the semiconductor substrate side and the second gate electrode side,
The third sidewall has a laminated structure in which the first silicon oxide film, the silicon nitride film, and the second silicon oxide film are sequentially formed from the semiconductor substrate side and the third gate electrode side. Item 14. A semiconductor device according to Item 1.   The semiconductor device according to claim 1, wherein the third sidewall has a larger number of insulating films stacked than the first sidewall and the second sidewall. The third field effect transistor is a MONOS type nonvolatile memory cell;
4. The semiconductor device according to claim 3, wherein the third gate insulating film includes at least a potential barrier film and a charge storage layer formed in order from the semiconductor substrate side. The second field effect transistor is a MONOS type nonvolatile memory cell;
6. The semiconductor device according to claim 5, wherein the second gate insulating film includes at least a potential barrier film and a charge storage layer formed in order from the semiconductor substrate side.   The semiconductor device according to claim 1, wherein the second diffusion layer functions as a source region of the second field effect transistor. A first field effect transistor formed in the first region of the main surface of the semiconductor substrate and a second field effect formed in the second region of the main surface of the semiconductor substrate and operating at a higher voltage than the first field effect transistor. A method of manufacturing a semiconductor device having a transistor,
(A) forming a first insulating film on the semiconductor substrate in the first region;
(B) forming a second insulating film thicker than the first insulating film on the semiconductor substrate in the second region;
(C) forming a conductor film on the first insulating film and the second insulating film;
(D) Processing the conductor film, the first insulating film, and the second insulating film, and forming the first gate electrode and the second gate electrode made of the conductor film in the first region and the second region, respectively. Forming, and
(E) after the step (d), introducing impurities into the upper surface of the semiconductor substrate in the first region, and forming a first extension region on the upper surface of the semiconductor substrate on both sides of the first gate electrode; ,
(F) After the step (d), introducing impurities into the upper surface of the semiconductor substrate in the second region, and forming a second extension region on the upper surface of the semiconductor substrate on both sides of the second gate electrode; ,
(G) After the step (e) and the step (f), a first sidewall is formed on one of the sidewalls on both sides of the first gate electrode and the sidewalls on both sides of the second gate electrode. Forming a second sidewall having a width in the gate length direction of the second gate electrode larger than the first sidewall on the other sidewall of the second gate electrode;
(H) After the step (g), an impurity having the same conductivity type as that of the first extension region is introduced into the upper surface of the semiconductor substrate in the first region at a concentration higher than that of the first extension region. Forming a layer;
(I) After the step (g), an impurity having the same conductivity type as that of the second extension region is introduced into the upper surface of the semiconductor substrate in the second region at a higher concentration than that of the second extension region. The first field effect transistor having the first gate insulating film, the first gate electrode, the first sidewall, the first extension region, and the first diffusion layer in the first region by forming a layer Form the
The second region includes the second insulating film, the second gate electrode, the first sidewall, the second sidewall, the first extension region, the second extension region, and the second diffusion layer. Forming a two field effect transistor;
Have
The second extension region under the second sidewall has a shorter width in the gate length direction on the upper surface of the semiconductor substrate than the first extension region under the first extension region. Manufacturing method. A method of manufacturing a semiconductor device having a third field effect transistor operating in a third region on the semiconductor substrate at a voltage higher than that of the first field effect transistor and having a use different from that of the second field effect transistor,
In the step (b), the second insulating film is formed in the third region,
In the step (d), a third gate electrode made of the conductor film is formed in the third region,
After the step (d) and before the step (g), an impurity is introduced into the upper surface of the semiconductor substrate in the third region, and the upper surface of the semiconductor substrate on both sides of the third gate electrode is 3 extension regions are formed,
In the step (g), the second sidewall is formed on the sidewalls on both sides of the third gate electrode,
After the step (g), an impurity having the same conductivity type as that of the third extension region is introduced into the upper surface of the semiconductor substrate in the third region at a higher concentration than the third extension region to form a third diffusion layer. Thus, the third field effect transistor having the second insulating film, the third gate electrode, the second sidewall, the third extension region, and the third diffusion layer is formed in the third region. A method for manufacturing a semiconductor device according to claim 9. The step (g)
(G1) forming a first silicon oxide film over the entire main surface of the semiconductor substrate;
(G2) forming a silicon nitride film on the first silicon oxide film;
(G3) forming a second silicon oxide film on the silicon nitride film;
(G4) Processing the second silicon oxide film, and forming the sidewall shape on the side walls on both sides of the first gate electrode and the second gate electrode via the first silicon oxide film and the silicon nitride film, respectively. Leaving the second silicon oxide film;
(G5) After the step (g5), a step of covering the second silicon oxide film on one of the side walls on both sides of the second gate electrode with a photoresist film;
(G6) using the photoresist film as a mask, removing the second silicon oxide film in the first region and one of the second silicon oxide films on both side walls of the second gate electrode;
(G7) removing the photoresist film;
(G8) The silicon nitride film and the first silicon oxide film are processed by anisotropic etching, and the first silicon oxide film is formed on one of the side walls on both sides of the first gate electrode and the side walls on both sides of the second gate electrode. Forming the first sidewall comprising a film and the silicon nitride film, and in the same step, forming the first silicon oxide film, the silicon nitride film, and the second silicon oxide on the other sidewall of the second gate electrode. Forming the second sidewall made of a film and having a width in the gate length direction of the second gate electrode larger than the first sidewall;
The method of manufacturing a semiconductor device according to claim 9, wherein: A method of manufacturing a semiconductor device having a MONOS type nonvolatile memory cell in a fourth region of a main surface of the semiconductor substrate,
(C1) After the step (c), removing the conductive film and the first insulating film in the fourth region;
(C2) After the step (c1), a step of sequentially forming a potential barrier film, a charge storage layer, and another conductive film on the entire main surface of the semiconductor substrate;
(C3) Before the step (d), the other conductive film, the charge storage layer, and the potential barrier film are processed to expose an upper surface of the conductive film, and the other conductive film is formed in the fourth region. Forming a fourth gate electrode comprising:
Further comprising
After the step (d) and before the step (g), impurities are introduced into the upper surface of the semiconductor substrate in the fourth region, and the upper surface of the semiconductor substrate on both sides of the fourth gate electrode is introduced into the upper surface of the semiconductor substrate. 4 extension regions are formed,
In the step (g), the second sidewall is formed on the sidewalls on both sides of the fourth gate electrode,
After the step (g), an impurity having the same conductivity type as that of the fourth extension region is introduced into the upper surface of the semiconductor substrate in the fourth region at a higher concentration than the fourth extension region to form a fourth diffusion layer. Thus, the MONOS-type non-volatile having the potential barrier film, the charge storage layer, the fourth gate electrode, the second sidewall, the fourth extension region, and the fourth diffusion layer in the fourth region 10. The method of manufacturing a semiconductor device according to claim 9, wherein a memory cell is formed. A method of manufacturing a semiconductor device having a MONOS type nonvolatile memory cell in a fourth region of a main surface of the semiconductor substrate,
(D1) After the step (c), removing the conductive film and the first insulating film in the fourth region;
(D2) After the step (d1), a step of sequentially forming a potential barrier film, a charge storage layer, and another conductive film on the entire main surface of the semiconductor substrate;
(D3) Before the step (d), the other conductive film, the charge storage layer, and the potential barrier film are processed to expose an upper surface of the conductive film, and the other conductive film is formed in the fourth region. Forming a fourth gate electrode comprising:
Further comprising
After the step (d) and before the step (g), impurities are introduced into the upper surface of the semiconductor substrate in the fourth region, and the upper surface of the semiconductor substrate on both sides of the fourth gate electrode is introduced into the upper surface of the semiconductor substrate. 4 extension regions are formed,
In the step (g), the first sidewall is formed on one of the sidewalls on both sides of the fourth gate electrode, and in the step, the second sidewall is formed on the other sidewall of the fourth gate electrode. And
After the step (g), an impurity having the same conductivity type as that of the fourth extension region is introduced into the upper surface of the semiconductor substrate in the fourth region at a higher concentration than the fourth extension region to form a fourth diffusion layer. Thus, the MONOS-type non-volatile having the potential barrier film, the charge storage layer, the fourth gate electrode, the second sidewall, the fourth extension region, and the fourth diffusion layer in the fourth region 10. The method of manufacturing a semiconductor device according to claim 9, wherein a memory cell is formed.

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