CN1291481C - Method for manufacturing imbedded non-volatile memory with sacrificed layer - Google Patents
Method for manufacturing imbedded non-volatile memory with sacrificed layer Download PDFInfo
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- CN1291481C CN1291481C CN03153080.XA CN03153080A CN1291481C CN 1291481 C CN1291481 C CN 1291481C CN 03153080 A CN03153080 A CN 03153080A CN 1291481 C CN1291481 C CN 1291481C
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Abstract
The present invention discloses a method which uses a protecting sacrificial layer for manufacturing high-density non-volatile memories, such as a mask ROM or an SONOS memory, etc. The high-density non-volatile memories and advanced peripheral logic components are combined and formed on a single chip. The manufacturing method comprises the following procedures: a silicon nitride sacrificial layer is used for covering a grid dielectric layer; a mask is used for defining a line structure pattern on the silicon nitride sacrificial layer in the step of bit line injection; dielectric material is deposited to fill the gap in the line structure; leveling operation is carried out; the silicon nitride sacrificial layer is removed and a polycrystalline silicon layer is covered; a character line is defined in an array area, and a transistor grid structure is defined in a non-array area; a low doping drain (LDD), silicide and other logic circuits are used.
Description
Technical field
The present invention relates to a kind of manufacture method, relate in particular to the manufacture method of the in-line memory on a kind of suitable complicated integrated circuit with non-volatility memorizer of little critical size.
Background technology
Along with the development of ic manufacturing technology, the size of components that is positioned on the integrated circuit phases down, and the degree of integration of functional block also improves gradually on the one chip.Therefore, design many embedded non-volatile memory chips that contain the logic function assembly, for example Memory Controller (memory controllers), general processor (general-purpose processors), input/output interface logic (input/outputinterface logic), special logic (dedicated logic), digital signal processor (digital signalprocessors) and various chip with other functional unit.
It is to be solved that present undersized complicated integrated circuit still has some problems to have in design and manufacturing.For example, when the width of diffusion conductor more hour, the resistance of this conductor is big more, therefore, for head it off, use existing autoregistration metal silicide (salicide) technology usually, that is on this diffusion surface of conductors, form a high conductive layer to reduce the resistance value of this diffusion conductor.For example, utilize silicide (silicide) in the autoregistration deposition step of autoregistration metal silicide technology, to form a film in this diffusion surface of conductors as titanium silicide (titanium silicide) etc.Yet to form the technology of high density memory cells also incompatible with some when using autoregistration metal silicide technology.For example, in the formation clearance wall step of autoregistration metal silicide technology, this clearance wall is used as mask and uses, and this process that forms clearance wall comprises etching step, and using plasma carries out the dry ecthing mode of thin film corrosive usually.Yet this etchback step may be destroyed the surface of described silica substrate, causes this substrate surface infringement to cause electric leakage to take place.This leaky can cause the soft electricity collapse phenomenon of memory, especially influences especially severe for highdensity memory array.
Therefore in addition, assembly is more little, and the length of channel will shorten thereupon, and transistorized service speed will be accelerated, and various because of the passage length problem of being derived that diminishes just can take place, and is referred to as short-channel effect (shortchannel effect).But, oxidation and high-temperature heat flux method are injected when dopant (dopants) causes diffusion and can not be shortened transistorized passage effectively now, and this phenomenon is called heat and strengthens diffusion phenomena (thermally enhanced diffusion) and oxidation enhancing phenomenon (oxidation enhanced diffusion).
Summary of the invention
Given this, the technical problem to be solved in the present invention provides a kind of manufacture method that can be fit to make high density non-volatility memorizer and senior peripheral logical circuit, utilize this manufacture method can reduce or avoid because of making the problems that little critical size assembly is derived, destroy the soft electric breakdown effect that causes and the problems such as high resistance of narrow diffusion conductor as short-channel effect, because of oxidation.
According to the present invention, the measure that solve the technical problem is to use a protection sacrifice layer to make the manufacture method as mask ROM (mask ROM) or SONOS memory high density non-volatility memorizers such as (SONOS memory).These high density non-volatility memorizers and senior peripheral logic assembly (advanced peripheral logic) integration is formed on the one chip.Execution mode among the present invention provides a kind of method of making an integrated circuit on a substrate, this integrated circuit comprises that the non-volatility memorizer and in an array zone that is arranged on the substrate is positioned at other circuit of a non-array region on this substrate, and this method of making integrated circuit package comprises:
On the array region of described substrate and non-array region, form a gate dielectric;
On the array region and non-array region of described substrate, cover described gate dielectric with the sacrifice layer of a tool protectiveness, and the material of this sacrifice layer is as comprising a silicon nitride (silicon nitride, Si
3N
4);
On described array region, comply with bit line direction formation (patterning) at least one line pattern and the described sacrifice layer of etching to form at least one line structure;
Between described line structure, penetrate described gate dielectric one dopant (dopants) is injected described substrate;
In depositing one first dielectric material between the described line structure to fill at least one gap between described line structure;
Described array region and non-array region are carried out smooth processing to a certain height, and this certain height exposes described line structure and is filled in first dielectric material in the described gap of this line structure;
Remove the sacrifice layer on the line structure that is positioned on described non-array region and the array region, stay described gate dielectric and be filled in the remaining part of first dielectric material in the gap between described line structure;
On described part of grid pole dielectric layer and be filled on first dielectric material in the gap between this line structure and cover a polysilicon layer;
In described array region, form at least one character line pattern, and according to the described polysilicon layer of this pattern etching, make in described array region, to define at least one character line and in non-array region, define at least one transistor grid structure;
In described non-array region, inject a dopant, to form at least one drain electrode and source region;
In the drain electrode of described non-array region and source region, form a self-aligned silicide;
On described array region and non-array region, cover one second dielectric materials layer; And
On described second dielectric materials layer, form and define metal level.
Wherein, generally speaking, in various execution modes, a thickness that comprises the sacrifice layer of silicon nitride be about 300 dusts (angstroms, ) about, or its thickness range is between 100 dust to 1000 dusts.And the thickness of this polysilicon (polysilicon) of deposition layer is about 1500 dusts, or its thickness range is between 1300 dust to 1600 dusts.
(lightly doped drain, LDD) technology is to improve performance of transistors, particularly at peripheral circuit to the present invention includes the existing low-doped drain of application.In using the low-doped drain technology, injecting a dopant at non-array region comprises with the method that forms at least one drain electrode and source region: aim at this transistor grid structure, inject one first dopant, form at least one clearance wall and aim at this clearance wall and inject steps such as one second dopant on this transistor grid structure.The clearance wall purpose that forms with silicon nitride is the selectivity of eat-backing in order to promote.Certainly, also can adopt other to have the material that to promote etching selectivity and form clearance wall to be used at autoregistration metal silicide technology (self aligned silicide, salicide) use as mask in the step, thereby can reduce generation because of the destroyed leaky that causes in silica substrate surface.
Among the present invention, deposit one first dielectric material in comprising use chemical vapour deposition technique (chemicalvapor deposition to carry out smooth (planarization) processing after filling the gap between described line structure again on the gate dielectric, CVD), plasma reinforced chemical vapour deposition method (plasma enhanced CVD) or the chemical vapour deposition technique of other any low temperature deposit, and the temperature of wall of reactor is preferable to be lower than 650 ℃.
In carrying out smooth processing procedure, (chemical mechanicalpolishing CMP) can further reduce the problem that Yin Gaowen caused in manufacture process to the cmp of use low temperature.
Described method is made on the mask ROM except can be applicable to, and also can be applicable to one and comprises on the embedded non-volatile memory array that can wipe with programmable memory cell such as SONOS.This SONOS memory comprises a combined type gate dielectric, and it is an ONO layer structure.This composite bed comprises that the silicon nitride dielectric layer with trapped electron effect and that a silicon dioxide dielectric layers, that is positioned at bottom is positioned at the intermediate layer is positioned at the silicon dioxide dielectric layers on upper strata.
Forming gate dielectric, injecting dopant with after separating steps such as bit line and character line, utilize the electronics injection mode to form the embedding diffusion layer (buried diffusion layers) of source electrode and drain electrode again, this mode can reduce heat and strengthen diffusion phenomena (thermally enhanced diffusion) and oxidation-enhanced diffusion phenomenon (oxidation enhanced diffusion).This two phenomenon may cause short-channel effect.Can avoid between embedding diffusion layer and character line, taking place soft electricity collapse phenomenon carrying out low temperature depositing and cmp from a thick dielectric layer between the character line.Polysilicon layer is to be used for forming a plurality of transistor grid structures for peripheral circuit.Form the silicon nitride gap wall purpose and be in order to promote etched selectivity, to use, prevent that gate dielectric is destroyed and reduce owing to the destroyed problems such as leaky that cause of embedding diffusion zone dielectric material as mask.
Description of drawings
For described purpose of the present invention, feature and advantage can be become apparent, a preferred implementation cited below particularly also elaborates in conjunction with the accompanying drawings.In the accompanying drawing:
The manufacture method flow chart of Figure 1A～Figure 1B for drawing according to embodiment of the present invention;
The complicated integrated circuit structure diagram with embedded mask memory of Fig. 2～Figure 10 for being drawn according to Figure 1A～Figure 1B correlation step;
Figure 11 is the embedded non-volatile memory structure chart with SONOS memory cell that manufacturing technology illustrated of application drawing 2～Figure 10.
The drawing reference numeral explanation
10,11,12,13,14,15,16,17,18,19,20,21,22,23: the step square
100 substrates
110 array regions
111 non-array regions
112,113 dielectric regimes
114,117 p type wellses
115 N types also
116 deep N-wells
118,119 gate dielectrics
125 sacrifice layers
126,127 line structures
128,129 embedding diffusion position lines
130 polysilicon layers
131 gaps
132 gap areas
134 character lines
140,141 transistor grid structures
145,146,147,148 diffusion zones
149 metal silicide layers
150,151,152 clearance walls
160 dielectric layers
161 contact holes
162 metal levels of composition
170,171 oxide lines
180,182 dielectric layers
181 trapped electron layers
Embodiment
It is as follows that detailed methods of fabrication that the present invention is disclosed and practical application will be distinguished accompanying drawings.The manufacture method flow chart of Figure 1A～Figure 1B for drawing according to embodiment of the present invention.The structure chart of Fig. 2～Figure 10 illustrates the correlation step of Figure 1A～Figure 1B.And Figure 11 uses the profile with embedded non-volatile memory structure of SONOS memory cell that the present invention drew.
Please refer to Figure 1A～Figure 1B, each step will be arranged explanation manufacture method of the present invention according to digital size order with step square 10 to step square 23.At first, as described in step square 10, on substrate 100, separate substrate 100 and define an array zone 110 and one non-array region 111 with a dielectric regime 112.Shown in the 2nd figure, dielectric regime 112 be adopt the localized oxidation of silicon method (local oxidation of silicon, LOCOS) or other prior art in irrigation canals and ditches, fill monoxide or other dielectric medium and be formed on the substrate 100.And in non-array region 111, adopt CMOS (Complementary Metal Oxide Semiconductor) (the complementary metal-oxide semiconductor of existing application on logical circuit, CMOS) technology is separated these non-array regions 111 with the N channel region that defines a N channel element and the P channel region of a P channel element with a dielectric regime 113, wherein, p type wells 114 is formed at the N channel region and N type well 115 is formed at the P channel region.In the present embodiment, array region 110 comprises a deep N-well 116, and a p type wells 117 is formed on this deep N-well 116.So, in p type wells 117, form a N channel memory assembly.In some embodiments, can in array region 110, use described many well construction combinations to reach the insulation purpose.For example, the forming process of degeneration well (retrograde well) can be applied in and produce a deep-well structure and make starting voltage (V
t) can be injected in memory cell region.The process of this generation deep-well structure comprises the process that forms two degeneration wells.Generally speaking, the process of degeneration well formation comprises: inject the identical mask of a well → anti-break-through (anti-punch through) injection → use and inject starting voltage.
In addition, according to the mode of described formation degeneration well process, when forming N type well 116 and p type wells 117, use two mask layers.For making N type semiconductor (NMOS) assembly, its typical method for implanting is as follows: use the voltage of about 150,000～250,000 KeV when injecting well, the about 1013dose/cm of concentration
2Boron (B); When anti-break-through is injected, use the voltage of about 50,000～80,000 KeV, the about 1012dose/cm of concentration
2Boron (B); When injecting starting voltage, use the voltage of about 50,000～80,000 KeV, the about 1012dose/cm of concentration
2Boron difluoride (BF
2).And for making P type semiconductor (PMOS) assembly, its typical method for implanting is as follows: use the voltage of about 550,000～600,000 KeV, the about 1013dose/cm of concentration when injecting well
2Phosphorus (P); When anti-break-through is injected, use the voltage of about 250,000～300,000 KeV, the about 2 * 1012dose/cm of concentration
2Phosphorus (P); When injecting starting voltage, use the voltage of about 100,000～120,000 KeV, the about 2 * 1012dose/cm of concentration
2Phosphorus (P).In some embodiments, in the described array region 110 combination of many well constructions as the usefulness of isolating with insulation.
In the narration of step square 11, on described array region 110 and non-array region 111, form gate dielectric 118 and 119 respectively, as shown in Figure 2.Gate dielectric 118 and 119 can be formed by identical step or use the different steps that forms in order to distinguish the gate dielectric on zones of different.For example, have in the execution mode of SONOS memory one, described gate dielectric 118 is a combined type multi-ply construction, and gate dielectric 119 still is individual layer silicon dioxide (silicon dioxide) layer structure, as shown in figure 11.
After forming gate dielectric 118 and 119, described in step square 12, deposition one has the silicon nitride of protectiveness, and (silicon nitride, Si3N4) layer is covered on gate dielectric 118 and 119, is called sacrifice layer 125, as shown in Figure 3.In the present embodiment, between 1000 dusts, generally speaking, the thickness of silicon nitride sacrifice layer 125 is about the 300 Izod right sides to sacrifice layer 125 thickness about 100 dusts (angstroms, )), or its thickness range is 200 dust to 450 dusts.
In step square 13, till forming at least one line pattern and etch sacrificial layer 125 to array region 110 according to a bit line direction on the array region 110 and exposing gate dielectric 118, to form line structure 126 and 127.At this, sacrifice layer 125 carries out etching according to following step: form the first photoresistance pattern, stay the line structure that comprises residual sacrifice layer.Next step please refer to Fig. 4, and this figure is the profile according to the array region 110 shown in the parallel bit lines direction.As described in step square 14, mask when utilizing line structure 126 and 127 as injection, outside line structure 126 and 127, penetrate expose gate dielectric 118 the zone insert dopant respectively (buried diffusion, BD) bit line 128 and 129 be in array region 110 as embedding diffusion.At this, this dopant comprises that one contains the package that a N type BD and a back injection P type BD inject in an elder generation.Wherein, this N type BD is the voltage with 30,000～60,000 KeV, about 2 * 1015～3.5 * 1015dose/cm of implantation concentration
2Arsenic (arsenic, As), and this P type BD is the voltage with 10,000 5000～40,000 KeV, about 3 * 1013～5 * 1013dose/cm of implantation concentration
2Boron (B).In these injection process, the certain chip that employed voltage and material concentration all can be produced according to desire or the structure of special component or operation are adjusted and are changed.
Because embedding diffusion position line 128 and 129 is formed on after the line structure 126 and 127 formation with protectiveness, can not produce the oxidation-enhanced diffusion effect so form the process of gate dielectric 118.
Please refer to Fig. 5, this figure is the profile according to the shown array region 110 of parallel bit lines direction.As described in step square 15, between this line structure 126 and 127, earlier deposition one dielectric material is in carrying out smooth processing (planarization) again behind the gap 131 with interstitial wire structure 126 and 127 on the gate dielectric 118.This deposition process comprises use chemical vapour deposition technique (chemical vapor deposition in one embodiment, CVD) or plasma reinforced chemical vapour deposition method (plasmaenhanced CVD) deposition one contain the dielectric material of silicon dioxide (silicon dioxide), and in deposition process, the wall of reactor need maintain the situation of lower temperature as much as possible, for example, the temperature maintenance of wall of reactor is being lower than 650 ℃, and dielectric material comprises silicon dioxide.Again for example, described dielectric material comprise tetraethyl orthosilicate salt (tetraethylorthosilicate, TEOS) with oxygen (O
2) mixture and the temperature maintenance of this wall of reactor be lower than 630 ℃.Other mentioned deposition process also can take this mode to control the wall of reactor temperature in embodiment of the present invention, makes it be lower than 650 ℃.In planarization step, and the cmp of use low temperature (chemical mechanical polishing, CMP) good than the high-temperature heat flux method that relates to a reflux.Deposit a dielectric material in gap 131 after, use reverse memory cell grid step (reverse cell gate process) to promote the uniformity of cmp.This reverse memory cell grid step comprise form the photoresistance pattern, eat-back, remove step such as photoresistance pattern so as before to grind earlier the reduction pattern density to the influence of dielectric material.As shown in Figure 5, oxide line 170 and 171 is filled in the gap 131 and between the silicon nitride line structure, makes substrate 100 have a smooth upper surface.
As described in step square 16, behind the smooth treatment step, remove and be arranged in the sacrifice layer 125 on the non-array region 111 and be positioned at the sacrifice layer 126 and 127 of array region 110, stay this gate dielectric 118 and be filled in line structure 126 and the remaining part in 127 gap 131 as line structure.Please refer to Fig. 6, as described in step square 17, deposit a polysilicon (polysilicon) layer 130 on the gate dielectric 118 of array region 110 and non-array region 111 and on the remaining part in filling gap 131.In addition, the thickness of polysilicon layer 130 is about 1500 dusts, or its thickness range is between 1300 dust to 1600 dusts.
As described in step square 18, after deposit spathic silicon layer 130, in array region 110, form the character line pattern and make and in array region 110, define character line 134 according to this pattern etching polysilicon layer 130; And in non-array region 111, define transistor grid structure 140 and 141.
Please refer to Fig. 8, this figure is the schematic diagram of overlooking from substrate 110 upper surfaces among Fig. 7.The embedding diffusion position line 128 and 129 that is positioned at lower floor is arranged according to B-B ' direction, and arranges with 134 one-tenth square crossings of the character line that is positioned at the upper strata according to A-A ' direction.Bit line 128 and 129 and character line 134 between form the gap area 132 that injects for dielectric material in twos in the middle of the gap.
In low-doped drain (lightly doped drain, LDD) oxide layers in the non-array region 111 of elder generation's two degree oxidations before the step.Please refer to Fig. 9, this figure is a parallel character line 134 that is along the profile shown in the direction of A-A ' among Fig. 8, as described in step square 19, in non-array region 111, aim at transistor grid structure 140, inject one first dopant to form drain electrode and source region, as for transistor grid structure 140, form diffusion zone 145 and 146.Afterwards, as described in step square 20, deposit a silicon nitride layer and in addition form two silicon nitride gap walls after the etching of anisotropy (anisotropical),, form clearance wall 150 and 151 as for transistor grid structure 140.The actual implementation method that deposits this silicon nitride layer is for example: when the wall of reactor temperature is 730 ℃, use N
2/ NH
3/ SiH
2Cl
2Mixing implement with chemical vapour deposition technique.And the actual implementation method of this silicon nitride layer of an etching dry-etching method for example, air pressure is at 75milli-torr (mt), with 1600 watts of (Watts, energy W), and C
4F
8/ Ar/CH
3The mixing of F decides the terminal point that stops etching.Next step is aimed at this clearance wall 150 and 151 and injects one second dopant as described in the step square 21, in Fig. 9, produces two diffusion zones 147 and 148 respectively at diffusion zone 145 and 146 both sides.In the present embodiment, be the selectivity of eat-backing substrate 110 surfaces with the clearance wall 150 of silicon nitride formation and 151 purpose in order to promote.Certainly, also can adopt other to have the material that to promote etching selectivity and form clearance wall.
Next step, form a self-aligned silicide (self aligned silicide, salicide).As described in step square 22, in the diffusion zone 147 of non-array region 111 and 148 and transistor grid structure 140 and 141 on and in array region 110 on the character line 134, alignment gap wall 150 and 151 forms the metal silicide layer 149 of a tool conductivity.And the embedding diffusion position line 128 in array region 110 and 129 since in the chemical vapour deposition technique protection of the deposition of dielectric material and clearance wall 150 and 151 avoided the effect of autoregistration metal silicide.
At last, formation one dielectric layer 160, a plurality of contact hole 161 and are positioned at the metal level 162 of the composition of the superiors on metal silicide layer 149, have just finished the manufacture method of this integrated circuit package.For making mask ROM, need in the flow process of aforementioned enforcement, for example between two steps of the sacrifice layer 125 on the non-array region 111 and the step described in the step square 17-coverings polysilicon layer 130, add a step-injection ROM sign indicating number in array region 110 in addition between the step described in the step square 16-remove.
In addition, please refer to Figure 10, this figure is a parallel diffusion position line 128 that is along the shown profile of the direction of B-B ' among Fig. 8.In array region 110, gate dielectric 118 is positioned on the diffusion position line 128, and is filled in silicon nitride and forms a clearance wall 152 structures in the gap of 134 of character lines.
This manufacture method also can be used for comprising one or more and can wipe in the embedded non-volatile memory array with programmable memory cell, for example with regard to an embedded non-volatile memory with SONOS memory cell, as long as the gate dielectric 118 that is arranged in area array 110 in the present embodiment is replaced into one comprising a composite dielectric layer with dielectric layer of trapped electron effect.Please refer to Figure 11, the combined type gate dielectric of this SONOS memory is an ONO layer structure.The material that is positioned at the dielectric layer 180 of bottom and is positioned at the dielectric layer 182 on upper strata comprises silicon dioxide, but and to be positioned in the middle of dielectric layer 180 and 182 be trapped electron layer 181, have the electron capture effect.Identical to step square 23 described steps among the manufacture method of this SONOS memory and Figure 1A～1B from step square 12, do not repeat them here.
In sum; though the present invention discloses as above with a preferred implementation; yet its also non-limiting the present invention; any those of ordinary skill in affiliated field; under the prerequisite that does not break away from design of the present invention and scope; can make various remodeling and retouching, so protection scope of the present invention should be as the criterion with the protection range that accompanying claims were limited.
Claims (33)
1. method of on a substrate, making an integrated circuit, this integrated circuit comprises that a non-volatility memorizer and that is positioned at an array zone on this substrate is positioned at other circuit of a non-array region on this substrate, described manufacture method comprises:
On the described array region of this substrate and non-array region, form a gate dielectric; On the described array region and non-array region of this substrate, cover this gate dielectric with a protective layer;
On described array region, form at least one line pattern and the described protective layer of etching to form two wires structure at least according to a bit line direction;
Between this line structure, penetrate described gate dielectric and inject a dopant in described substrate;
Between this line structure, deposit one first dielectric material to fill at least one gap between this line structure;
Described array region and non-array region are carried out smooth processing to a certain height, and this certain height exposes described line structure and is filled in first dielectric material in the gap of described line structure;
Remove the protective layer on the line structure that is positioned on described non-array region and the array region, the remaining part that stays described gate dielectric and be filled in first dielectric material in the gap between line structure;
On the described gate dielectric of part and be filled on first dielectric material in the gap between described line structure and cover a polysilicon layer;
In described array region, form at least one character line pattern, in described non-array region, form at least one transistor grid structure pattern, and according to the described polysilicon layer of this pattern etching, make in this array region, to define at least one character line, and in described non-array region, define at least one transistor grid structure;
In described non-array region, inject a dopant, to form at least one drain electrode and source region;
In the drain electrode of described non-array region and source region, form a self-aligned silicide;
On described array region and non-array region, cover one second dielectric materials layer (160); And
On described second dielectric materials layer, form and define metal level.
2. manufacture method as claimed in claim 1 also comprises: inject described dopant so that before forming described drain electrode and source region in described non-array region, earlier the oxide layer in two these non-array regions of degree oxidation.
3. manufacture method as claimed in claim 1, wherein in described non-array region, inject dopant and comprise with the process that forms drain electrode and source region:
Aim at described transistor grid structure and inject one first dopant;
On this transistor grid structure, form at least one clearance wall; And
Aim at this clearance wall and inject one second dopant.
4. manufacture method as claimed in claim 1, wherein in described non-array region, inject dopant and comprise with the process that forms drain electrode and source region:
Aim at described transistor grid structure and inject one first dopant;
On described transistor grid structure, form at least one clearance wall, and filling gap between this character line to form described clearance wall identical materials between the character line of described array region; And
Aim at described clearance wall and inject one second dopant.
5. manufacture method as claimed in claim 1, wherein in non-array region, inject dopant and comprise with the process that forms drain electrode and source region:
Aim at described transistor grid structure and inject one first dopant;
On described transistor grid structure, use different dielectric materials to form at least one clearance wall; And
Aim at this clearance wall and inject one second dopant.
6. manufacture method as claimed in claim 1, wherein in non-array region, inject dopant and comprise with the process that forms drain electrode and source region:
Aim at described transistor grid structure and inject one first dopant;
On described transistor grid structure, use silicon nitride to form at least one clearance wall; And
Aim at this clearance wall and inject one second dopant.
7. manufacture method as claimed in claim 1, the gate dielectric that wherein is arranged in described array region comprises ONO sandwich bedded structure.
8. manufacture method as claimed in claim 1, the process that wherein deposits one first dielectric material comprise utilizes chemical vapour deposition technique to deposit, and this first dielectric material comprises silicon dioxide.
9. manufacture method as claimed in claim 1, the process that wherein deposits one first dielectric material comprise utilizes the plasma reinforced chemical vapour deposition method to deposit, and this first dielectric material comprises silicon dioxide.
10. manufacture method as claimed in claim 1, the step that wherein deposits described first dielectric material comprises: a temperature all is lower than 500 ℃ deposition step.
11. manufacture method as claimed in claim 1, wherein smooth processing procedure comprises: use chemical mechanical milling method.
12. manufacture method as claimed in claim 1 is included in and forms after the self-aligned silicide at least one ROM sign indicating number of injection in described array region.
13. manufacture method as claimed in claim 1, wherein said protective layer comprise that a thickness is the silicon nitride layer of 300 dusts.
14. manufacture method as claimed in claim 1, the thickness of wherein said polysilicon layer are 1500 dusts.
15. manufacture method as claimed in claim 1, wherein said protective layer comprises a silicon nitride layer, and the thickness range of this silicon nitride layer is between 100 dust to the 1000 Izod right sides.
16. manufacture method as claimed in claim 1, the thickness range of wherein said polysilicon layer is between 1300 dust to the 1600 Izod right sides.
17. the method for claim 1, wherein said non-volatility memorizer are mask ROM;
Wherein said protective layer is a silicon nitride layer;
Wherein deposition one first dielectric material comprises with the step of filling at least one gap between this line structure between this line structure: when using chemical vapour deposition technique and temperature to be lower than 650 ℃, deposition one first dielectric material between described gate electrode structure is to fill at least one gap between gate electrode structure;
Wherein on described second dielectric materials layer, form and define metal level after also comprise: at least one ROM sign indicating number of injection in described array region.
18. manufacture method as claimed in claim 17 is wherein injected dopant and is comprised with the process that forms drain electrode and source region in described non-array region:
Aim at described transistor grid structure and inject one first dopant;
On described transistor grid structure, form at least one clearance wall with silicon nitride; And
Aim at this clearance wall and inject one second dopant.
19. manufacture method as claimed in claim 17 is wherein saidly carried out smooth processing procedure and is comprised: use chemical mechanical milling method.
Utilize the plasma reinforced chemical vapour deposition method to deposit 20. manufacture method as claimed in claim 17, the process that wherein deposits one first dielectric material comprise, and this first dielectric material comprise silicon dioxide.
21. manufacture method as claimed in claim 17, the thickness of wherein said silicon nitride layer are 300 dusts.
22. manufacture method as claimed in claim 17, the thickness of wherein said polysilicon layer are 1500 dusts.
23. manufacture method as claimed in claim 17, the thickness range of wherein said silicon nitride layer is between 100 dust to the 1000 Izod right sides.
24. manufacture method as claimed in claim 17, the thickness range of wherein said polysilicon layer is between 1300 dust to the 1600 Izod right sides.
25. the method for claim 1, gate dielectric on the wherein said array region is the combined type gate dielectric, and described combined type gate dielectric comprises: the dielectric layer with trapped electron effect and that a dielectric layer, that is positioned at bottom is positioned at the intermediate layer is positioned at the dielectric layer on upper strata;
Wherein said protective layer is a silicon nitride layer;
Wherein deposition one first dielectric material comprises with the step of filling at least one gap between this line structure between this line structure: when using chemical vapour deposition technique and temperature to be lower than 650 ℃, deposition one first dielectric material between described gate electrode structure is to fill at least one gap between gate electrode structure.
26. manufacture method as claimed in claim 25 is wherein injected dopant and is comprised with the process that forms drain electrode and source region in described non-array region:
Aim at described transistor grid structure and inject one first dopant;
On described transistor grid structure, form at least one clearance wall with silicon nitride; And
Aim at this clearance wall and inject one second dopant.
27. manufacture method as claimed in claim 25, wherein smooth processing procedure comprises: use chemical mechanical milling method.
Utilize the plasma reinforced chemical vapour deposition method to deposit 28. manufacture method as claimed in claim 25, the process that wherein deposits one first dielectric material comprise, and this first dielectric material comprise silicon dioxide.
29. manufacture method as claimed in claim 25, wherein said dielectric layer with trapped electron effect comprises silicon nitride.
30. manufacture method as claimed in claim 25, the thickness of wherein said silicon nitride layer are 300 dusts.
31. manufacture method as claimed in claim 25, the thickness of wherein said polysilicon layer are 1500 dusts.
32. manufacture method as claimed in claim 25, the thickness range of wherein said silicon nitride layer is between 100 dust to the 1000 Izod right sides.
33. manufacture method as claimed in claim 25, the thickness range of wherein said polysilicon layer is between 1300 dust to the 1600 Izod right sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03153080.XA CN1291481C (en) | 2003-08-12 | 2003-08-12 | Method for manufacturing imbedded non-volatile memory with sacrificed layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03153080.XA CN1291481C (en) | 2003-08-12 | 2003-08-12 | Method for manufacturing imbedded non-volatile memory with sacrificed layer |
Publications (2)
| Publication Number | Publication Date |
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| CN1581467A CN1581467A (en) | 2005-02-16 |
| CN1291481C true CN1291481C (en) | 2006-12-20 |
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| CN03153080.XA Expired - Lifetime CN1291481C (en) | 2003-08-12 | 2003-08-12 | Method for manufacturing imbedded non-volatile memory with sacrificed layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9633734B1 (en) * | 2016-07-14 | 2017-04-25 | Ememory Technology Inc. | Driving circuit for non-volatile memory |
| US9881930B1 (en) | 2016-10-21 | 2018-01-30 | International Business Machines Corporation | Simple integration of non-volatile memory and complementary metal oxide semiconductor |
| CN114335004B (en) * | 2022-03-11 | 2022-05-17 | 江苏游隼微电子有限公司 | 1.5T SONOS device and preparation method thereof |
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