CN1237607C - Process for manufacturing integrated circuit on a substrate - Google Patents
Process for manufacturing integrated circuit on a substrate Download PDFInfo
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- CN1237607C CN1237607C CN03143603.XA CN03143603A CN1237607C CN 1237607 C CN1237607 C CN 1237607C CN 03143603 A CN03143603 A CN 03143603A CN 1237607 C CN1237607 C CN 1237607C
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- 238000004519 manufacturing process Methods 0.000 title claims description 37
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- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 37
- 230000015654 memory Effects 0.000 claims abstract description 35
- 239000003989 dielectric material Substances 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 18
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- 239000002019 doping agent Substances 0.000 claims description 21
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- 238000005229 chemical vapour deposition Methods 0.000 claims description 16
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Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a first layer of polysilicon in the array portion and in the non-array portion; covering the first layer of polysilicon with a layer of silicon nitride; using two masks for gate electrode formation in a first layer of polysilicon and bit line implant processes; depositing a dielectric material among the gate electrode structures to fill gaps among the gate structures; planarizing the deposited oxide; removing said layer of silicon nitride and applying a second layer of polysilicon material; patterning wordlines in the array portion over said gate electrode structures, and transistor gate structures in said non-array portion, and applying LDD, silicide and other logic circuit processes.
Description
Technical field
The present invention relates to a kind of method of on substrate, making integrated circuit, be specifically related to have the manufacture method of the nonvolatile memory of small critical dimension, and particularly relevant for a kind of manufacture method that is applicable to the embedded non-volatile memory of combined type integrated circuit.
Background technology
Along with the improvement of Manufacturing Technology of integrated circuit, be positioned at that size of component also reduces gradually on the integrated circuit, and the degree of integration of the function on the one chip increases gradually also.Therefore, many chips that contain the embedded non-volatile memory of logic functional element are just arranged around here, for example Memory Controller (memorycontrollers), general processor (general-purpose processors), input/output interface logic (input/output interface logic), special logic (dedicated logic), digital signal processor (digital signal processors), and the design of various chips etc. with other function.
The combined type integrated circuit that has miniature scale at present all still has some problems and waits to solve on design and technology.For example, when the width of diffusion conductor more hour, then the resistance of conductor is big more.Therefore,, can use existing automatic aligning metal silicide technology (salicide) usually, promptly form a high conductive layer to reduce the resistance value of diffusion conductor in the diffusion surface of conductors in order to solve such problem.For example, utilizing for example is the silicide (silicide) that waits of titanium silicide (titanium silicide) etc., forms a film in spreading surface of conductors in the automatic aligning deposition step of aiming at the metal silicide technology automatically.Yet, to use when aiming at the metal silicide technology automatically, the technology that forms high-density storage with some is also incompatible.
For example, aiming at the metal silicide technology automatically in forming the clearance wall step, clearance wall is used as mask and uses.This process that forms clearance wall comprises etched step, and using plasma carries out the dry ecthing mode of membrane attack usually.Yet this step of eat-backing may be destroyed the surface of this siliceous substrate, and causes the substrate surface infringement to cause the generation of leaky.This leaky will cause the phenomenon of the soft electricity collapse of memory, especially will especially severe for the influence of high density memory arrays.
In addition, when element is more little, the length of raceway groove also will shorten thereupon.Therefore, transistorized operating rate will be accelerated, and various problem of being derived because of diminishing of channel length just can take place one by one.This is called short-channel effect (short channel effect).But oxidation now and high-temperature heat flux method are injected dopant (dopants), and the diffusion that causes can not be shortened transistorized raceway groove effectively.This phenomenon is called heat and strengthens diffusion phenomena (thermally enhanced diffusion) and oxidation-enhanced diffusion phenomenon (oxidationenhanced diffusion).
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of manufacture method that can be suitable for making high-density nonvolatile memory and high peripheral logic circuit.This manufacture method can reduce or avoid the problems of deriving because of the element of making small critical dimension, for example short-channel effect, destroy the soft electric breakdown effect that causes because of oxidation, and the problems such as high resistance of narrow diffusion conductor.
According to above-mentioned purpose, the invention provides a kind of use two polysilicon layers, make manufacture method as mask-type ROM (mask ROM) or SONOS memory high density nonvolatile memories such as (SONOS memory).Those high-density nonvolatile memories and high peripheral logic devices (advancedperipheral logic) integration is formed on the one chip.Embodiment among the present invention provides a kind of method of making integrated circuit on substrate.This integrated circuit comprises that the nonvolatile memory and in an array zone that is arranged on the substrate is arranged in other circuit of the non-array region on the substrate.This manufacture method comprises the following steps:
At first, array region and the non-array region at substrate forms a gate dielectric.Then, at the array region and the non-array region of substrate, cover first polysilicon layer in the gate dielectric top.Then, cover silicon nitride layer in first polysilicon layer top.Afterwards, in array region and along word-line direction definition and this silicon nitride layer of etching and the many bar lines being used for gate electrode of this first polysilicon layer to form.Then, also the described many lines of etching are to form a plurality of gate electrodes along the direction definition perpendicular to word line, and wherein, those gate electrodes comprise remaining first polysilicon layer and silicon nitride layer.Then, inject dopant to the array region of substrate perpendicular to gate dielectric lines word-line direction and between grid, wherein, dopant injects in the mode that penetrates a plurality of non-overlay areas on the gate dielectric.Afterwards, remove perpendicular to word-line direction and those gate dielectric lines between grid.Then, deposit a dielectric material between those gate electrodes, to fill a plurality of gaps between those gate electrodes.Then, planarization array region and non-array region to a certain height, and can expose dielectric material in silicon nitride layer and a plurality of gaps between those gate electrodes in this certain height.Afterwards, remove be positioned on the non-array region with gate electrode on silicon nitride layer, and stay dielectric material in first remaining polysilicon layer and a plurality of gaps between those gate electrodes.Then, cover the dielectric material top of second polysilicon layer in first remaining polysilicon layer and a plurality of gaps between those gate electrodes.Then, define many word lines those gate electrode tops in array region, and, define a plurality of transistor gates in non-array region, again according to those word lines and remaining first polysilicon layer and second polysilicon layer of those transistor gate etchings.Afterwards, inject dopant to non-array region, to form a plurality of source electrodes and a plurality of drain electrode.Then, form the automatic silicide of aiming in those source electrodes and those drain electrodes.Then, the coating dielectric layer is in array region and non-array region top.At last, be coated with defined metal level in the dielectric layer top.
Generally speaking, in various embodiments, the thickness of the polysilicon layer of deposition is about 300 dusts, or its thickness range is between 200 dust to 450 dusts.The thickness of the silicon nitride layer of deposition then also is about 300 dusts, or its thickness range is also between 200 dust to 450 dusts.And the thickness that deposits second polysilicon layer is about 1500 dusts, or its thickness range is between 1300 dust to 1600 dusts.
Embodiments of the invention comprise that (lightly doped drain, LDD) technology is to improve transistor performance, particularly at peripheral circuit for the so-called lightly doped drain of application.In using lightly doped drain technology, injecting dopant at non-array region comprises with the method that forms drain electrode and source region: aim at transistor gate construction, inject first dopant, formation clearance wall and alignment gap wall inject steps such as second dopant on transistor gate construction.Form clearance wall with silicon nitride, purpose is the selectivity of eat-backing in order to increase.Yet, also can adopt other to have the material that can increase etching selectivity and form clearance wall, to be used for aiming at metal silicide technology (self aligned silicide automatically, salicide) use as mask in the step, cause the generation of leaky with the destruction of reducing siliceous substrate surface.
In the embodiments of the invention, deposition of dielectric materials on the gate dielectric with interstitial wire behind the interstructural gap, impose the process of planarization again, comprise use chemical vapour deposition technique (chemical vapordeposition, CVD), plasma enhanced chemical vapor deposition method (plasma enhanced CVD) or the chemical vapour deposition technique of other any low temperature deposit.And the wall temperature of reactor preferably is lower than 650 degree Celsius.
In flatening process, (chemical mechanicalpolishing CMP), can further reduce the problem that Yin Gaowen caused in manufacture process in the chemico-mechanical polishing of use low temperature.
Above-mentioned method is made on the mask-type ROM except can be applicable to, and also can be applicable to one and comprise and can erase and programmable storage, for example be on the embedded non-volatile memory array of SONOS.This SONOS memory comprises the gate dielectric of combined type, and it is the layer structure of ONO.This composite bed comprises the silicon dioxide dielectric layers that is positioned at bottom, is positioned at the silicon nitride dielectric layer with trapped electron effect in intermediate layer and the silicon dioxide dielectric layers that is positioned at the upper strata.
Therefore, the invention provides the manufacture method that being used on the combined type integrated circuit embeds two polysilicon layers of mask ROM array and SONOS array.After forming grid polycrystalline silicon electrode step, utilize injection mode to form the buried diffusion layer serves (buried diffusion layers) of source electrode and drain electrode again.This mode can reduce heat and strengthen diffusion phenomena (thermally enhanced diffusion) and oxidation-enhanced diffusion phenomenon (oxidation enhanced diffusion), also may cause short-channel effect.Between word line and gate electrode, form thick dielectric layer with low temperature depositing and chemico-mechanical polishing, can be used to avoid between buried diffusion layer serves and word line, taking place the phenomenon of soft electricity collapse.Define first polysilicon layer and use the twice mask, this twice mask is used on first polysilicon layer, formation can with the rectangle that is connected in the formed word line of second polysilicon layer or square gate electrode.Second polysilicon layer is used for forming word line connecting the gate electrode in the array region, and second polysilicon layer and to be used for be that peripheral circuit forms transistor gate.The purpose that forms silicon nitride gap wall is in order to increase etched selectivity, and prevents the destroyed of gate dielectric, and reduces owing to the destroyed problems such as leaky that cause of buried doped region territory dielectric material.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A～1B is the flow chart according to the manufacture method of the embodiment of the invention;
Fig. 2～10th is according to the structure chart of the combined type integrated circuit with embedded mask memory shown in Figure 1A～1B step;
Figure 11 is the structure chart of the embedded non-volatile memory with SONOS memory of the technology of application drawing 2～10.
Description of reference numerals
110 array regions, 111 non-array regions
113 dielectric regimes, 112 dielectric regimes
114 P type traps, 115 N type traps
116 dark N type trap 117 P type traps
118 gate dielectrics, 119 gate dielectrics
124 first polysilicon layers, 125 silicon nitride layers
126 gate electrodes, 127 gate electrodes
128 bury diffusion position line 129 buries diffusion position line
130 second polysilicon layer 131a oxides
133 gate electrodes, 134 word lines
135 gate electrodes, 136 gate electrodes
140 transistor gates, 141 transistor gates
145 diffusion zones, 146 diffusion zones
147 diffusion zones, 148 diffusion zones
149 metal silicide layers, 150 clearance walls
151 clearance walls, 160 dielectric layers
161 contact holes, 162 patterned metal layers
170 clearance walls, 180 dielectric layers
181 trapped electron layers, 182 dielectric layer
Embodiment
The disclosed manufacture method of the present invention will be described in detail as follows with the embodiment conjunction with figs..Figure 1A～1B is the flow chart according to the manufacture method of the embodiment of the invention.Fig. 2～1O is the structure chart according to the combined type integrated circuit with embedded mask memory shown in Figure 1A～1B step.And Figure 11 is the structure chart of the embedded non-volatile memory with SONOS memory of application drawing 2～10 technologies.
Please refer to Figure 1A～1B, each step is arranged according to digital size order with step square 10 to step square 24, and manufacture method of the present invention is described.At first, as described in step square 10, on substrate, separate substrate to define array region 110 and non-array region 111 with dielectric regime 112.As shown in Figure 2, dielectric regime 112 adopt regional silicon oxidation method (local oxidation of silicon, LOCOS) or other prior art fill oxide or other dielectric material in a groove be formed on the substrate.And in non-array region 111, adopt CMOS (Complementary Metal Oxide Semiconductor) (the complementary metal-oxide semiconductor of existing application on logical circuit, CMOS) technology is separated non-array region 111 with dielectric regime 113, makes the N channel region that defines a N channel element and the P channel region of a P channel element.Wherein, P type trap 114 is formed at the N channel region, and N type trap 115 then is formed at the P channel region.In the present embodiment, array region 110 comprises a dark N type trap 116, and P type trap 117 is formed at dark N type trap 116 tops.So, just in P type trap 117, form a N channel transistor structure element.In certain embodiments, can in array region 110, use above-mentioned many well structure combinations to reach the purpose of insulation.For example, the forming process of degeneration trap (retrograde well) can be applied to produce the deep trap structure, makes starting voltage (Vt) to be injected in the memory cell area.The process that produces the deep trap structure comprises the process that forms two degeneration traps.Generally speaking, degeneration trap forming process comprises: the identical mask of injection → use that injects one trap → counterelectrode tunnelling (anti-punch through) injects starting voltage.
In addition, according to the mode of above-mentioned formation degeneration trap process, when forming N type trap 116 and P type trap 117, use two mask layers.For making N type semiconductor (NMOS) element, its typical method for implanting is as follows: use the voltage of about 150,000～250,000 KeV when injecting trap, concentration about 10
13Dose/cm
2Boron (B); When the counterelectrode tunnelling is injected, use the voltage of about 50,000～80,000 KeV, concentration about 10
12Dose/cm
2Boron; When injecting starting voltage, use the voltage of about 50,000～80,000 KeV, concentration about 10
12Dose/cm
2Boron difluoride (BF
2).And for making P type semiconductor (PMOS) element, its typical method for implanting is as follows: use the voltage of about 550,000～600,000 KeV, concentration about 10 when injecting trap
13Dose/cm
2Phosphorus (P); When the injection of counterelectrode tunnelling, use the voltage of about 250,000～300,000 KeV, concentration about 2 * 10
12Dose/cm
2Phosphorus; When injecting starting voltage, use the voltage of about 100,000～120,000 KeV, concentration about 2 * 10
12Dose/cm
2Phosphorus.In certain embodiments, in this array region 110 the combination purpose of many well structures as the usefulness of isolating with insulation.
In the narration of step square 11, gate dielectric 118 and 119 is formed at respectively on array region 110 and the non-array region 111, as shown in Figure 2.Gate dielectric 118 and 119 has identical formation step or owing to using different processing steps for the gate dielectric of distinguishing on zones of different.For example, have among the embodiment of SONOS memory one, gate dielectric 118 is the structure of a combined type multilayer, and gate dielectric 119 then still is the structure of silicon dioxide (silicondioxide) layer of individual layer, as shown in figure 11.
After forming gate dielectric 118 and 119, described in step square 12, deposit first polysilicon layer 124 in the top of gate dielectric 118 and 119, then, in step square 13, again in the top deposited silicon nitride layer 125 of first polysilicon layer 124, as shown in Figure 3.Therefore, first polysilicon layer 124 is covered in the top of the gate dielectric of array region 110 and non-array region 111.The thickness of first polysilicon layer 124 about 100 dusts (angstrom) between 1000 dusts.Generally speaking, the thickness of first polysilicon layer 124 is about the 300 Izod right sides, or its thickness range is 200 dust to 450 dusts.And at the thickness of the silicon nitride layer 125 above first polysilicon layer 124 also between 100 dust to 1000 dusts.Generally speaking, the thickness of silicon nitride layer 125 also is about the 300 Izod right sides, or its thickness range is 200 dust to 450 dusts.
In step square 14, define a bit line and gate electrode at array region 110, and etches both silicon nitride layer and first polysilicon layer are till the gate dielectric 118.Utilize the twice mask, comprise that the step that defines one first photoresist layer is to form the layer that divests on the word-line direction.Silicon nitride layer and first polysilicon layer come in addition etching according to the first photoresist layer.And after the first photoresist layer is divested, then in the direction perpendicular to word line, promptly be coated with one second photoresist along the direction of bit line and divest layer.Along bit line direction and between the remaining part that belongs to the silicon nitride layer and first polysilicon layer that divests between the layer, all it is removed to the gate dielectric that is stored in the array region, comprise residual fraction and pile up the gate electrode that forms with first polysilicon layer and silicon nitride layer and stay.Next step uses to divest layer along second photoresist of bit line direction and be mask, by the gate dielectric that exposes inject bury diffusion position line 128 and 129 (such as step square 15 narration).And can be for the method that diffusion position line is buried in injection: dopant comprises that containing one injects the package that P type BD is injected in N type BD and a back earlier.Wherein, N type BD is with the voltage of 30,000～60,000 KeV, implantation concentration about 2 * 10
15～3.5 * 10
15Dose/cm
2Arsenic (arsenic, As), and P type BD is with the voltage of 1.5 ten thousand～40,000 KeV, implantation concentration about 3 * 10
13～5 * 10
13Dose/cm
2Boron.In the process of these injections, the certain chip that employed voltage and material concentration all can be produced according to desire or the structure of special component or technology are adjusted and are changed.
Please refer to 5, and as described in the step square 16.Between the gate electrode 126 and 127 in array region 110, earlier deposition one dielectric material on gate dielectric 118 to fill except gate electrode 126 and 127 gap of being vacated.Again impose planarization (planarization) thereafter.In this embodiment, deposition process can use chemical vapour deposition technique (chemical vapor deposition, CVD) or plasma enhanced chemical vapor deposition method (plasma enhanced CVD) deposition contain the dielectric material of silicon dioxide (silicon dioxide).And in deposition process, the wall of reactor must maintain the situation of lower temperature as much as possible.For example, the temperature maintenance of the wall of reactor is being lower than 650 degree Celsius.Dielectric material then comprises silicon dioxide.Again for example, dielectric material comprise tetraethyl orthosilicate salt (tetraethylorthosilicate, TEOS) with oxygen (O
2) mixture, and the temperature maintenance of the wall of reactor be lower than Celsius 630 the degree.Other mentioned in embodiments of the present invention deposition process also can be taked to control the modes that the wall of reactor temperature is lower than 650 degree Celsius and carry out.In flatening process, (chemical mechanical polishing CMP) then can be better than the high-temperature heat flux method that involves a reflux in the chemico-mechanical polishing of use low temperature.Deposition of dielectric materials in the gap after, can use contrary memory cell grid technology (reverse cell gate process) to promote the uniformity of chemico-mechanical polishing.Should contrary memory cell grid technology then comprise forming the photoresist figure, eat-backing, removes step such as photoresist figure, with for before polishing earlier the reduction pattern density to the influence of dielectric material.As shown in Figure 5, oxide 131a and 131b are filled in the gap, and between gate electrode 126 and 127, make substrate have a smooth upper surface.
As described in step square 17, after the planarisation step, remove the silicon nitride layer that is positioned on array region 110 and the non-array region 111.As described in the step square 18, deposit second polysilicon layer 130 then in dielectric layer that exposes and first polysilicon layer top.Its result as shown in Figure 6, wherein silicon nitride layer (as the silicon nitride layer among Fig. 5 126,127) is removed, and second polysilicon layer 130 is finished deposition.The thickness of second polysilicon layer 130 is about 1500 dusts, or its thickness range is between 1300 dust to 1600 dusts.
Please refer to Fig. 7, and as described in the step square 19, after deposition second polysilicon layer 130, in array region 110, define the word line figure and, make and in array region 110, define word line 134 according to figure etching first polysilicon layer and second polysilicon layer.And in non-array region 111, define transistor gate 140 and 141.Gate electrode 135,136 in the memory cell then is positioned at the below of polysilicon word line 134.
Please refer to Fig. 8, it is according to the schematic diagram of overlooking from substrate top surface shown in Figure 7.The diffusion position line 128 and 129 of burying that is positioned at lower floor is arranged along B-B ' direction, arranges with 134 one-tenth square crossings of the word line that is positioned at the upper strata along A-A ' direction.Gate electrode 126 and 127 is positioned at word line 134 belows entirely.The zone of chemical vapour deposition (CVD), for example 132, be filled in the space between gate electrode, and in abutting connection with word line 134 and be positioned at the top of burying diffusion position line 128 and 129.Polysilicon word line 134 is wideer than gate electrode 132,133, and it is to improve conductance, and another purpose is then for improving the problem of mask alignment.
(lightly doped drain, LDD) before the step, first two spend the gate dielectrics 119 in the non-array region 111 of oxidations at lightly doped drain.Please refer to Fig. 9, it is along parallel wordlines 134, promptly along the profile shown in the direction of A-A ' among Fig. 8.As described in step square 20, in non-array region 111, aim at transistor gate 140, inject first dopant to form drain electrode and source area, as for transistor gate 140, form diffusion zone 145 and 146.Afterwards, as described in step square 21, deposited silicon nitride layer and in addition after anisotropy (anisotropic) etching forms two silicon nitride gap walls, as for transistor gate construction 140, forms clearance wall 150 and 151.The implementation method of deposited silicon nitride layer can for example be: when the wall temperature of reactor is 730 degree Celsius, use N
2/ NH
3/ SiH
2Cl
2Mixing implement with chemical vapour deposition technique.The implementation method of etches both silicon nitride layer then can be for example with the dry-etching method, and air pressure is at 75milli-torr (mt), with 1600 watts of (Watts, energy W), and C
4F
8/ Ar/CH
3The mixing of F decides the terminal point that stops etching.Next step is as described in the step square 22, and alignment gap wall 150 and 151 injects second dopant.In Fig. 9,, produce two diffusion zones 147 and 148 respectively in clearance wall 150,151 both sides.In the present embodiment, clearance wall 150 and 151 purposes that form with silicon nitride are the selectivity of eat-backing substrate surface in order to increase.
Next step, and formation one automatic aligning silicide (self aligned silicide, salicide).As described in step square 23, in the diffusion zone 147 of non-array region 111 and 148 and transistor gate 140 and 141 on, and in array region 110 on the word line 134, alignment gap wall 150 and 151 forms the metal silicide layer 149 of tool conductivity.And in array region 110, bury diffusion position line 128 and 129, because the deposition of dielectric material has been avoided automatic effect of aiming at metal silicide with clearance wall 150 and 151 protection in the chemical vapour deposition technique.
At last, formation dielectric layer 160, a plurality of contact hole 161 and are positioned at the patterned metal layer 162 of the superiors on metal silicide layer 149, have just finished the manufacture method of this integrated circuit component.For making mask-type ROM; need in the flow process of aforementioned enforcement, for example between two steps of the step (covering second polysilicon layer) described in step described in the step square 17 (removal is arranged in the protective layer on the non-array region 111) and the step square 18, add a step (injecting ROM sign indicating number (ROM code)) in addition at array region 110.
In addition, please refer to Figure 10, it is along parallel diffusion position line 128, promptly along the profile shown in the direction of B-B ' among Fig. 8.The dielectric material district 165 of chemical vapour deposition (CVD) is between gate electrode 135 and 136.Silicon nitride gap wall 170 then is filled between the word line 134.
The manufacture method of the invention described above, also can be used for comprising one or more can erase and the embedded non-volatile memory array of programmable memory cell in, for example with regard to an embedded non-volatile memory with SONOS memory cell, as long as the gate dielectric 118 that is arranged in area array 110 in the present embodiment is replaced into one comprising a composite dielectric layer with dielectric layer of trapped electron effect.Please refer to Figure 11, the combined type gate dielectric of SONOS memory is the layer structure of an ONO.The material that is positioned at the dielectric layer 180 of bottom and is positioned at the dielectric layer 182 on upper strata comprises silicon dioxide, but and be positioned at dielectric layer 180 and 182 intermediate are trapped electron layer 181, have the effect of electron capture.Identical to step square 23 described steps among the manufacture method of this SONOS memory and Figure 1A～1B from step square 12, do not repeat them here.
In sum; though the present invention discloses as above in conjunction with a preferred embodiment; right those skilled in the art are appreciated that technology of the present invention is not confined to this; any those skilled in the art; without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, so protection scope of the present invention is with being as the criterion that claims were defined.
Claims (19)
1. method of on substrate, making integrated circuit, this substrate has other circuit that a nonvolatile memory and that is arranged in an array zone is arranged in a non-array region, and this manufacture method comprises:
Form a gate dielectric in this array region and this non-array region;
Cover one first polysilicon layer in this gate dielectric top;
Cover a silicon nitride layer in this first polysilicon layer top;
In this array region and along word-line direction definition and this silicon nitride layer of etching and this first polysilicon layer to be formed for many lines of gate electrode;
Also the described many lines of etching are to form a plurality of gate electrodes along the direction definition perpendicular to this word line, and wherein, those gate electrodes comprise remaining this first polysilicon layer and this silicon nitride layer;
Inject a dopant to this array region of this substrate perpendicular to this word-line direction and the gate dielectric lines between grid, wherein, this dopant injects in the mode that penetrates a plurality of non-overlay areas on this gate dielectric;
Removal is perpendicular to this word-line direction and those gate dielectric lines between grid;
Deposit a dielectric material between those gate electrodes, to fill a plurality of gaps between those gate electrodes;
This array region of planarization and this non-array region to a certain height, and can expose this dielectric material in this silicon nitride layer and a plurality of gaps between those gate electrodes in this certain height;
Removal be positioned on this non-array region with this gate electrode on this silicon nitride layer, and stay this remaining first polysilicon layer and this dielectric material in a plurality of gaps between those gate electrodes;
Cover one second polysilicon layer in this remaining first polysilicon layer and this dielectric material top in a plurality of gaps between those gate electrodes;
Define many word lines those gate electrode tops in this array region, and, define a plurality of transistor gates in this non-array region, then, according to those word lines and remaining this first polysilicon layer and this second polysilicon layer of those transistor gate etchings;
Inject a dopant to this non-array region, to form a plurality of source electrodes and a plurality of drain electrode;
Form one and aim at silicide automatically in those source electrodes and those drain electrodes;
Be coated with a dielectric layer in the non-array region of this array region and this top; And
Be coated with once the metal level that defines in this dielectric layer top.
2. manufacture method as claimed in claim 1 is wherein injected this dopant to this non-array region in this, before the step that forms those source electrodes and those drain electrodes, also comprises the step of this gate dielectric in one or two these non-array regions of degree oxidation.
3. manufacture method as claimed in claim 1 is wherein injected this dopant to this non-array region in this, to comprise in the step that forms those source electrodes and those drain electrodes:
Aim at those transistor gates, inject one first dopant;
Form a plurality of clearance walls on those transistor gates; And
Aim at those clearance walls, inject one second dopant.
4. manufacture method as claimed in claim 3 also comprises:
Filling a spacer material goes between those word lines of this array region.
5. manufacture method as claimed in claim 3, wherein
Use one is different from the material of this dielectric material of deposition, to form a plurality of clearance walls on those transistor gates.
6. manufacture method as claimed in claim 1, this gate dielectric that wherein is arranged in this array region comprises an ONO sandwich layer structure.
7. manufacture method as claimed in claim 1, wherein the step of this this dielectric material of deposition utilizes chemical vapour deposition technique to deposit, and this dielectric material is a silicon dioxide.
8. manufacture method as claimed in claim 1, wherein the step of this this dielectric material of deposition uses a depositing temperature that is lower than 650 degree Celsius to deposit this dielectric material.
9. manufacture method as claimed in claim 8, wherein said nonvolatile memory comprises mask-type ROM, this step that deposits this dielectric material is used chemical vapour deposition technique, and wherein be coated with after the step of metal level above this dielectric layer of definition, also comprise and inject the step of a ROM sign indicating number to this array region in this.
10. manufacture method as claimed in claim 8, the gate dielectric that wherein is positioned at this array region is to have a composite bed that the dielectric layer with trapped electron effect and that a dielectric layer, that is positioned at bottom is positioned at the intermediate layer is positioned at the dielectric layer on upper strata, and step that should this dielectric material of deposition is used chemical vapour deposition technique.
11. as claim 1,9 or 10 described manufacture methods, wherein inject this dopant to this non-array region in this, to comprise in the step that forms those source electrodes and those drain electrodes:
Aim at those transistor gates, inject one first dopant;
Form a plurality of clearance walls on those transistor gates with silicon nitride; And
Aim at those clearance walls, inject one second dopant.
12. as claim 1,9 or 10 described manufacture methods, wherein this planarisation step is used chemical mechanical polishing method.
13. as claim 1,9 or 10 described manufacture methods, wherein the step of this this dielectric material of deposition utilizes the plasma enhanced chemical vapor deposition method to deposit, and this dielectric material is a silicon dioxide.
14. as claim 1,9 or 10 described manufacture methods, wherein the thickness of this first polysilicon layer is about 300 dusts, and the thickness of this silicon nitride also is about 300 dusts.
15. as claim 1,9 or 10 described manufacture methods, wherein the thickness of this second polysilicon layer is about 1500 dusts.
16. as claim 1,9 or 10 described manufacture methods, wherein the thickness of this first polysilicon layer is between 200 dusts and 450 dusts, and the thickness of this silicon nitride is also between 200 dusts and 450 dusts.
17. as claim 1,9 or 10 described manufacture methods, wherein the thickness of this second polysilicon layer is between 1300 dusts and 1600 dusts.
18. manufacture method as claimed in claim 10, wherein this dielectric layer with trapped electron effect is a silicon nitride.
19. manufacture method as claimed in claim 1, wherein covered this second polysilicon layer before the step of this remaining first polysilicon layer and this dielectric material top in those gaps between those gate electrodes, comprise that also one injects the step of a plurality of ROM sign indicating numbers to this array region in this.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/361,419 US6803284B2 (en) | 2003-02-10 | 2003-02-10 | Method for manufacturing embedded non-volatile memory with two polysilicon layers |
| US10/361,419 | 2003-02-10 |
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| Publication Number | Publication Date |
|---|---|
| CN1521831A CN1521831A (en) | 2004-08-18 |
| CN1237607C true CN1237607C (en) | 2006-01-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN03143603.XA Expired - Lifetime CN1237607C (en) | 2003-02-10 | 2003-07-25 | Process for manufacturing integrated circuit on a substrate |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6803284B2 (en) |
| CN (1) | CN1237607C (en) |
| TW (1) | TWI220301B (en) |
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| US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
| US20040188777A1 (en) * | 2003-03-31 | 2004-09-30 | Macronix International Co., Ltd. | Mixed signal embedded mask ROM with virtual ground array and method for manufacturing same |
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| KR100620219B1 (en) * | 2003-12-31 | 2006-09-11 | 동부일렉트로닉스 주식회사 | Fabricating method for memory device |
| US7476945B2 (en) * | 2004-03-17 | 2009-01-13 | Sanyo Electric Co., Ltd. | Memory having reduced memory cell size |
| US6946349B1 (en) * | 2004-08-09 | 2005-09-20 | Chartered Semiconductor Manufacturing Ltd. | Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| US20060084219A1 (en) * | 2004-10-14 | 2006-04-20 | Saifun Semiconductors, Ltd. | Advanced NROM structure and method of fabrication |
| US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
| US7804126B2 (en) | 2005-07-18 | 2010-09-28 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
| US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
| US20080025084A1 (en) * | 2005-09-08 | 2008-01-31 | Rustom Irani | High aspect ration bitline oxides |
| CA2521675C (en) * | 2005-09-29 | 2009-11-24 | Chipworks Inc | Method of preparing an integrated circuit die for imaging |
| US7432178B2 (en) * | 2005-10-21 | 2008-10-07 | Advanced Micro Devices, Inc. | Bit line implant |
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| KR101673015B1 (en) * | 2010-04-06 | 2016-11-04 | 삼성전자 주식회사 | Method of Fabricating a Semiconductor Device Including a bit Line Contact Plug and a Buried Channel Array Transistor |
| US8461687B2 (en) | 2010-04-06 | 2013-06-11 | Samsung Electronics Co., Ltd. | Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same |
| KR101718980B1 (en) * | 2010-04-06 | 2017-03-23 | 삼성전자주식회사 | Semiconductor Device Including a Bit Line Contact Plug and a Buried Channel Array Transistor and Method of Fabricating the Same, and a Semiconductor Module, an Electronic Circuit Board, and an Electronic System including the Same |
| CN104576522B (en) * | 2013-10-16 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | The integrated approach of surface channel CMOS logic device and SONOS devices |
| FR3051969A1 (en) * | 2016-05-31 | 2017-12-01 | Stmicroelectronics Rousset | METHOD FOR MANUFACTURING POWER DIODES, ESPECIALLY FOR FORMING A GRATEZ BRIDGE, AND CORRESPONDING DEVICE |
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| TW519756B (en) * | 2002-01-16 | 2003-02-01 | Macronix Int Co Ltd | Non-volatile memory structure and its manufacturing method |
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2003
- 2003-02-10 US US10/361,419 patent/US6803284B2/en not_active Expired - Lifetime
- 2003-06-25 TW TW092117329A patent/TWI220301B/en not_active IP Right Cessation
- 2003-07-25 CN CN03143603.XA patent/CN1237607C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
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| US20040157393A1 (en) | 2004-08-12 |
| TWI220301B (en) | 2004-08-11 |
| CN1521831A (en) | 2004-08-18 |
| TW200415758A (en) | 2004-08-16 |
| US6803284B2 (en) | 2004-10-12 |
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