CN1286167C - Structure of mask ROM and method for manufacturing the same - Google Patents
Structure of mask ROM and method for manufacturing the same Download PDFInfo
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- CN1286167C CN1286167C CN 02108452 CN02108452A CN1286167C CN 1286167 C CN1286167 C CN 1286167C CN 02108452 CN02108452 CN 02108452 CN 02108452 A CN02108452 A CN 02108452A CN 1286167 C CN1286167 C CN 1286167C
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Abstract
The present invention relates to a method for manufacturing a mask ROM, which comprises: a composite silicon oxide/silicon nitride/silicon oxide layer and a plurality of grids are orderly formed on a substrate, and the composite silicon oxide/silicon nitride/silicon oxide layer between any grid and the substrate is used as a prearranged coding region; subsequently, a plurality of bit lines are formed on the substrate between grids, and a plurality of character lines electrically connected with the grids are formed on the substrate; then, an anti-reflecting material layer, which is made by chemical vapor deposition and is provided with a coding window, and an internal dielectric layer are formed on the substrate; after that a coding technology is carried out, the anti-reflecting layer made by chemical vapor deposition is used as a coding mask, ultraviolet rays are used for radiating the substrate so as to form a plurality of writing coding regions on the prearranged coding region below the grid exposed by the coding window, and a plug is formed in the coding window.
Description
Technical field
The invention relates to a kind of read-only memory (Read Only Memory, structure ROM) and manufacture method, and particularly relevant for structure and the manufacture method of a kind of mask-type ROM (Mask ROM).
Background technology
Because read-only memory does not have and loses wherein non-volatile (Non-Volatile) characteristic of stored data because of power interruptions, therefore all must possess this type of internal memory in many electric equipment products, the normal running when starting shooting to keep electric equipment products.In the read-only memory the most the basis a kind of promptly be mask-type ROM, general mask-type ROM commonly used utilizes channel transistor to be used as memory cell, and optionally inject ion to the channel appointed zone in sequencing (Program) stage, reach control store unit conducting in read operation (On) by changing start voltage (Threshold Voltage) or close the purpose of (Off).
The structure of general mask-type ROM with the polysilicon character line (Word Line, WL) be across bit line (Bit Line, BL) on, be positioned at zone between character line below and bit line then as the channel region of memory cell.For part technology, whether mask-type ROM promptly injects with the channel intermediate ion, stores binary data " 0 " or " 1 ".Wherein, the injection ion is called coding injection (Coding Implantation) technology again to the technology in channel appointed zone.
Please refer to Fig. 1, it is the schematic top plan view of known a kind of mask-type ROM.Several parallel character lines 102 are across crossing several parallel bit lines 104 in Fig. 1, and by in the channel region of selected memory cell, promptly be in the substrate of the ion implanted region piece 110 of icon, to inject ion, to carry out the sequencing step, adjust start voltage, reach the switching purposes of control store unit when read operation.
Then please refer to Fig. 2, it is the generalized section and the method for programming thereof of known mask-type ROM.In Fig. 2, the embedded type bit line 208 of the substrate 200 that have a plurality of grid structures of forming by gate dielectric 202 and gate conductor layer 204 206 in the substrate 200, is arranged in 206 of grid structures and the insulating barrier 210 of covering embedded type bit line 208.When encoding injection technology, utilize light shield to form a patterned light blockage layer 212 earlier, desire coding region to expose.Then, carrying out admixture injection technology 214, is mask with photoresist layer 212, and with the substrate 200 that admixture injects bottom grid stack architecture 206 belows of desiring coding region, to carry out sequencing, the program code that institute's desire is formed enrolls in the read-only memory.
Because known mask-type ROM, when encoding injection, in FEOL, optionally inject admixture in the memory transistor channel region, therefore mask-type ROM must pass through many processing steps, the shipment of can casing again after injecting admixture.After such read-only memory order required time of delivery longer, and need an encoding mask that is exclusively used in coding carry out the step that the channel ion injects.And, when carrying out channel ion implantation step,, will directly influence the operating characteristic of memory cell if the position of ion implanted region piece produces the situation of misalignment (misalignment), cause the error in data in the ROM storage unit, cause the reliability of products variation.
Summary of the invention
Structure and the manufacture method thereof of a purpose of the present invention for a kind of mask-type ROM is provided is to avoid the error in data in the read-only memory.
Structure and the manufacture method thereof of another object of the present invention for a kind of mask-type ROM is provided, it can save the encoding mask that is exclusively used in coding together.
Structure and the manufacture method thereof of another purpose of the present invention for a kind of mask-type ROM is provided ETCD estimated time of commencing discharging to reduce.
According to above-mentioned purpose, the invention provides a kind of manufacture method of mask-type ROM, the method forms a charge immersing layer (for example being the silicon oxide/silicon nitride/silicon oxide composite bed) and a plurality of grid structures in regular turn in substrate, and the charge immersing layer between arbitrary grid structure and substrate is as a predictive encoding district.Then, form a plurality of bit lines in the substrate between grid structure, and in substrate, form a plurality of character lines that are electrically connected with grid structure.Then, in substrate, form ultraviolet light barrier layer and inner layer dielectric layer with coding window.Then, carrying out a coding technology, is encoding mask with the ultraviolet light barrier layer, utilizes the UV-irradiation substrate, so that the predictive encoding district of the grid structure that coding window exposes below forms a plurality of code areas that write, forms connector again in coding window.
In the manufacture method of mask-type ROM proposed by the invention, with the coding region of charge immersing layer as mask-type ROM, and utilize ultraviolet light barrier layer as encoding mask, and irradiating ultraviolet light is with the technology of encoding with coding window.Because when definition forms coding window in inner layer dielectric layer and ultraviolet light barrier layer, can in the inner layer dielectric layer of peripheral circuit region, define simultaneously and form contact hole, therefore the technology of coding window can with the contact hole process integration, and can reduce light shield one, reduce production costs.
And, owing to before the technology of mask-type ROM of the present invention can stop at contact hole technology, after the client places an order by the time, carry out the contact hole technology of peripheral circuit region and the coding technology of memory cell areas more simultaneously, so can reduce and ETCD estimated time of commencing discharging.
The invention provides a kind of structure of mask-type ROM, this structure is made of substrate, charge immersing layer (for example being the silicon oxide/silicon nitride/silicon oxide composite bed), grid structure, bit line, character line, ultraviolet light barrier layer, inner layer dielectric layer and connector.Wherein charge immersing layer is positioned in the substrate; Grid structure is positioned on the charge immersing layer, and the charge immersing layer between grid structure and substrate is as a plurality of code areas; Bit line is arranged in the substrate between grid structure; Character line is positioned on the grid structure, and is electrically connected with grid structure; The ultraviolet light barrier layer is covered in the substrate; Inner layer dielectric layer is positioned on the ultraviolet light barrier layer; And comprise a connector in inner layer dielectric layer and the ultraviolet light barrier layer.
Description of drawings
Fig. 1 is the vertical view of known a kind of mask-type ROM.
Fig. 2 is the generalized section and the method for programming thereof of known a kind of mask-type ROM.
Fig. 3 A to Fig. 3 G is the technology schematic top plan view according to the mask-type ROM of the embodiment of the invention.
Fig. 4 A to Fig. 4 G is the technology generalized section according to the mask-type ROM of the embodiment of the invention.
Description of reference numerals:
102,422: character line
104,418: bit line
110: the ion implanted region piece
200,400: substrate
202,410: gate dielectric
204: gate conductor layer
206,414,424: grid structure
208: embedded type bit line
210,420: insulating barrier
212: photoresist layer
214,416: the admixture injection technology
402: memory cell areas
404: peripheral circuit region
406: isolation structure
408: composite dielectric layer (charge immersing layer)
412: conductor layer
414: the strip conductor layer
426: light doped region
428: clearance wall
430: heavily doped region
432: source/drain regions
434: material layer
436: inner layer dielectric layer
438: coding window
440: contact window
442: the code area
444: connector
446: interconnect
Embodiment
The invention provides a kind of structure and manufacture method thereof of mask-type ROM.Fig. 3 A to Fig. 3 G is the vertical view of memory cell areas of a kind of mask-type ROM of the embodiment of the invention.Fig. 4 A to Fig. 4 G is the manufacturing process profile of a kind of mask-type ROM of the embodiment of the invention.Substrate 400 can be divided into memory cell areas 402 and peripheral circuit region 404 in Fig. 4 A and Fig. 4 G, and wherein the structure that is respectively Fig. 3 A to Fig. 3 G shown in the memory cell areas 402 of each figure is along the profile of II-II ' line.
At first, please refer to Fig. 3 A and Fig. 4 A, a substrate 400 is provided, this substrate 400 for example is the semiconductor silicon substrate.This substrate 400 can be divided into memory cell areas 402 and peripheral circuit region 404.
Then, in the peripheral circuit region 404 of this substrate 400, form a plurality of isolation structures 406.Isolation structure 406 shown here is that (Shallow Trench Isolation STI), but also can be regional area thermal oxidation (Local Oxidation, LOCOS) separator under other situation to a shallow trench isolation.
Then, form one deck composite dielectric layer 408 (charge immersing layer) in memory cell areas 402, and form one deck gate dielectric 410 in peripheral circuit region 404, composite dielectric layer 408 for example is silicon monoxide/nitrogenize silicon/oxidative silicon (ONO) layer.The material of gate dielectric 410 for example is a silica, and the method that forms gate dielectric 410 for example is thermal oxidation method (Thermal Oxidation).Wherein, in memory cell areas 402 formation one deck composite dielectric layers 408 and in the step that peripheral circuit region 404 forms a gate dielectric 410 for example is to form one deck mask layer (not icon) earlier to cover memory cell areas 402 and expose peripheral circuit regions 404, then in the substrate 400 of peripheral circuit region 404, form gate dielectric 410, remove the mask layer that covers memory cell areas 402 again.Then, form another layer mask layer (not icon) again and cover peripheral circuit region 404 and exposed memory cell areas 402, then in the substrate 400 of memory cell areas 402, form one deck composite dielectric layer 408 (charge immersing layer), remove the mask layer that covers peripheral circuit region 404 again.One deck mask layer (not icon) be can certainly form earlier and peripheral circuit region 404 and exposed memory cell areas 402 covered, then in the substrate 400 of memory cell areas 402, form one deck composite dielectric layer 408 (charge immersing layer), remove the mask layer that covers peripheral circuit region 404 again.Then, form another layer mask layer (not icon) again and cover memory cell areas 402 and exposed peripheral circuit region 404, then in the substrate 400 of peripheral circuit region 404, form gate dielectric 410, remove the mask layer that covers memory cell areas 402 again.
Then, please refer to Fig. 3 B and Fig. 4 B, in substrate 400, form one deck conductor layer 412, the material of this conductor layer 412 for example is a doped polycrystalline silicon, the method that forms conductor layer for example is in the mode of (In-Situ) dopant ion of coming personally, and utilizes chemical vapour deposition technique to form one deck doped polysilicon layer in substrate 400.Then, utilize lithography technology, this conductor layer 412 of patterning is to form a plurality of strip conductor layers 414 in memory cell areas 402.
Carrying out an admixture injection technology 416 then, is mask with strip conductor layer 414, forms a plurality of bit lines 418 in the substrate 400 that strip conductor layer 414 is exposed.And admixture injection technology 416 employed admixtures for example are the ions of N type.The step that forms bit line 418 for example is after injecting admixture with ion implantation, and (Rapid Thermal Anneal is RTA) to repair impaired lattice structure in the substrate 400 to carry out a rta technique.
Then, please refer to Fig. 3 C and Fig. 4 C, in substrate 400, form a layer insulating 420, to fill up the gap of 414 on strip conductor layer, the material of this insulating barrier 420 for example is a silica, the step that forms insulating barrier 420 for example is to form one deck silicon oxide layer with chemical vapour deposition technique in memory cell areas 402 earlier, and (Chemical Mechanical Polishing is CMP) up to the surface that exposes strip conductor layer 414 to eat-back (Etching Back) technology or chemical mechanical milling tech again.
Then, in substrate 400, form another layer conductor layer (not icon), the material of conductor layer for example is a doped polycrystalline silicon, and the method that forms conductor layer for example is in the mode of the dopant ion of coming personally, and utilizes chemical vapour deposition technique to form one deck doped polysilicon layer in substrate 400.Then, utilize lithography technology, this conductor layer of patterning is to go in memory cell areas 402 into a plurality of character lines 422, and continuation defines strip conductor layer 414 and forms a plurality of grid structures 414 again, and forms a plurality of grid structures 424 in peripheral circuit region 404.Wherein, character line 422 is electrically connected with grid structure 414, and character line 422 is across on the bit line 418, and a grid structure 414 then constitutes a memory cell with composite dielectric layer 408, the character line 422 of top and two bit lines 418 of both sides under it.
Then, please refer to Fig. 3 D and Fig. 4 D, carry out an admixture implantation step, is mask with the grid structure 424 of peripheral circuit region 404, injects admixture in grid structure 424 substrate on two sides 400, to form a light doped region 426.
Then, form one dielectric layer (not icon) in substrate 400, the material of this dielectric layer for example is silica or silicon nitride, and the method that forms dielectric layer for example is a chemical vapour deposition technique.Then, remove the part dielectric layer and form clearance wall 428 with sidewall in the grid structure 424 of peripheral circuit region 404.The method that removes the part dielectric layer for example is the anisotropic etching method.
Then, in peripheral circuit region 404, be mask with grid structure 424 with clearance wall 428, carry out an admixture implantation step, in grid structure 424 substrate on two sides 400 of peripheral circuit region 404, inject admixture, to form a dense doped region 430.Wherein light doped region 426 and dense doped region 430 are as source/drain regions 432.
Then, please refer to Fig. 3 E and Fig. 4 E, form layer of material layer 434 in substrate 400, this material layer 434 can prevent that ultraviolet light from penetrating and shine composite dielectric layer 408 (charge immersing layer).This material layer comprises that (Chemical VaporDeposition Anti-reflective Coating, CVDARC), its material for example is Si to a chemical vapour deposition (CVD) anti-reflecting layer
xN
y(OH)
z
Then, on material layer 434, form one deck inner layer dielectric layer 436, the material of this inner layer dielectric layer 436 for example be with the silicon tetraethyl acid esters (Tetra Ethyl Ortho Silicate, TEOS)/ozone (O
3) be reacting gas source, and utilize plasma enhanced chemical vapor deposition method (PlasmaEnhanced Chemical Vapor Deposition, PECVD) formed silica.Then, carry out a flatening process and make inner layer dielectric layer 436 have a flat surfaces.The method that makes inner layer dielectric layer 436 planarizations for example is chemical mechanical milling method or etch-back method.
Then, please refer to Fig. 3 F and Fig. 4 F, utilize photolithography techniques patterning inner layer dielectric layer 436 and material layer 434, with formation coding window opening 438 (Code Window) on the desire code storage unit of memory cell areas 402, and in the contact window 440 (Contact Window) of peripheral circuit region 404 formation exposure grid structures 424.
Then, with material layer 434 is encoding mask, utilize UV-irradiation substrate 400 with the technology of encoding, make the memory cell of ultraviolet light via coding window opening 438 irradiation desire codings, the composite dielectric layer 408 (charge immersing layer) that makes electronics inject memory cell forms electric charge code area 442, and thus the preset program code is enrolled in the mask-type ROM.
Then please refer to Fig. 3 G and Fig. 4 G, form one deck conductor layer (not icon) in substrate 400, this conductor layer fills up coding window opening 438 and contact window 440.Then, remove coding window opening 438 and contact window 440 unnecessary conductor layer in addition to form connector 444.Then, in substrate 400, form another layer conductor layer (not icon), and this conductor layer of patterning is to form the interconnect 446 that electrically contacts with connector 444.
According to above-mentioned manufacture method, can form the structure of mask-type ROM assembly provided by the present invention.Please refer to Fig. 4 G, understanding the structure of mask-type ROM assembly proposed by the invention, it comprise substrate 400, composite dielectric layer 408 (charge immersing layer) (for example being the silicon oxide/silicon nitride/silicon oxide composite bed) but, the material layer 434 (for example being the chemical vapour deposition (CVD) anti-reflecting layer) and the inner layer dielectric layer 436 of grid structure 414, bit line 418, character line 422 block ultraviolet.Wherein composite dielectric layer 408 is positioned in the substrate 400; Grid structure 414 is positioned on the composite dielectric layer 408; Bit line 418 is arranged in the substrate 400 of 414 of grid structures; Character line 422 is positioned on the grid structure 414, and is electrically connected with grid structure 414; Material layer 434 is covered in the substrate 400; Inner layer dielectric layer 436 is positioned on the material layer 434; And comprise connector 444 in inner layer dielectric layer 436 and the material layer 434.
Described according to the foregoing description, the present invention utilizes silicon oxide/silicon nitride/silicon oxide composite bed (charge immersing layer) through after the UV-irradiation, can make electric charge can be absorbed in principle in the silicon oxide/silicon nitride/silicon oxide composite bed (charge immersing layer), with the coding region of silicon oxide/silicon nitride/silicon oxide composite bed (charge immersing layer) as mask-type ROM, on memory cell areas, form one deck then and can prevent the material layer that ultraviolet ray penetrates, when encoding technology, in material layer, form coding window, directly with material layer as encoding mask, irradiating ultraviolet light is with the technology of encoding, whether shine ultraviolet light by memory cell, and electric charge can be absorbed in the silicon oxide/silicon nitride/silicon oxide composite bed (charge immersing layer), store two stepwise bit data " 0 " or " 1 ".
Because, but the present invention directly with the material layer of block ultraviolet as encoding mask, and with technology and the contact hole process integration of coding window, so can reduce light shield one, reduce production costs.
And, but since in the material layer of block ultraviolet, form coding window technology can with the contact hole process integration of peripheral circuit region together, before so the technology of mask-type ROM of the present invention can be parked in contact hole technology, by the time after the client places an order, carry out the contact hole technology of peripheral circuit region and the coding technology of memory cell areas simultaneously, can reduce and ETCD estimated time of commencing discharging.
Though the present invention with embodiment explanation as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is when being as the criterion with claims.
Claims (13)
1. the manufacture method of a mask-type ROM, it is characterized by: this method comprises:
In a substrate, form a charge immersing layer;
Form a plurality of grid structures on this charge immersing layer, this charge immersing layer between each those grid structure and this substrate is as a predictive encoding district;
Form a plurality of bit lines in this substrate between those grid structures;
In this substrate, form a plurality of character lines, and those character lines are electrically connected with those grid structures;
Form a material layer in this substrate, the material of this material layer can prevent that ultraviolet light from penetrating;
On this material layer, form an inner layer dielectric layer;
Form a plurality of coding windows in this inner layer dielectric layer and this material layer, this coding window is positioned at the top in the predictive encoding district of a plurality of desire codings;
Carrying out a coding technology, is encoding mask with this material layer, utilizes this substrate of UV-irradiation, so that those predictive encoding districts of those coding window belows form a plurality of code areas;
Form a connector in those these coding windows in each.
2. the manufacture method of mask-type ROM as claimed in claim 1 is characterized by: wherein comprise a chemical vapour deposition (CVD) anti-reflecting layer in this material layer.
3. the manufacture method of mask-type ROM as claimed in claim 2, it is characterized by: wherein the material of this chemical vapour deposition (CVD) anti-reflecting layer comprises Si
xN
y(OH)
z
4. the manufacture method of mask-type ROM as claimed in claim 1, it is characterized by: wherein this charge immersing layer comprises silicon monoxide/nitrogenize silicon/oxidative silicon composite bed.
5. the manufacture method of mask-type ROM as claimed in claim 4, it is characterized by: wherein this material layer comprises a chemical vapour deposition (CVD) anti-reflecting layer.
6. the manufacture method of mask-type ROM as claimed in claim 5, it is characterized by: wherein the material of this chemical vapour deposition (CVD) anti-reflecting layer comprises SixNy (OH) z.
7. the manufacture method of mask-type ROM as claimed in claim 1, it is characterized by: before wherein forming those character line steps after the step of those bit lines of formation and in this substrate in this substrate between those grid structures, also be included in and form an insulating barrier on those bit lines to fill up the gap between those grid structures.
8. the manufacture method of mask-type ROM as claimed in claim 1 is characterized by: wherein comprise in the step that forms those bit lines:
Carry out an admixture implantation step, inject an admixture in this substrate between those grid structures; And
Carry out an annealing process.
9. the structure of a mask-type ROM, it is characterized by: this structure comprises:
One substrate;
One charge immersing layer, this charge immersing layer are positioned in this substrate;
A plurality of grid structures, those grid structures are positioned on this charge immersing layer, and this charge immersing layer between those grid structures and this substrate is as a plurality of code areas;
A plurality of bit lines, those bit lines are positioned between those grid structures;
One prevents the material layer that ultraviolet ray penetrates, and it is covered in this substrate, and the material of this material layer can prevent that ultraviolet light from penetrating;
One inner layer dielectric layer, this inner layer dielectric layer are positioned on this material layer; And
One connector, this connector are positioned at this inner layer dielectric layer and this material layer, and are positioned at top, a code area.
10. the structure of mask-type ROM as claimed in claim 9, it is characterized by: wherein this material that prevents the material layer that ultraviolet ray penetrates comprises Si
xN
y(OH)
z
11. the structure of mask-type ROM as claimed in claim 9 is characterized by: wherein also comprise a dielectric layer between those grid structures.
12. the structure of mask-type ROM as claimed in claim 9 is characterized by: wherein this charge immersing layer comprises silicon monoxide/nitrogenize silicon/oxidative silicon composite bed.
13. the structure of mask-type ROM as claimed in claim 12 is characterized by: wherein this prevents that the material of the material layer that ultraviolet ray penetrates from comprising SixNy (OH) z.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108452 CN1286167C (en) | 2002-04-01 | 2002-04-01 | Structure of mask ROM and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108452 CN1286167C (en) | 2002-04-01 | 2002-04-01 | Structure of mask ROM and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1449028A CN1449028A (en) | 2003-10-15 |
| CN1286167C true CN1286167C (en) | 2006-11-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02108452 Expired - Fee Related CN1286167C (en) | 2002-04-01 | 2002-04-01 | Structure of mask ROM and method for manufacturing the same |
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| CN (1) | CN1286167C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100341139C (en) * | 2003-12-30 | 2007-10-03 | 旺宏电子股份有限公司 | Method for manufacturing nonvolatile memory element and metal interconnection wire preparing process |
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2002
- 2002-04-01 CN CN 02108452 patent/CN1286167C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN1449028A (en) | 2003-10-15 |
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