CN1201389C

CN1201389C - Making process of charging-preventing nitride ROM

Info

Publication number: CN1201389C
Application number: CN 01132907
Authority: CN
Inventors: 刘振钦; 宋建龙
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2001-09-04
Filing date: 2001-09-04
Publication date: 2005-05-11
Anticipated expiration: 2021-09-04
Also published as: CN1404141A

Abstract

The present invention provides the making method of a nitride read only memory (NROM) for preventing charges from being charged. The method is characterized in that an oxide-nitride-oxide (ONO) layer composed of a bottom oxidation layer, a silicon nitride layer and a top oxidation layer is formed on the surface of a substrate comprising a memorizer area and a perimeter area. Then, multiple bit line masks which are longitudinally arranged are formed on the surface of the ONO layer in the memorizer area, and multiple buried bit lines are formed in the substrate which is not covered by the bit line masks by using first ion implantation treatment. Then, multiple word lines which are transversally arranged and are almost perpendicular to the buried bit lines are formed on the surface of the ONO layer. Finally, a spacer is formed on surrounding side walls of the word lines, and an insulating layer and a protecting layer are orderly formed on the surface of the substrate so as to prevent that the NROM is charged by the charges in semiconductor treatment.

Description

A kind of nitride ROM manufacture method that is used to prevent charge charging

FIELD OF THE INVENTION

The present invention system provides a kind of manufacture method of nitride ROM.

Background note

Nitride ROM (nitride read only memory, NROM) be a kind of semiconductor element that is used for storage data, (memory cell) formed by a plurality of memory cell, and wherein each memory cell all includes MOS transistor and silicon nitride layer.Therefore because silicon nitride layer has the compactness of height, can make via MOS transistor tunnelling (tunneling) to enter in the hot electron trap (trap) in the silicon nitride layer, to reach the purpose of storage data.

Please refer to Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 is the method schematic diagram of a known making nitride ROM.As shown in Figure 1, known nitride ROM system is made in silicon base 12 surfaces.Silicon base 12 is P type silicon base and includes the memory block (memory array) in order to store charge and carry out the surrounding zone (periphery circuit) that logical circuit is controlled.The known formula genealogy of law is carried out traditional oxidation-nitrogenize-oxidation (oxide-nitride-oxide prior to silicon base 12 surfaces, ONO) handle, to form by bottom oxide (bottom oxide) 14, silicon nitride layer 16 and to go up oxide layer (top oxide) the 18 ONO dielectric layers of being formed 19.Form photoresist layer 20 on ONO dielectric layer 19 surfaces then, and carry out a gold-tinted and handle and etch processes,, be used for defining the position of bit line (bit line) so that photoresist layer 20 forms a pattern.

As shown in Figure 2, next utilize photoresist layer 20 as mask (mask), carry out dry etch process to remove last oxide layer 18 and the silicon nitride layer 16 that is not covered by photoresist layer 20, carry out implanting ions subsequently again and handle 22, in silicon base 12, form a plurality of doped regions 24, with bit line, perhaps be called embedded drain electrode (buried drain) as memory.Subsequently photoresist layer 20 is removed fully.

As shown in Figure 3, utilize a thermal oxidation method (thermal oxidation) to form a field oxide 26, as the isolation between each silicon nitride layer 16 in surface, bit line 24 tops.At last as shown in Figure 4, deposit a doped polysilicon layer 28 again, as word line.

Known nitride ROM is after word line completes; for avoiding element in follow-up chemical deposition processing or etch processes, to be subjected to ultraviolet irradiation or producing plasma damage; therefore can form protective layer 29 is covered in each word line surface; and sidewall all is formed with wall (spacer) 27 around each word line, as shown in Figure 5.Yet because the ONO dielectric layer 19 of protective layer 29 and this nitride ROM is directly to contact; so follow-up free electron that in chemical deposition processing or etch processes, is subjected to the part that ultraviolet irradiation produces; will pass protective layer 29 and enter in the ONO dielectric layer 19, and then influence the electrical performance of this nitride ROM.

Summary of the invention

Therefore, the object of the present invention is to provide a kind of manufacture method of nitride ROM (NROM) of improvement, to avoid this nitride ROM in subsequent treatment, to be subjected to ultraviolet ray (UV light) irradiation or to produce plasma damage (plasma damage).

In most preferred embodiment of the present invention, be the substrate that provides the surface to include memory block and surrounding zone earlier, (ONO) layer of oxidation-nitrogenize-oxidation (oxide-nitride-oxide) that oxidation (top oxide) layer is constituted on this substrate surface forms by end oxidation (bottom oxide) layer, silicon nitride layer and then.Then this ONO laminar surface in this memory block forms many bit line masks of vertically arranging (bit line mask), carry out first implanting ions subsequently and handle, in this substrate that is not covered, to form many buried bit lines (buried bit line) by this bit line mask.After removing this bit line mask, on this ONO laminar surface, form many transversely arranged and be close to vertical word line with these many buried bit lines.Form sacrifice layer in this substrate surface at last, and this sacrifice layer is carried out an etch-back handle, form wall (spacer) with sidewall around this word line respectively, and form barrier layer and protective layer in regular turn in this substrate surface.

Because the nitride ROM surface that the present invention makes is formed with barrier layer and protective layer in regular turn; therefore can avoid this nitride ROM in subsequent treatment, to be subjected to ultraviolet ray (UV light) irradiation or generation plasma damage (plasma damage); this barrier layer more can be isolated the ONO dielectric layer of this protective layer and this nitride ROM effectively simultaneously; avoiding this protective layer directly to contact, can suppress further therefore that free electron in this protective layer enters this ONO dielectric layer and the electrical performance that influences this nitride ROM with this ONO dielectric layer.

Detailed description of the invention

Please refer to Fig. 6 to Figure 10, Fig. 6 to Figure 10 makes the generalized section of nitride ROM for the present invention.As shown in Figure 6, nitride ROM of the present invention is substrate 32 surfaces that are made in semiconductor wafer 30, and substrate 32 surface definition have memory block and surrounding zone.In preferred embodiment of the present invention, substrate 32 is a P type silicon base.Yet the present invention is not limited thereto, and in other embodiments of the invention, substrate 32 can also be the silicon chip on the insulator (silicon-on-insulator, SOI) substrate.Emphasis of the present invention for convenience of description, Fig. 6 to Figure 10 only shows the section of nitride ROM of the present invention memory block.As shown in Figure 6, at first form a thickness and be about 150 to 250 dust (angstrom in substrate 32 surfaces, A) ONO dielectric layer 39, ONO dielectric layer 39 are to be about the last oxide layer 38 that the bottom oxide 34 of 50 to 150 dusts, silicon nitride layer 36 that a thickness is about 20 to 150 dusts and a thickness is about 50 to 150 dusts by a thickness to be formed.

Next adjust the step of surrounding zone element start voltage (threshold voltage), at first 39 surfaces of the ONO dielectric layer in the memory block form the mask (not shown), and carry out implanting ions and handle, to adjust, remove this mask at last not by the dopant concentration in the substrate 32 that mask covered.Subsequently as shown in Figure 7, form photoresist layer 40 in ONO dielectric layer 39 surfaces, and carry out gold-tinted and handle and etch processes, make photoresist layer 40 form pattern, be used for defining the position of bit line.Utilize photoresist layer 40 as the bit line mask then, vertically be arranged in ONO dielectric layer 39 surfaces.Then carry out implanting ions and handle 42, utilize arsenic ion (arsenic, As) or other N types mix the substrate 32 that is covered by photoresist layer 40 do not mixed, in substrate 32, to form the doped region 44 that a plurality of N types mix, as the embedded bit line (buried bit line) of memory.Handle in 42 at implanting ions, a typical arsenic ion dosage is about every square centimeter of 1E15 to 1E16 atom (atoms/cm2) implantation energy and is about 20 to 80KeV, is preferably 50KeV.Then carry out the prompt tempering that a temperature is about 800 to 1000 ℃ and handle, be implanted in admixture in the substrate 32 with activation.Again photoresist layer 40 is removed fully subsequently.

As shown in Figure 8, again in semiconductor wafer 30 surface depositions one doped polysilicon layer 46, as word line.This word line is transversely arranged in semiconductor wafer 30 surfaces, and is close to vertical overlapping Rankine-Hugoniot relations up and down with doped region 44 formation one, as shown in Figure 9.

At last as shown in figure 10, Figure 10 is the profile along Fig. 9 Vertical Centre Line A-A.Form a sacrifice layer (not shown) that is constituted by the nitrogen silicon compound in substrate 32 surface, and this sacrifice layer carried out an etch-back handle, until substrate 32 surfaces, with in and respectively this word line around sidewall form a wall (spacer) 47.The last protective layer 50 that is constituted by the nitrogen silicon compound by barrier layer 48 that silicon oxide compound constituted and that forms in regular turn in substrate 32 surfaces.Protective layer 50 is to be used for avoiding this nitride ROM (NROM) to be subjected to ultraviolet ray (UV light) irradiation or generation plasma damage (plasma damage) in a subsequent treatment; and be formed at barrier layer 48 between protective layer 50 and this nitride ROM; then be to be used for preventing that protective layer 50 from contacting with silicon nitride layer 36; avoiding the follow-up free electron that in chemical deposition processing or etch processes, is subjected to the part that ultraviolet irradiation produced to pass protective layer 50 and to enter in the ONO dielectric layer 39, so influence this nitride ROM (NROM) electrically.

Compared to known nitride ROM manufacture method; the present invention system utilizes a chemical vapour deposition (CVD) mode to form a barrier layer; to isolate the ONO dielectric layer of this protective layer and this nitride ROM; owing to this protective layer may be subjected to the free electron that ultraviolet irradiation produces in follow-up chemical deposition processing or etch processes; therefore this barrier layer can stop the free electron in this protective layer to enter this ONO dielectric layer; reach avoid this nitride ROM in handling by the effect of charge charging, and then improve this nitride ROM hold patience (endurance) and reliability (reliability).

The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Illustrated simple declaration

Fig. 1 to Fig. 5 is the method schematic diagram of known making nitride ROM.

Fig. 6 to Figure 10 makes the method schematic diagram of nitride ROM for the present invention.

Illustrated symbol description

12 silicon base, 14 bottom oxides

Oxide layer on 16 silicon nitride layers 18

19ONO dielectric layer 20 photoresist layers

22 implanting ions are handled 24 doped regions (bit line)

26 field oxides, 27 walls

28 doped polysilicon layers (word line), 29 protective layers

32 substrates of 30 semiconductor wafers

34 bottom oxides, 36 silicon nitride layers

Oxide layer 39ONO dielectric layer on 38

40 photoresist layers (bit line mask), 42 ion implantations are handled

44 doped regions (bit line)

46 doped polysilicon layers (word line), 47 walls

48 barrier layers, 50 protective layers

Claims

1. nitride ROM manufacture method that is used to prevent charge charging, this method includes the following step:

Provide substrate, and this substrate surface includes memory block and surrounding zone;

Form the oxidation-nitrogenize-oxide layer that is constituted by bottom oxide, silicon nitride layer and last oxide layer in this substrate surface;

This oxidation-nitrogenize in this memory block-oxide layer surface forms many bit line masks of vertically arranging;

Carry out first implanting ions and handle, in this substrate that is not covered, to form many buried bit lines by this bit line mask;

Remove this bit line mask;

On this oxidation-nitrogenize-oxide layer surface, form many transversely arranged and be close to vertical word line with these many buried bit lines;

Form sacrifice layer in this substrate surface, and this sacrifice layer is carried out an etch-back handle,, form wall with sidewall around this word line respectively until this substrate surface; And

Form barrier layer and protective layer in regular turn in this substrate surface.

2. according to the process of claim 1 wherein that this method before forming this multiple bit lines mask, still includes the following step:

Form mask to this oxidation-nitrogenize-oxide layer surface that is less than in this memory block;

Carry out second implanting ions and handle, to adjust not by the dopant concentration in this substrate that this mask covered; And remove this mask.

3. according to the process of claim 1 wherein that this bottom oxide thickness is between 50 to 150 dusts, this silicon nitride layer thickness is between 20 to 150 dusts, is between 50 to 150 dusts and should go up oxidated layer thickness.

4. according to the process of claim 1 wherein that this bit line mask is made of photoresist.

5. according to the process of claim 1 wherein that this substrate is at the bottom of the silicon wafer-based on silicon base or the insulator.

6. according to the process of claim 1 wherein that this sacrifice layer is made of the nitrogen silicon compound.

7. according to the process of claim 1 wherein that this protective layer is made of the nitrogen silicon compound.

8. according to the process of claim 1 wherein that this barrier layer is made of Si oxide.