CN1258218C - Method for mfg. system integrated chip - Google Patents
Method for mfg. system integrated chip Download PDFInfo
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- CN1258218C CN1258218C CN 01130312 CN01130312A CN1258218C CN 1258218 C CN1258218 C CN 1258218C CN 01130312 CN01130312 CN 01130312 CN 01130312 A CN01130312 A CN 01130312A CN 1258218 C CN1258218 C CN 1258218C
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Abstract
The present invention provides a method for making a system organized chip (SOC) of a nitride read only memory (NROM) by using the NROM to process to establish a read only memory (ROM). The method comprises the following steps: an ONO dielectric layer is firstly formed on the surface of a substrate and is processed by yellow light and ion implantation; then, the ONO dielectric layer on a peripheral circuit zone is removed; the threshold voltage of a transistor of the circumference circuit zone is adjusted; the ONO dielectric layer on an ROM zone is removed, and a thermal oxidation method is implemented; then, various word lines of a memory zone and various grids of transistors of the peripheral circuit in the peripheral circuit zone are formed; thus, at least one NROM is formed on a nitride memory zone, and a high starting voltage element and a low starting voltage element are simultaneously formed on the ROM zone; finally, implantation treatment is implemented by using an ROM code.
Description
Technical field
The invention provides a kind of accumulator system integral chip (system on chip, SOC), refer to that especially a kind of nitride ROM (NROM) that utilizes handles to set up the manufacture method of read-only memory (ROM) and the system combination chip (SOC) of nitride ROM.
Background technology
Read-only memory (Read only memory, ROM) element is a kind of semiconductor element that is used for storage data, (memory cell) formed by a plurality of memory cells, nowadays has been widely used in the data storing and the memory of computer.According to the data storing mode, read-only memory can be divided into shielded read-only memory (mask ROM), programmable read only memory (Programable ROM, PROM), EPROM (Erasable Programmable Read Only Memory) (Erasable programmble ROM, EPROM), EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically erasable programmable ROM, EEPROM), nitride ROM (nitride read only memory, NROM) and flash memory (flash ROM) wait several, in case its characteristics are for after data or data are stored into, data that is deposited in or data can not disappear because of the interruption of power supply supply, therefore are called nonvolatile memory (non-volatilememory) again.
And the principal character of nitride ROM wherein (NROM) is to use the insulation dielectric layer of silicon nitride as electric charge capture medium (charge trapping medium).Because silicon nitride layer has the compactness of height, therefore can make and wear the hot electron that (tunneling) enter in the silicon nitride layer then via MOS transistor and be captured on (trap) wherein, and then form a CONCENTRATION DISTRIBUTION heterogeneous, with the speed of accelerating reading of data and avoid leakage current.As for flash memory, then use unsteady gate pole (floating gate) store charge of polysilicon or metal, therefore also can many again gate poles except general control gate pole (control gate).It is simple that the former has manufacturing process, the advantage that cost of manufacture is low.And the structure of latter's gate pole-intermediate dielectric layer-control gate pole because essential making is floated, and the quality of the material in this three-decker is very important, must cooperate with suitable processing, so manufacturing process is more complicated, and spent cost is also higher.
And in present electronics industry, read-only memory and nonvolatile memory often need be present among the various products simultaneously, be made in the mode of same chip simultaneously compared to two kinds of elements, when if two kinds of elements are made on two chips respectively, higher cost also can be expended simultaneously in the more space that not only can account for.Therefore, at United States Patent (USP) the 5th, 403, in No. 764, Yamamoto et al. can propose a kind of method, in the manufacturing process of flash memory component, part is arranged in the flash memory component of read-only memory district (ROMregion), the mode of (ion implantation) of injecting with ion is injected read-only memory sign indicating number (ROM code), promptly finishes so-called write-in program, and then continues to finish flash memory processes.Therefore, in flash memory chip, can set up the read-only memory of part.
Please refer to Fig. 1 to Fig. 5, Fig. 1 to Fig. 5 includes the method schematic diagram of the flash memory chip 10 of read-only memory 24 for known making one.As scheme shown in the l, known making one includes the method for the flash memory chip 10 of read-only memory 24, be that a semiconductor chip 11 that includes P type silicon base (sillicon base) 12 is provided earlier, then utilize a temperature to be about 1100 ℃, time is about 90 minutes thermal oxidation (thermal oxidation) processing, not by such as silicon nitride (silicon nitride, Si
3N
4) surface of oxidation barrier film (oxidation-protectivefilm) silicon base 12 that (not shown) covered of layer, form a plurality of thickness and reach thousands of dusts (angstrom, silicon dioxide A) (silicon dioxide, SiO
2) layer 14, and this silicon dioxide layer 14 be also referred to as field oxide (field oxide layer, FOX).After finishing, removing remaining silicon nitride layer (not shown) again, 14 of silicon dioxide layer 14 and silicon dioxide layers, also is between each FOX only, keeps a very thin silicon oxide layer 16.In other words, (localoxidation LOCOS) carries out isolation between the follow-up transistor AND gate transistor of finishing promptly to utilize the selective oxidation method.
Then as shown in Figure 2, then carry out an ion in the read-only memory zone 18 on flash memory chip 10 and inject and handle (ion implantation process), this ion injects that to handle be that to utilize acceleration energy be that 40～50keV, dosage are 1E12 to 3E12/cm
2Boron (Boron) ion, to inject ion concentration be 10 to form one
16～10
17/ cm
3A P+ type doped region 22.This ion injects the purpose of handling, be starting voltage (the threshold voltage that is used for adjusting the first read-only memory (not shown) in the read-only memory zone 18, Vth) to first particular value, so that being adjusted to, the starting voltage of one first read-only memory (not shown) is approximately 1V, to deposit the data for " 1 " in.
As shown in Figure 3, carry out one first gold-tinted and handle, in the read-only memory zone 18 on flash memory chip 10, to form read-only memory 26 part in addition that starting voltage is second particular value, and the part beyond the read-only memory zone 18, form one first shielding 31.Then on flash memory chip 10, carry out an ion and inject processing (ion implantation process).This ion injects that to handle be that to utilize acceleration energy be that 40～50keV, dosage are 5E12 to 1E13/cm
2Boron (Boron) ion, last to inject ion concentration be 10 to form one
17～10
18/ cm
3The 2nd P+ type doped region 32.This ion injects the purpose of handling, be starting voltage (the threshold voltage that is used for adjusting the second read-only memory (not shown) in the read-only memory zone 18, Vth) to first particular value, so that being adjusted to, the starting voltage of the second read-only memory (not shown) is approximately 7V, to deposit the data for " 0 " in.
Then as shown in Figure 4, on flash memory chip 10, deposit one first polysilicon layer 34, in regular turn by intermediate insulating layer 36 and one second polysilicon layer 38 that silicon nitride or silica constituted.And then carry out one second gold-tinted and handle, to form the dual gate pole 39 of first, second read- only memory 24,26 and flash memory 40.Though generally speaking, the gate structure of first, second read- only memory 24,26 is an individual layer, does not need to use three layers dual gate pole 39 structures, and in the prior art, in order to reduce treatment step, so all gate poles are all finished in same treatment step.
As shown in Figure 5, utilize one the 3rd shielding (not shown), and carry out a phosphorus (phosphorous) ion and inject processing, with in the both sides of the dual gate pole 39 of first, second read- only memory 24,26, each forms a N+ type source electrode 41, drain electrode 42, to finish the making of first, second read-only memory 24,26.Utilize one the 4th shielding (not shown) at last, and carry out another phosphorus (phosphorous) ion and inject to handle, with on the both sides of the dual gate pole 39 of flash memory 40, each forms a N+ type source electrode 43, drain electrode 44, to finish the making of flash memory 40.Thus, only need are in the manufacturing process of the flash memory of general standard, add two treatment steps of adjusting starting voltage, not only the read-only memory on the flash memory chip 10 24,26 is written into the data of " 1 " or " 0 ", and flash memory 40 also is done simultaneously.
Yet the flash memory chip in the known technology just comprises read-only memory partly, does not reach the purpose of system combination chip.And the cost of manufacture of flash memory is higher, is not suitable for the making of system combination chip.Therefore how to develop and produce a kind of system combination chip, with element and the processing thereof that utilizes lower cost, can make read-only memory and nitride ROM simultaneously on same chip, can omit the electrical write step that also needs after general nonvolatile memory is finished again, just become crucial problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of making accumulator system integral chip (system onchip, SOC) method refers to that especially a kind of nitride ROM (NROM) that utilizes handles to set up the manufacture method of read-only memory (ROM) and the system combination chip (SOC) of nitride ROM.
In most preferred embodiment of the present invention, this system combination chip is to be located on the surface of semiconductor chip, and utilize the processing of nitride ROM (NROM), make read-only memory (ROM) and nitride ROM simultaneously, the production method of this system combination chip includes the following step: at this substrate surface, form " bottom oxide-silicon nitride layer-last oxide layer " (ONO) dielectric layer at this substrate surface, utilize one first gold-tinted to handle and inject processing, in substrate, to form a plurality of N type doped regions and each bit line with one first ion.The ONO dielectric layer on the periphery circuit region is removed in etching, and carries out one second ion and inject processing, to adjust the transistorized starting voltage (thresholdvoltage) of periphery circuit region.Carry out one the 3rd etch processes, to remove the ONO dielectric layer in the read-only memory district, carry out a thermal oxidation method (thermal oxidation) again, bury drain electrode oxide layer (buried drain oxide layer) to form one, and on read-only memory district and periphery circuit region, form the gate oxide of low starting voltage element, high starting voltage element and peripheral circuit transistor respectively on each bit line surface.Utilize one second gold-tinted and one the 4th etch processes, each gate pole with each peripheral circuit transistor of forming each word line in the memory areas and periphery circuit region simultaneously, and on the nitride memory areas, form mononitride read-only memory at least, and form a low starting voltage element and a high starting voltage element respectively at low starting voltage (lowVth) element region and high starting voltage (high Vth) element region in read-only memory district.Utilize one the 3rd ion to inject and handle, to adjust the starting voltage of this high starting voltage element.The 3rd ion injects to handle and comprises that carrying out one the 4th gold-tinted handles, and to form one the 4th photoresist layer of patterning, covers low starting voltage element, this non-volatile memory region and this periphery circuit region of being somebody's turn to do in this read-only memory district; Also comprise and firmly go into p type impurity in this high starting voltage element,, finish the read-only memory sign indicating number and handle and remove the 4th photoresist layer to adjust the starting voltage of this high starting voltage element.Because the existence of high starting voltage element and low starting voltage element is arranged in the read-only memory district, can be used as read-only memory and use.Therefore, on this system combination chip,, also comprise read-only memory and nitride ROM except comprising peripheral circuit transistor.
Because the present invention utilizes the ion of nitride ROM and adding to inject to handle, and makes read-only memory and nitride ROM simultaneously on the same system integral chip.Therefore, after not only can avoiding general nonvolatile memory to finish, also need make spent time and manpower in the mode that electrically writes, what caused is not suitable for mass-produced problem, can keep producing system combination chip cheaply under the simple principle of processing again simultaneously.
Description of drawings
Fig. 1 to Fig. 5 includes the method schematic diagram of the flash memory chip of read-only memory for known making one.
Fig. 6 to Figure 12 embeds the method schematic diagram of the system combination chip of nitride ROM and shielded read-only memory for the present invention.
In Figure of description, 10 represent flash memory chip, 11 represent semiconductor chip, 12 represent silicon base, 14 represent silicon dioxide layer, 16 represent silicon oxide layer, 18 represent the read-only memory zone, 22 represent a P+ type doped region, 24 represent first read-only memory, 26 represent second read-only memory, and 31 represent first shielding, and 32 represent the 2nd P+ type doped region, 34 represent first polysilicon layer, 36 represent intermediate insulating layer, and 38 represent second polysilicon layer, the dual gate pole of 39 representatives, 40 represent flash memory, 41 represent source electrode, 42 representative drain electrodes, and 43 represent source electrode, 44 representative drain electrode representative system integral chips, 101 represent semiconductor chip, and 102 represent P type silicon base, and 103 represent periphery circuit region, 104 represent memory areas, 105 represent the nitride ROM district, and 106 represent the read-only memory district, the low starting voltage element region of 107 representatives, the high starting voltage element region of 108 representatives, 109 represent doped region, and 110 represent the shallow isolating trough zone, and 112 represent bottom oxide, 114 represent silicon nitride layer, oxide layer is gone up in 116 representatives, and 118 represent the ONO dielectric structure, and 121 represent first photoresist layer, 122 represent bit line, 123 represent P-type pocket doped region, and 124 represent P-type pocket doped region, and 126 represent active region, the drain electrode oxidation is buried in 128 representatives, 134 represent word line, and 136 represent peripheral circuit transistor, and 138 represent gate pole, 142 represent nitride ROM, the low starting voltage element of 144 representatives, the high starting voltage element of 146 representatives, 147 represent light dope source electrode/drain electrode, 148 represent clearance wall, 149 represent source electrode, 150 representative drain electrodes, and 152 represent the 3rd photoresist layer.
Embodiment
Please refer to Fig. 6 to Figure 12, Fig. 6 to Figure 12 embeds the method schematic diagram of the system combination chip 100 of nitride ROM and shielded read-only memory for the present invention.As shown in Figure 6, the manufacture method of system combination chip 100 of the present invention, be that a semiconductor chip 101 that includes P type silicon base (siliconbase) 102 is provided earlier, include a periphery circuit region 103 and a memory areas 104 on the semiconductor chip 101, include height in the periphery circuit region 103, low-voltag transistor element (not shown), capacity cell (not shown) and resistive element (not shown) etc., then include a mononitride read-only memory district 105 and a read-only memory district 106 in the memory areas 104, and include at least one low starting voltage (low threshold in the read-only memory district 106 again, low Vt) element region 107 and a high starting voltage (high threshold, high Vt) element region 108.In the present invention because the non-invention emphasis of element in the periphery circuit region 103, so only do recapitulative narration, and in illustrating, with a single high voltage peripheral circuit transistor as representative.
At first can carry out the processing of part periphery circuit region 103 earlier, utilize a N type ion to inject and handle and P type ion injection processing, to form the N type well (not shown) and the p type wells (not shown) of periphery circuit region 103 high voltage appearance transistor unit (not shown)s respectively, and in the present invention for convenience's sake, only represent with an impure well (well) 109.Then form a plurality of insulants,, and define the active region of each element with isolated periphery circuit region 103, nitride ROM district 105 and read-only memory district 106 respectively on substrate 102 surfaces.Wherein, insulant can be a shallow isolating trough zone, or is a field oxide, then illustrates as representative with shallow isolating trough zone 110 in diagram.
As shown in Figure 7, utilize the low-temperature oxidation (lowtemperature oxidation) of 750 ℃～1000 ℃ of temperature ranges to handle subsequently, (angstrom, oxide layer A) are used for being used as bottom oxide 112 to form one 50～150 dusts on silicon base 102 surfaces.Then carry out a low pressure gas phase deposition (low pressure chemical vapor deposition, LPCVD) handle, unsteady gate pole and the thickness of being used as this nitride ROM at bottom oxide 112 surface depositions one are the silicon nitride layer 114 of 100～300 dusts (A), are used as and are detained electronic shell (charge trapping layer).Last again in 950 ℃ hot environment, carry out 30 minutes structures of a temper with repairing silicon nitride layer 114, and feed steam to carry out wet oxidation, with form on silicon nitride layer 114 surface thickness be 50～200 dusts (A) contain oxygen silicide (silicon oxy-nitride) layer, as last oxide layer 116.Wherein, in the generative process of oxide layer 116, rough meeting consumes the silicon nitride layer 114 of 25～100 dusts (A) on this, and is formed at silicon base 102 lip-deep bottom oxides 112, silicon nitride layer 114 and goes up oxide layer 116, is collectively referred to as ONO dielectric structure 118.
Then as shown in Figure 8, form one first photoresist layer 121 on ONO dielectric structure 118 surfaces, and carry out one first gold-tinted and handle and etch processes, in first photoresist layer 121, to form the position that a predetermined pattern defines bit line (bit line).Next the pattern that utilizes first photoresist layer 121 is as shielding (mask), carry out a dry etch process to remove last oxide layer 116, silicon nitride layer 114 and the bottom oxide 112 that is not covered fully by first photoresist layer 121, promptly all ONO dielectric structures 118, or only remove last oxide layer 116, the silicon nitride layer 114 that is not covered, and bottom oxide 112 to one predetermined thickness of etching part by photoresist layer 121.Carrying out an ion concentration subsequently is 2～4E15/cm
2And arsenic (arsenic) ion that energy is about 50Kev injects processing, to form a plurality of N in silicon base 102
+The type doped region as the bit line 122 of memory, perhaps be called embedded drain electrode (buried drain), and two adjacent doped regions promptly defines a passage, and the distance of two adjacent doped regions is passage length (channel length).
Then carry out a rake angle ion and inject processing, form a P with a side at each bit line 122
-Type pocket doped region 123.And then carry out a rake angle ion and inject processing, form a P with opposite side at each bit line 122
-Type pocket doped region 124.These two angled ion are injected and are handled except the incident direction difference, and all the other ion injection parameters are all identical haply.It is to utilize BF that this two angled ion is injected processing
2+Be admixture, its dosage is about 1E13 to 1E15ions/cm
2, energy is about 20 to 150KeV, and the incidence angle between the silicon base 102 is about 20 to 45 °.And this two rake angle is handled, and also can carry out before the ion that forms bit line 122 injects processing.In this condition and range, inject the BF of silicon base 102
2+The admixture Cmax appears at the silicon base 102 that dark about 1000 Izod right sides are arranged in the passage below approximately, and the horizontal range of below, injection channel is about hundreds of to 1000 dusts.Form P
-The purpose of type doped region 123,124, being to provide a high electric field region at an end of passage, and high electric field region can improve hot electron (hot carrier) effect, increase the speed when passing through passage when electronics writes (program), in other words be accelerated electron, make more electronics can obtain enough kinetic energy and pass bottom oxide 112 and enter in the silicon nitride layer 114, and then promote and write efficient via collision or scattering effect.
Then as shown in Figure 9, remove first photoresist layer 121.Then on system combination chip 100, carry out one second dry etch process, to remove the ONO dielectric structure 118 in the periphery circuit region 103, utilize a light shield (not shown) as shielding subsequently, carry out one first ion and inject processing, the ion that carries out starting voltage adjustment (threshold voltageadjustment) with the active region 126 to the peripheral circuit transistor (not shown) injects.And the N type ion of aforementioned N type well (not shown) that is used for forming periphery circuit region 103 high voltage appearance transistor unit (not shown)s and p type wells (not shown) injects and handles and P type ion injects and handles, and also can inject at first ion and just carry out before handling.
As shown in figure 10, carry out one the 3rd etch processes, removing the ONO dielectric structure 118 in the read-only memory district 106, and a clean is carried out on the surface in periphery circuit region 103 and read-only memory district 106.Carrying out the purpose of this step, is to form a gate oxide in subsequent treatment in addition, to replace ONO dielectric structure 118.Carrying out a thermal oxidation (thermal oxidation) then handles, bury drain electrode oxide layer (buried drain oxidelayer) 128 to form one, and utilize the high temperature heat of this thermal oxidation to activate admixture in each bit line 122 on each bit line 122 surfaces.In addition, this thermal oxidation can not be coated with the zone of ONO dielectric structure 118 simultaneously on semiconductor chip 101 surfaces yet, forming a thickness is the gate oxide 132 of 100～250 dusts, and there has been the part of ONO dielectric layer 118 in the memory areas 104 on the semiconductor chip 101, can not generate gate oxide 132 again.That is to say, this thermal oxidation can form the gate oxide 132 of low starting voltage element (not shown), high starting voltage element (not shown) and peripheral circuit transistor (not shown) respectively on read-only memory district 106 and periphery circuit region 103.
What deserves to be mentioned is, after above-mentioned processing, also can add several N type wells, p type wells injection processing again, and the cleaning of several repetitiousness and etching and thermal oxidation, to make the peripheral circuit transistor (not shown) of different voltages in the periphery circuit region on semiconductor chip 101 103.Then as shown in figure 11, the composite bed that includes multi-crystal silicification metal object (polysilicide) and polysilicon in ONO dielectric structure 118, the surface deposition one polysilicon layer (not shown) or of burying drain electrode oxide layer 128 and gate oxide 132.Carry out one second gold-tinted then and handle, form second photoresist layer 133 of a patterning on this polysilicon layer surface, to define the position of the gate pole of each peripheral circuit transistor in word line in the memory areas 104 and the periphery circuit region 103.
Carry out one the 4th etch processes subsequently, remove the polysilicon layer do not covered, to form the gate pole 138 of the peripheral circuit transistor 136 in word line 134 and the periphery circuit region 103 in the memory areas 104 simultaneously by this second photoresist layer 133.Remove second photoresist layer 133 at last, and in nitride ROM district 105, form mononitride read-only memory 142 at least, and form a low starting voltage element 144 and a high starting voltage element 146 respectively at low starting voltage (low Vth) element region 107 and high starting voltage (high Vth) element region 108 in read-only memory district 106.
As shown in figure 12, then carry out some treatment steps, with in the periphery circuit region 103 of system combination chip 100, continue to finish peripheral circuit transistor 136 uncompleted treatment steps, for example light dope source electrode/drain electrode (lightly doped drain, LDD) 147, the making of clearance wall (spacer) 148 and source/drain (S/D) 149,150.Utilize one the 3rd photoresist layer 152 then, cover low starting voltage (low Vth) element area 107 and whole periphery circuit region 103 and nitride ROM district 105 in the read-only memory district 106, carry out the ion injection processing that another starting voltage is adjusted then, p type impurity is injected high starting voltage (high Vth) element area 108 in the read-only memory district 106, this step also can be described as the injection of read-only memory sign indicating number (ROM code), in order to adjust the starting voltage of high starting voltage element 146 in the read-only memory district 106.Remove the 3rd photoresist layer 152 at last.Wherein, the 3rd photoresist layer 152 can cover together with burying drain electrode 128, also can expose and bury drain electrode 128.
Because the existence of high starting voltage element 146 and low starting voltage element 144 is arranged in the read-only memory district 106, so after a while when chip moves, can represent 0﹠amp respectively; 1, or 1﹠amp; 0, store data or the purpose of data to reach.After the injection of finishing read-only memory sign indicating number (ROM code), then on system combination chip 100, carry out inner metal dielectric layer (inter-metal dielectric, ILD) (not shown), metal level (metal layer) (not shown) and contact hole (contacthole) (not shown), making step with contact plunger (contact plug) (not shown), to finish whole processing of system combination chip 100, and on this system combination chip 100, except comprising some peripheral circuits that comprise peripheral circuit transistor 136, also comprise shielded read-only memory and nitride ROM.
Because the production method of system combination chip provided by the invention, be to utilize the ion of nitride ROM and adding to inject processing, make read-only memory and nitride ROM simultaneously on same chip, like this, after not only can avoiding general nonvolatile memory to finish, also need make spent time and manpower and be not suitable for mass-produced problem in the mode that electrically writes.Simultaneously because the processing of nitride ROM is simple, cost of manufacture is approximately only suitable with shielded read-only memory, the flash memory and function can match in excellence or beauty, so utilize nitride ROM, set up the mode of the system combination chip of read-only memory and nitride ROM, significantly significantly reduce cost of manufacture and obviously simplify the making flow process than prior art.
The mode that comprises read-only memory compared to known making flash memory chip, the present invention utilizes nitride ROM and ion to inject and handles, set up the mode of the system combination chip of read-only memory and nitride ROM, after not only can avoiding general nonvolatile memory to finish, also need make in the mode that electrically writes, too many because of spent time and manpower, be not suitable for mass-produced problem.Simultaneously more can be under function match in excellence or beauty the prerequisite of flash memory, reduce cost of manufacture significantly and obviously simplify and make flow process.
The above only is the preferred embodiments of the present invention, and all various variations and modifications of doing according to claim of the present invention all should belong to the covering scope of patent of the present invention.
Claims (8)
1. manufacture method of utilizing nitride ROM to set up the system combination chip of read-only memory and nonvolatile memory, this system combination chip comprises the substrate that a definition has a memory areas and a periphery circuit region, and this memory areas comprises a non-volatile memory region and a read-only memory district, and this read-only memory district includes an at least one low starting voltage element region and a high starting voltage element region, and the manufacture method of this system combination chip includes the following step:
Form impure well at periphery circuit region;
Form a plurality of insulants at this substrate surface, isolating this periphery circuit region, this non-volatile memory region and this read-only memory district respectively, and define the active region of each element;
Form a dielectric structure layer that oxide layer constituted on by a bottom oxide, a silicon nitride layer and at this substrate surface;
This bottom oxide-silicon nitride layer-on oxide layer dielectric layer surface form one first photoresist layer, and carry out that one first gold-tinted is handled and etch processes to define the position of many bit lines;
Utilize this first photoresist layer to carry out one first etch processes, to remove this bottom oxide-silicon nitride layer-last oxide layer dielectric layer that is not covered by this first photoresist layer as shielding;
Carry out one first ion and inject processing, in this substrate, to form a plurality of N type doped regions, as respectively this bit line in this memory areas;
Carry out a rake angle ion and inject processing,, carry out a rake angle ion again and inject processing, form a P type doped region with opposite side at each bit line to form a P type doped region at each bit line;
Remove this first photoresist layer;
Carry out one second etch processes, remove this bottom oxide-silicon nitride layer-last oxide layer dielectric layer on this periphery circuit region;
Carry out one second ion and inject processing, be used for adjusting the transistorized starting voltage of this periphery circuit region;
Carry out one the 3rd etch processes, remove this bottom oxide-silicon nitride layer-last oxide layer dielectric layer in this read-only memory district;
Carry out a thermal oxidation method, bury the drain electrode oxide layer to form one, and on this read-only memory district and this periphery circuit region, form the gate oxide of this low starting voltage element, this high starting voltage element and this peripheral circuit transistor respectively on this bit line surface respectively;
Form a polysilicon layer and one second photoresist layer in regular turn at this substrate surface, and utilize one second gold-tinted to handle, with the position of a plurality of gate poles of in this second photoresist layer, defining many word lines in this memory areas and respectively this peripheral circuit transistor in this periphery circuit region;
Carry out one the 4th etch processes, remove this polysilicon layer that is not covered by this second photoresist layer, respectively this gate pole with respectively this peripheral circuit transistor of forming respectively this word line in this memory areas and this periphery circuit region simultaneously, remove second photoresist layer, and on this non-volatile memory region, form mononitride read-only memory at least, and form a low starting voltage element and a high starting voltage element respectively at this low starting voltage element region and this high starting voltage element region in this read-only memory district;
Form the 3rd photoresist layer;
Carry out one the 3rd ion and inject processing, be used for adjusting the starting voltage of this high starting voltage element; And
Remove the 3rd photoresist layer.
2. the method for claim 1, wherein this substrate is a silicon base.
3. the method for claim 1, wherein this bottom oxide be utilize the low-temperature oxidation of 750 ℃～1000 ℃ of temperature ranges handle form, and the thickness of this bottom oxide is 50～150 dusts.
4. the method for claim 1, wherein this silicon nitride layer be utilize a low pressure gas phase deposition handle form, be used for being used as the unsteady gate pole of this nitride ROM, and the thickness of this silicon nitride layer is 100～300 dusts.
5. the method for claim 1, wherein should go up oxide layer is to utilize a wet oxidation to handle institute to form, and is somebody's turn to do upward that thickness of oxide layer is 50～200 dusts.
6. the step that the method for claim 1, wherein forms impure well in this periphery circuit region is injected the processing realization by one the 4th ion.
7. the method for claim 1, wherein this high starting voltage element and output signal that should low starting voltage element are to be used for representing respectively 0 or 1 or 1 or 0, to store a specific data or data.
8. the method for claim 1, wherein this read-only memory district is a shielded read-only memory district.
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| CN 01130312 CN1258218C (en) | 2001-11-20 | 2001-11-20 | Method for mfg. system integrated chip |
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| US20060223267A1 (en) * | 2005-03-31 | 2006-10-05 | Stefan Machill | Method of production of charge-trapping memory devices |
| CN102054679B (en) * | 2009-11-09 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Method for etching interpoly dielectric |
| US9805806B2 (en) * | 2015-10-16 | 2017-10-31 | Ememory Technology Inc. | Non-volatile memory cell and method of operating the same |
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